Through Same Mask Opening Patents (Class 438/377)
  • Patent number: 9236248
    Abstract: A (000-1) C-plane of an n? type silicon carbide substrate having an off-angle ? in a <11-20> direction is defined as a principal plane, and a periphery of a portion of this principal surface layer defined as an alignment mark is selectively removed to leave the convex-shaped alignment mark. The alignment mark has a cross-like plane shape such that two rectangles having longitudinal dimensions tilted by 45 degrees relative to the <11-20> direction are orthogonal to each other. When a film thickness of a p? type epitaxial layer is Y; a width of the alignment mark parallel to the principal surface of the n? type silicon carbide substrate is X; and an off-angle of the n? type silicon carbide substrate is ?, an epitaxial layer is formed on an upper surface of the alignment mark such that Y?X·tan ? is satisfied.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: January 12, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Tsuji, Kenji Fukuda
  • Patent number: 8900943
    Abstract: A process for fabrication of a power semiconductor device is disclosed in which a single photomask is used to define each of p-conductivity well regions and n-conductivity type source regions. In the process a single photomask is deposited on a layer of polysilicon on a wafer, the polysilicon layer is removed from first regions of the power semiconductor device where the p-conductivity well regions and the n-conductivity type source regions are to be formed, and both p-conductivity type and n-conductivity type dopants are introduced into the wafer through the first regions.
    Type: Grant
    Filed: May 31, 2014
    Date of Patent: December 2, 2014
    Assignee: IXYS Corporation
    Inventors: Kyoung Wook Seok, Jae Yong Choi, Vladimir Tsukanov
  • Patent number: 8835269
    Abstract: A method of manufacturing a solid-state image sensor having photoelectric conversion elements and one or more MOS transistors are formed on a semiconductor substrate is provided. The method includes forming a resist pattern having an opening and a shielding portion over the substrate; and implanting ions in the substrate through the opening. When the substrate is viewed from a direction, an isolation region that is positioned between accumulation regions adjacent to one another is exposed in the opening, and when viewed from a different direction, a channel region of the MOS transistors is exposed in the opening, and the isolation region is shielded by the shielding portion. Ions irradiated in the direction are implanted in the isolation region, and ions irradiated in the different direction are implanted in the channel region.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: September 16, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mahito Shinohara, Junji Iwata
  • Patent number: 8741781
    Abstract: Some embodiments include a semiconductor construction having a pair of lines extending primarily along a first direction, and having a pair of contacts between the lines. The contacts are spaced from one another by a lithographic dimension, and are spaced from the lines by sub-lithographic dimensions. Some embodiments include a method of forming a semiconductor construction. Features are formed over a base. Each feature has a first type sidewall and a second type sidewall. The features are spaced from one another by gaps. Some of the gaps are first type gaps between first type sidewalls, and others of the gaps are second type gaps between second type sidewalls. Masking material is formed to selectively fill the first type gaps relative to the second type gaps. Excess masking material is removed to leave a patterned mask. A pattern is transferred from the patterned mask into the base.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: June 3, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, Ranjan Khurana, David Swindler, Jianming Zhou
  • Patent number: 8741709
    Abstract: A process for fabrication of a power semiconductor device is disclosed in which a single photomask is used to define each of p-conductivity well regions and n-conductivity type source regions. In the process a single photomask is deposited on a layer of polysilicon on a wafer, the polysilicon layer is removed from first regions of the power semiconductor device where the p-conductivity well regions and the n-conductivity type source regions are to be formed, and both p-conductivity type and n-conductivity type dopants are introduced into the wafer through the first regions.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: June 3, 2014
    Assignee: IXYS Corporation
    Inventors: Kyoung Wook Seok, Jae Yong Choi, Vladimir Tsukanov
  • Patent number: 8629026
    Abstract: The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
  • Patent number: 8461005
    Abstract: A method of manufacturing doping patterns includes providing a substrate having a plurality of STIs defining and electrically isolating a plurality of active regions in the substrate, forming a patterned photoresist having a plurality of exposing regions for exposing the active regions and the STIs in between the active regions on the substrate, and performing an ion implantation to form a plurality of doping patterns in the active regions.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: June 11, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Huan-Ting Tseng, Chun-Hsien Huang, Hung-Chin Huang, Chen-Wei Lee
  • Patent number: 8377320
    Abstract: A method of forming an undercut microstructure includes: forming an etch mask on a top surface of a substrate; forming, on a top surface of the etch mask, an ion implantation mask having a top surface that is smaller than the top surface of the etch mask and that does not extend beyond the top surface of the etch mask; ion implanting the substrate in the presence of the etch mask and the ion implantation mask so that a damaged region is generated at a depth below an area of the surface that is not masked by the ion implantation mask; and etching the surface of the substrate until the damaged region is removed.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: February 19, 2013
    Assignee: National Taipei University of Technology
    Inventors: Tzyy-Jiann Wang, Yueh-Hsun Tsou
  • Patent number: 7927955
    Abstract: By providing a novel bipolar device design implementation, a standard CMOS process (105-109) can be used unchanged to fabricate useful bipolar transistors (80) and other bipolar devices having adjustable properties by partially blocking the P or N well doping (25) used for the transistor base (581). This provides a hump-shaped base (583, 584) region with an adjustable base width (79), thereby achieving, for example, higher gain than can be obtained with the unmodified CMOS process (101-104) alone. By further partially blocking the source/drain doping step (107) used to form the emitter (74) of the bipolar transistor (80), the emitter shape and effective base width (79) can be further varied to provide additional control over the bipolar device (80) properties. The embodiments thus include prescribed modifications to the masks (57, 62, 72, 46) associated with the bipolar device (80) that are configured to obtain desired device properties.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: April 19, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Bernhard H. Grote, Hongning Yang, Jiang-Kai Zuo
  • Patent number: 7927969
    Abstract: A method and an equipment for cleaning masks used for photolithography steps, including at least one step of thermal treatment under pumping at a pressure lower than the atmospheric pressure and at a temperature greater than the ambient temperature.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: April 19, 2011
    Assignee: STMicroelectronics S.A.
    Inventor: Christophe Martin
  • Patent number: 7902051
    Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including providing a single crystal substrate; forming an insulating layer on the single crystal substrate; forming a via through the insulating layer to provide an exposed portion of the single crystal substrate; forming amorphous Si on at least the exposed portion of the single crystal substrate; converting at least a portion of the amorphous Si into single crystal Si; and forming dopant regions in the single crystal Si. In one embodiment the diode of the present invention is integrated with a memory device.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: March 8, 2011
    Assignees: International Business Machines Corporation, Qimonda AG, Macronix International Co., Ltd.
    Inventors: Bipin Rajendran, Thomas Happ, Hsiang-Lan Lung
  • Patent number: 7863170
    Abstract: A semiconductor body includes a substrate, a buried zone having a first conductivity type that is formed in the substrate, a first zone having the first conductivity type that is above the buried zone, a second zone having a second conductivity type that is different from the first conductivity type and above the first zone, and a third zone having the first conductivity type that is above the second zone. The buried zone includes first and second implantation regions that are formed via first and second implantations that are performed using a mask. The buried zone, the first zone, the second zone and the third zone are parts of a first transistor structure.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: January 4, 2011
    Assignee: Austriamicrosystems AG
    Inventors: Georg Röhrer, Bernard Löffler, Jochen Kraft
  • Patent number: 7842525
    Abstract: A system for making small modifications to the pattern in standard processed semiconductor devices. The modifications are made to create a small variable part of the pattern against a large constant part of the same pattern. In a preferred embodiment the exposure of the variable and constant parts are done with the same wavelength in the same combined stepper and code-writer. The invention devices a way of writing variable parts of the chip that is automatic, inexpensive and risk-free. A system for automatic design and production of die-unique patterns is also shown.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: November 30, 2010
    Assignee: Micronic Mydata AB
    Inventor: Torbjorn Sandstrom
  • Patent number: 7824973
    Abstract: According to one embodiment of the present invention, a method of forming a semiconductor device is provided, the method including: forming a substrate; forming a first gate on the substrate; forming a mask layer on the substrate, the mask layer including a first window covering an area within which the first gate is formed so that the first gate divides the substrate exposed by the first window into a first region and a second region; and doping the exposed substrate using rays inclined with respect to the substrate top surface, where the position of the first gate with respect to a border of the first window is chosen such that the inclined doping rays impinge more on the first region than on the second region.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: November 2, 2010
    Assignee: Infineon Technologies AG
    Inventors: Karl Hofmann, Stefan Decker
  • Patent number: 7807555
    Abstract: This disclosure describes an improved process and resulting structure that allows a single masking step to be used to define both the body and the threshold adjustment layer of the body. The method consists of forming a first mask on a surface of a substrate with an opening exposing a first region of the substrate; implanting through the opening a first impurity of a first conductivity type and having a first diffusion coefficient; and implanting through the opening a second impurity of the first conductivity type and having a second diffusion coefficient lower than the first diffusion coefficient. The first and second impurities are then co-diffused to form a body region of a field effect transistor. The remainder of the device is formed.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: October 5, 2010
    Assignee: Intersil Americas, Inc.
    Inventor: Michael Curch
  • Patent number: 7598133
    Abstract: A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly comprise laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: October 6, 2009
    Assignee: Renesas Technology Corp
    Inventors: Masahiro Moniwa, Hiraku Chakihara, Kousuke Okuyama, Yasuhiko Takahashi
  • Patent number: 7550355
    Abstract: A boron ion stream may be used to implant ions, such as boron ions, into the sidewalls of an active area, such as an NFET active area. The boron ion stream has both vertical tilt and horizontal rotation components relative to the sidewalls and/or the silicon device, to provide a better line of sight onto the sidewalls. This may allow components of the silicon device to be moved closer together without unduly reducing the effectiveness of boron doping of NFET active area sidewalls, and provides an improved line of sight of a boron ion stream onto the sidewalls of an NFET active area prior to filling the surrounding trench with STI material.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: June 23, 2009
    Assignee: Toshiba America Electronic Components, Inc.
    Inventor: Yusuke Kohyama
  • Patent number: 7488663
    Abstract: A method for manufacturing a semiconductor article and a semiconductor article is provided, wherein a base region of a first semiconductor material is applied, a silicide layer is applied above the base region, after the application of the silicide layer, an opening is created in the silicide layer by removing the silicide layer within the area of the opening, and after this, an emitter region is formed within the opening.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: February 10, 2009
    Assignee: Atmel Germany GmbH
    Inventor: Christoph Bromberger
  • Publication number: 20070298579
    Abstract: A method for forming a bipolar transistor device includes providing a semiconductor substrate. An oxide layer is formed on the semiconductor substrate. The oxide layer is patterned to form an opening that exposes a portion of the semiconductor substrate. A dopant, such as antimony, is implanted into the semiconductor substrate through the opening to form a buried layer. An upper portion of the mask layer is removed to define a thin mask layer. A buried layer diffusion process is performed to drive in the implanted dopants while mitigating recess formation.
    Type: Application
    Filed: June 26, 2006
    Publication date: December 27, 2007
    Inventors: Binghua Hu, Yu-En Hsu, Qingfeng Wang
  • Patent number: 7303949
    Abstract: A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: December 4, 2007
    Assignee: International Business Machines Corporation
    Inventors: Huajie Chen, Dureseti Chidambarrao, Omer H Dokumaci
  • Patent number: 7241660
    Abstract: A manufacturing method of a semiconductor device having a semiconductor memory including a plurality of nonvolatile memory elements, comprising a step of forming a mask on the semiconductor memory and a step of irradiating through the mask with electron beams, the mask having transmission parts on one or more nonvolatile memory elements selected from the plurality of nonvolatile memory elements and a blocking part in which the electron beam is blocked, thereby said one or more nonvolatile memory elements are irradiated with electron beams without requiring an additional process.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: July 10, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hidenori Fujii
  • Patent number: 7067383
    Abstract: A method of forming bipolar transistors by using the same mask to form the collector region in a substrate of an opposite conductivity type as to form the base in the collector region. More specifically, impurities of a first conductivity type are introduced into a region of a substrate of a second conductivity type through a first aperture in a first mask to form a collector region. Impurities of the second conductivity type are introduced in the collector through the first aperture in the first mask to form the base region. Impurities of the first conductivity type are then introduced into the base region through a second aperture in a second mask to form the emitter region. The minimum dimension of the first aperture of the first mask is selected for a desired collector to base breakdown voltage. This allows tuning of the breakdown voltage.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: June 27, 2006
    Assignee: Intersil Americas, Inc.
    Inventor: James Douglas Beasom
  • Patent number: 7037748
    Abstract: A CMOS image sensor and a manufacturing method thereof, wherein the gates of several transistors of the CMOS image sensor are formed in an active region defined by an isolation region for a unit pixel of the CMOS image sensor, and a passivation layer composed of insulating layer is formed on the semiconductor substrate. Impurities are ion-implanted into the active region to form one or more diffusion regions of a photo diode of the CMOS image sensor, wherein the passivation layer prevents a boundary portion of the active region from being ion-implanted. Thus, damages by ion implantation at the boundary portion between the diffusion region for the photo diode and the isolation region are prevented, and the dark current of the CMOS image sensor is reduced.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: May 2, 2006
    Assignee: Dongbuanam Semiconducor Inc.
    Inventor: Chang Hun Han
  • Patent number: 7033903
    Abstract: A method for forming a patterned photoresist layer aligned with a predetermined layer is described. A photoresist layer is formed on a substrate and then exposed. The overlay offset between the exposed portions of the photoresist layer and the predetermined layer is measured for determining whether the exposed portions of the photoresist layer are aligned with the predetermined layer. A development step is performed when the exposed portions of the photoresist layer are found to align with the predetermined layer. An apparatus for forming a patterned photoresist layer is also described, which utilizes the aforementioned method and has a mechanism capable of feeding back the overlay offset in real time for reducing the cycle time and the rework time in the lithography process.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: April 25, 2006
    Assignee: United Microelectronics Corp.
    Inventors: Jack Lin, Calvin Wu, George K C Huang
  • Patent number: 6890826
    Abstract: A method of manufacturing a bipolar junction transistor results in an integrated polysilicon base contact and field plate element minimally spaced from a polysilicon emitter contact by using a single mask to define respective openings for these elements. In particular, a dielectric layer is deposited on a semiconductor wafer and has two openings defined by a single masking step, one opening above an emitter region and a second opening above a base-collector junction region. Polysilicon is deposited on the dielectric layer and selectively doped in the areas of the openings. Thus for an NPN transistor for example, the area above the emitter opening is doped N type and the area above the base/field plate opening is doped P type. The doped polysilicon is patterned and etched to leave a polysilicon emitter contact and an integrated polysilicon base contact and field plate within the respective openings.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: May 10, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: Sheldon Douglas Haynie
  • Patent number: 6872645
    Abstract: Methods of positioning and orienting nanostructures, and particularly nanowires, on surfaces for subsequent use or integration. The methods utilize mask based processes alone or in combination with flow based alignment of the nanostructures to provide oriented and positioned nanostructures on surfaces. Also provided are populations of positioned and/or oriented nanostructures, devices that include populations of positioned and/or oriented nanostructures, systems for positioning and/or orienting nanostructures, and related devices, systems and methods.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: March 29, 2005
    Assignee: Nanosys, Inc.
    Inventors: Xiangfeng Duan, Hugh Daniels, Chunming Niu, Vijendra Sahi, James Hamilton, Linda T. Romano
  • Patent number: 6835606
    Abstract: A low temperature polysilicon thin film transistor and a method of forming the polysilicon layer inside the thin film transistor. An amorphous silicon layer is formed over a panel. The panel has a display region and a peripheral circuit region. A metallic layer is formed over a portion of the amorphous silicon layer in the peripheral circuit region. A crystallization process is performed to transform the amorphous silicon layer in the peripheral circuit region into a polysilicon layer. Thereafter, an excimer laser annealing process is performed to increase the grain size of the polysilicon layer in the peripheral circuit region and, at the same time, transform the amorphous silicon layer in the display region into a polysilicon layer. Since the average grain size of the polysilicon layer in the peripheral circuit region is larger, electron mobility is increased as demanded.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: December 28, 2004
    Assignee: Au Optronics Corporation
    Inventors: Chia-Tien Peng, Huan-Chao Wu
  • Publication number: 20030203561
    Abstract: A dual-gate CMOS semiconductor device and a manufacturing method therefor suppressing mutual diffusion of P type impurities and N type impurities in a gate electrode are provided. This invention is comprised of an NMOS part 103 and a PMOS part 104 formed on a semiconductor substrate; a polycrystalline silicon layer formed on the NMOS part 103 and the PMOS part 104 and consisting of an N type impurity containing polycrystalline silicon layer 106 and a P type impurity containing polycrystalline silicon layer 107; and a first conductive layer 108 formed on the polycrystalline silicon layer so as to include a groove region 120, in which the first conductive layer is not formed, on a predetermined region including a boundary between the N type impurity containing polycrystalline silicon layer 106 and the P type impurity containing polycrystalline silicon layer 107.
    Type: Application
    Filed: April 29, 2003
    Publication date: October 30, 2003
    Inventor: Hiroyuki Tanaka
  • Publication number: 20020112784
    Abstract: A correcting device that properly maintains the flatness of a mask, an exposure apparatus in which overlay accuracy is increased by making use of the correcting device, and a device production method. The correcting device includes a gas flow path including a first area and a second area. The first area is formed above a reticle having formed thereon a pattern that is projected onto a material to be processed in order to form an image of the pattern on the material to be processed. The second area is connected to the first area, has a cross-sectional area that is different from that of the first area, and is not disposed in line with the reticle. The correcting device also includes a blowing section that blows gas to the gas flow path.
    Type: Application
    Filed: December 11, 2001
    Publication date: August 22, 2002
    Inventors: Nobuyoshi Tanaka, Eiji Sakamoto
  • Patent number: 6432790
    Abstract: The reliability of a photomask is improved. The planar shape of a mask substrate 1 of a resist shading mask having a shading pattern composed of a resist film is made circular.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: August 13, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihiko Okamoto, Masamichi Kobayashi, Satoshi Momose
  • Publication number: 20020052088
    Abstract: The reliability of a photomask is improved. The planar shape of a mask substrate 1 of a resist shading mask having a shading pattern composed of a resist film is made circular.
    Type: Application
    Filed: August 31, 2001
    Publication date: May 2, 2002
    Inventors: Yoshihiko Okamoto, Masamichi Kobayashi, Satoshi Momose
  • Patent number: 6337252
    Abstract: There is provided a method of manufacturing a semiconductor device which can use commonly a part of a step of forming a PAP transistor with a step of forming an NON transistor. In an area separated by a side separation region (5) of PNP formed by doping N-type impurities simultaneously with the formation of the collector region (4) of NPN, an N-type bottom separation region (8) of PNP, a collector region (9) and a base region (10) are formed by using the same mask. Trenches (18, 17) extending to the collector regions (9, 4) are formed by an over-etching treatment carried out when the emitter electrodes (16, 15) of PNP and NPN are subjected to a patterning treatment, and N-type impurities are doped through the trench (17) simultaneously with the formation of an external base region (20) of PNP, thereby forming a collector drawing region (21) of NPN.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: January 8, 2002
    Assignee: NEC Corporation
    Inventor: Hiroshi Yoshida
  • Patent number: 6329260
    Abstract: An integrated circuit has an isolation structure in the form of a double diode moat. The P substrate has P+ buried layers 8601 and 8602 on opposite sides of N+ buried layer 8605. Analog devices are formed behind one diode moat, digital CMOS devices are formed behind the other moat.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: December 11, 2001
    Assignee: Intersil Americas Inc.
    Inventors: Glenn Alan DeJong, Akira Ito, Choong-Sun Rhee, Jeffrey Johnston, Michael D. Church, Kantilal Bacrania
  • Patent number: 6251739
    Abstract: The present invention relates to a collector pin and a trench in an integrated circuit intended for high speed communication, and to a manufacturing method for these items. The collector pin is achieved by creating an area which is implantation damaged or made amorphous and at least partially doped (139) by means of ion implantation from an upper silicon surface comprised in a semiconductor structure (144) down to a depth lower than the depth of the surrounding field oxide (120), and that the semiconductor structure (144) is then heat treated.
    Type: Grant
    Filed: May 22, 1998
    Date of Patent: June 26, 2001
    Assignee: Telefonaktiebolaget LM Ericsson
    Inventors: Hans Erik Norstrom, Sam-Hyo Hong, Bo Anders Lindgren, Torbjorn Larsson
  • Patent number: 6180442
    Abstract: The present invention relates to a method for fabricating an integrated circuit including an NPN-type bipolar transistor, including the steps of defining a base-emitter location of the transistor with polysilicon spacers resting on a silicon nitride layer; overetching the silicon nitride under the spacers; filling the overetched layer with highly-doped N-type polysilicon; depositing an N-type doped polysilicon layer; and diffusing the doping contained in the third and fourth layers to form the emitter of the bipolar transistor.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: January 30, 2001
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Yvon Gris
  • Patent number: 6077746
    Abstract: A method for forming a p-type halo implant as ROM cell isolation in a flat-cell mask ROM process is described. A P-well is formed within a semiconductor substrate and an oxide layer is formed overlying a surface of the substrate. A photomask is formed overlying the oxide layer wherein openings are left within the photomask exposing portions of the oxide layer. First, ions are implanted through the exposed portions of the oxide layer into the underlying semiconductor substrate whereby buried bit lines are formed. Thereafter, second ions are implanted through the exposed portions of the oxide layer whereby halo regions are formed encompassing the buried bit lines. The halo regions provide ROM isolation and punch-through protection for the buried bit lines. Thereafter, the photomask is removed and fabrication of flat-cell mask ROM device is completed.
    Type: Grant
    Filed: August 26, 1999
    Date of Patent: June 20, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jyh-Cheng You, Lin-June Wu
  • Patent number: 6043130
    Abstract: A bipolar transistor compatible with CMOS processes utilizes only a single layer of polysilicon while maintaining the low base resistance associated with conventional double-polysilicon bipolar designs. Dopant is implanted to form the intrinsic base through the same dielectric window in which the polysilicon emitter contact component is later created. Following poly deposition within the window and etch to create the polysilicon emitter contact component, large-angle tilt ion implantation is employed to form a link base between the intrinsic base and a subsequently-formed base contact region. Tilted implantation enables the link base region to extend underneath the edges of the polysilicon emitter contact component, creating a low resistance path between the intrinsic base and the extrinsic base. Fabrication of the device is much simplified over a conventional double-poly transistor, particularly if tilted implantation is already employed in the process flow to form an associated structure such as an LDMOS.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: March 28, 2000
    Assignee: National Semiconductor Corporation
    Inventor: Haydn James Gregory
  • Patent number: 6001700
    Abstract: A method for making self-aligned sub-micrometer bipolar transistors and FETs on a substrate for BiFET and BiCMOS circuits was achieved using a novel LOCOS structure as a self-aligned implant mask. This LOCOS structure uses a silicon nitride mask comprised of stripes with well defined widths and spacings to form a punchthrough oxide mask of varying thicknesses over the emitter, base, and collector of the bipolar transistor, while providing a thick field oxide elsewhere on the substrate. The oxide mask serves as a self-aligned implant mask for implanting the emitter, base, and collector of the bipolar transistor. The nitride mask can be patterned concurrently to form an implant mask for the FET. A series of ion implants is then used to form the emitter, base, and collector without requiring separate photoresist masks. An array of nitride stripes with well defined widths and spacings can be used to make larger transistors, such as bipolar power transistors.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: December 14, 1999
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventor: Igor V. Peidous
  • Patent number: 5885880
    Abstract: A semiconductor device is provided in which a vertical NPN transistor and a vertical PNP transistor electrically isolated from each other are formed on a p-type semiconductor substrate. An n-type buried separating region of the vertical PNP transistor is formed by high-energy ion implantation after formation of the n.sup.+ type buried collector region of the vertical NPN transistor, and a p.sup.+ type buried collector region of the vertical PNP transistor is formed subsequently to formation of an n-type epitaxial layer and a device separating region whereby the thickness of the n-type epitaxial layer is optimized to a required minimum value. A method for producing a semiconductor device is also provided in which a first vertical bipolar transistor of a first conductivity type and a second vertical bipolar transistor of a second conductivity type, electrically isolated from each other, are formed on a semiconductor substrate having a pre-set conductivity type.
    Type: Grant
    Filed: September 15, 1995
    Date of Patent: March 23, 1999
    Assignee: Sony Corporation
    Inventor: Takayuki Gomi
  • Patent number: 5846858
    Abstract: In a manufacturing method for lateral bipolar transistors on an SOI substrate, a ridge-shaped gate electrode (8/9) is applied onto a mesa (3) provided with a basic doping and is covered surface-wide with a TEOS layer (10) that has vertical portions functioning as spacers (11,12) at the sidewalls of this gate electrode. Dopants for a collector region (4) and an emitter region (6) are introduced using lacquer masks (13,14). After the removal of the TEOS layer (10), the base implantation ensues in the region of the spacer (11) along an edge of the gate electrode.
    Type: Grant
    Filed: April 22, 1996
    Date of Patent: December 8, 1998
    Assignee: Siemens Aktiengesellschaft
    Inventor: Martin Kerber
  • Patent number: 5837590
    Abstract: A vertical PNP transistor and method for making it provide a transistor in a surface layer (12), which may be an epitaxial layer, of P- type conductivity at a surface of a substrate (11) of P+ type conductivity. An isolation region (14) of N- type conductivity in the P- surface layer (12) contains a collector region (25) of P- type conductivity. A base region (30) of N type conductivity is contained in the collector region (25), and an emitter region (40) of P+ type conductivity is contained in the base region (30). The base region (30) may be provided with a higher N type impurity concentration than a P type impurity concentration of the collector region (25). At least the collector region (25) and the base region (30) may be self aligned. The collector region (25) may be of thickness of about 2.2 .mu.m, the base region (30) of thickness of about 0.1 .mu.m, and the emitter region (40) of thickness of about 0.4 .mu.m.
    Type: Grant
    Filed: June 5, 1997
    Date of Patent: November 17, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Lawrence F. Latham, Theresa M. Keller