Abstract: An arrangement having p-doped semiconductor layers and n-doped semiconductor layers which exhibits transitions between the p-doped semiconductor layers and n-doped semiconductor layers, the transitions displaying a Zener breakdown upon application of a voltage characteristic of a transition, a plurality of transitions between p-doped semiconductor layers and n-doped semiconductor layers being present, and the characteristic voltages additively make up the breakdown voltage of the entire arrangement. Also described is a method for manufacturing the arrangement.

Abstract: A diode for use in an under-the-hood automotive application has a TO 220 outline and consists of a diode die on a two piece lead frame which has a thick section to which the bottom of the die is soldered, and a thinner section which extends through a plastic housing as a connection tab and which has a forked end for easy connection to a node of a three phase bridge. The bottom of the thickened section is exposed through the insulation housing for easy connection to a d-c heat sink rail. The diode is particularly useful in applications greater than 2 KW.

Abstract: A tunnel diode has a quantum well having at least one layer of semiconductor material. The tunnel diode also has a pair of injection layers on either side of the quantum well. The injection layers comprise a collector layer and an emitter layer. A barrier layer is positioned between each of the injection layers and the quantum well. The quantum well has an epitaxial relationship with the emitter layer. An amount of one element of the well layer is increased to increase the lattice constant a predetermined amount. The lattice constant may have a reduction in the conduction band energy. A second element is added to the well layer to increase the conduction band energy but not to change the lattice constant. By controlling the composition in this matter, the negative resistance, and thus the effective mass, may be controlled for various diode constructions.

Abstract: A semiconductor component includes a semiconductor layer (210) and at least one diode (220) in the semiconductor layer. The semiconductor component also includes an electrically insulative layer (230) over the semiconductor layer and the diode. The semiconductor component further includes at least one more diode (240, 250, 280, 290, 440, 450) over the electrically insulative layer, the semiconductor layer, and the diode in the semiconductor layer.

Abstract: Semiconductor structures and a method of forming semiconductor structures The avalanche breakdown characteristics, such as breakdown voltage and impact ionisation coefficient, of a semiconductor structure can be controlled by controlling the Brilluin-zone-averaged energy bandgap (<Ec>) of the material forming the structure. Consequently, the avalanche breakdown characteristics of a device may be tailored independently of the bandgap Eg. The Brillouin-zone-averaged energy bandgap (<Ec>) may be controlled by controlling the composition of the semiconductor used or by straining its lattice.

Abstract: A semiconductor device with a tunnel diode comprises two mutually adjoining semiconductor regions (2, 3) of opposed conductivity types having high enough doping concentrations to provide a tunneling junction. Portions (2A, 3A) of the semiconductor regions adjoining the junction comprise a mixed crystal of silicon and germanium. The doping concentration of both phosphorus and boron are substantially increased, given the same amount of dopants being offered as during the formation of the remainder of the regions. The tunneling efficiency is substantially improved, and also because of the reduced bandgap of said portions (2A, 3A). A much steeper current-voltage characteristic both in the forward and in the reverse direction is achieved. Thus, the tunneling pn junction can be used as a transition between two conventional diodes which are stacked one on the other and formed in a single epitaxial growing process. The doping concentration may be 6×1019 or even more than 1020 at/cm3.

Abstract: A method for manufacturing a pair of electrodes comprises fabricating a first electrode with a substantially flat surface and placing a sacrificial layer over a surface of the first electrode, wherein the sacrificial layer comprises a first material. A second material is placed over the sacrificial layer, wherein the second material comprises a material that is suitable for use as a second electrode. The sacrificial layer is removed with an etchant, wherein the etchant chemically reacts with the first material, and further wherein a region between the first electrode and the second electrode comprises a gap that is a distance of 50 nanometers or less, preferably 5 nanometers or less. Alternatively, the sacrificial layer is removed by cooling the sandwich with liquid nitrogen, or alternatively still, the sacrificial layer is removed by heating the sacrificial layer, thereby evaporating the sacrificial layer.

Abstract: The present invention provides an encapsulated 3-D conductive pillar and a method of formation thereof. Significant economic savings are achieved by filling a substantial portion of the volume of the pillar with a lesser expensive conductive material. Additionally, the encapsulated 3-D conductor pillar forms a suitable unreactive, oxygen-stable electrode for use with high-dielectric constant (HDC) materials as the encapsulating barrier layer metal provides a stable conductive interface between the HDC material and the encapsulated conductive material.

Abstract: A method is proposed that functions to produce Zener diodes. The method includes a two-part film diffusion step for producing flatter and deeper doping profiles using neutral films.

Abstract: An avalanche photodiode fabricating method with a simplified fabrication process and an improved reproducibility is disclosed.

Abstract: Semiconductor structures and a method of forming semiconductor structures The avalanche breakdown characteristics, such as breakdown voltage and impact ionisation coefficient, of a semiconductor structure can be controlled by controlling the Brillouin-zone-averaged energy bandgap (<Ec>) of the material forming the structure. Consequently, the avalanche breakdown characteristics of a device may be tailored independently of the bandgap Eg. The Brillouin-zone-averaged energy bandgap (<Ec>) may be controlled by controlling the composition of the semiconductor used or by straining its lattice.

Abstract: A method for manufacturing a pair of electrodes comprises fabricating a first electrode with a substantially flat surface and placing a sacrificial layer over a surface of the first electrode, wherein the sacrificial layer comprises a first material. A second material is placed over the sacrificial layer, wherein the second material comprises a material that is suitable for use as a second electrode. The sacrificial layer is removed with an etchant, wherein the etchant chemically reacts with the first material, and further wherein a region between the first electrode and the second electrode comprises a gap that is a distance of 50 nanometers or less, preferably 5 nanometers or less. Alternatively, the sacrificial layer is removed by cooling the sandwich with liquid nitrogen, or alternatively still, the sacrificial layer is removed by heating the sacrificial layer, thereby evaporating the sacrificial layer.

Abstract: A manufacturing process providing a zener diode formed in an N-type well housing a first N-type conductive region and having a doping level higher than the well, and a second P-type conductive region arranged contiguous to the first conductive region. The first conductive region is connected, through a third N-type conductive region having the same doping level as the first conductive region, to a conductive material layer overlying the gate oxide layer to be protected. The third conductive region, the well, and the substrate form an N+/N/P diode that protects the gate oxide layer during manufacture of the integrated device from the deposition of the polycrystalline silicon layer that forms the gate regions of the MOS elements.

Abstract: A passive mechanism suppresses injection, into any active guard regions interposed between the edge of a photodiode array chip and the outer photodiode pixels or into the outer pixels themselves, of minority carrier current generated in the physically disrupted region at the edge of the semiconductor die created by cleaving, sawing or otherwise separating the chip from the remainder of the wafer on which the die was fabricated. A thin metallic layer covers all or part of the edge region, thereby creating a Schottky barrier. This barrier generates a depletion region in the adjacent semiconductor material. The depletion region inherently creates an energy band distribution which preferentially accelerates minority carriers generated or near the metal-semiconductor interface towards the metal, thereby suppressing collection of these carriers by any active regions of the guard structure or by the photodiode pixels.

Abstract: The present invention relates to a method of manufacturing an avalanche diode of determined threshold in a substrate of a first conductivity type with a low doping level, including the steps of diffusing in the substrate at least one first region of the first conductivity type; diffusing in the substrate a second region of the second conductivity type protruding from the first region. The opening of a mask of definition of the first region has a lateral extent smaller than the diffusion depth of the first region in the substrate, this lateral extent being chosen all the smaller as the desired avalanche threshold is high.

Abstract: A semiconductor device with a tunnel diode (23) is particularly suitable for various applications. Such a device comprises two mutually adjoining semiconductor regions (2, 3) of opposed conductivity types and having doping concentrations which are so high that breakdown between them leads to conduction by means of tunnelling. A disadvantage of the known device is that the current-voltage characteristic is not yet steep enough for some applications.

Abstract: A semiconductor processing method of forming a resistor from semiconductive material includes: a) providing a node to which electrical connection to a resistor is to be made; b) providing a first electrically insulative material outwardly of the node; c) providing an exposed vertical sidewall in the first electrically insulative material outwardly of the node; d) providing a second electrically insulative material outwardly of the first material and over the first material vertical sidewall, the first and second materials being selectively etchable relative to one another; e) anisotropically etching the second material selectively relative to the first material to form a substantially vertically extending sidewall spacer over the first material vertical sidewall and to outwardly expose the first material adjacent the sidewall spacer, the spacer having an inner surface and an outer surface; f) etching the first material selectively relative to the second material to outwardly expose at least a portion of the s

Abstract: A fast recovery diode (FRED) is fabricated by a process using a reduced number of masking steps. The FRED is a vertical conduction device in which P type anode regions are isolated using either LOCOS oxidation or deposited low temperature oxide. The first masking step defines the anode and isolation regions, and a second masking step defines the aluminum contact layer. For devices having a breakdown voltage greater than 800 volts, a third masking step is included which defines the passivated area.

Abstract: In a process for fabricating a radiation detector comprising the step of drifting lithium from one side of a silicon wafer, a boron diffusion layer is formed on the other side of the silicon wafer prior to the drifting step. Therefore, in spite of the tendency of the drift layer to have uneven thickness, the drift layer is allowed to be formed uniformly over the entire area. This eliminates the need to lap the other side of the wafer to expose the drift layer over the entire surface. Also, a PN junction diode is formed on the other side of the wafer, and this makes the completed detector resistant to environmental influences, as opposed to conventional radiation detectors of this type which include a surface barrier type diode.

Abstract: An embodiment of the instant invention is a method of substantially isolating an electrical device over a semiconductor substrate from a structure which collects charge, the method comprising the steps of: forming an insulating layer (layer 304) on the substrate; forming a conductive layer (layer 306) on the insulating layer; incorporating at least one element (element 310) into portions of the conductive layer so as to render that portion the conductive layer more resistive; and wherein the portion of the conductive layer which has been rendered more resistive (region 312) is rendered conductive after one or more charging events by subjecting the portion of the conductive layer to an elevated temperature. Preferably, the element is comprised of an element selected from the group comprised of: As, P, N, Ar, Si, H, B, Ge, C, Sb, F, Cl, O, any noble element, and any combination thereof and their isotopes.

Abstract: A manufacturing method for rectifying diodes, wherein, a plurality of upper and lower pins are combined with a plurality of electronic chips to form a coarse blank. And then they are processed to form shaped insulating layers by molding. Each insulating layer is processed to have superficial coarseness having micro-protuberances thereon; the areas on both the lateral sides of the insulating layer are applied with electric conductive layer. The electric conductive layer is combined with the insulating layer; they are equidistantly cut with a knife into shaped rectifying diodes. The shaped rectifying diodes each is further electrically plated with a further layer of electric conductive material on both sides of the electric conductive layer to form a harder protection layer, and then finished rectifying diodes are obtained. The upper and lower pins are in the form of thin sheets, plus the small chips, the shaped rectifying diodes have small volumes.

Abstract: The first trench is formed in the region of the semiconductor substrate, in which an element isolation region is to be formed, and the first buried member, which is insulative, is buried in the first trench. Then, the second trench, having a width smaller than that of the first trench, is made in the first buried member, and the portion of the semiconductor substrate which is located at the bottom portion of the first trench, and the insulating second buried member is buried in the second trench, thereby forming the element isolation region.

Abstract: A diode integrated on semiconductor material with BCD technology and of the type provided on a substrate having a first type of conductivity inside an isolation region having a second type of conductivity. The diode comprises also a buried anode region having a first type of conductivity and a cathode region having a second type of conductivity. The cathode region comprises an epitaxial layer located above the buried anode region and a highly doped region provided inside the epitaxial layer. The buried anode region comprises depressions opposite which is located the highly doped region with the depressions being achieved by the intersection of lateral diffusions of distinct and adjacent portions of the buried anode region.

Abstract: The invention relates to a method of manufacturing a semiconductor device with a pn junction, whereby an epitaxial layer (2) with a first zone (3) of a first conductivity type and with a second zone (4) of a second conductivity type opposed to the first is provided on a silicon substrate (1), a pn junction (5) being formed between the second and first zones (3, 4, respectively). According to the invention, the method is characterized in that the epitaxial layer (2) is provided by means of a CVD process at a temperature below 800.degree. C., the epitaxial layer (2) being provided in that first the first zone (3) and then the second zone (4) are epitaxially provided on the substrate (1), while no heat treatments at temperatures above 800.degree. C. take place after the epitaxial layer (2) has been provided.

Abstract: An auxiliary device is constituted by a U-bolt-shaped, pincer-like implement which, during the fabrication of semiconductor devices with a mesa structure from a starting substrate forming a wafer, serves to transfer the outline geometry of the individual semiconductor devices from one side of the wafer to the back of the wafer. The implement has at least one tracer at the end of one of its arms for engaging a sawed groove and for guiding the implement along the sawed groove on one side of the wafer. At the end of the other arm, a marking device with at least one marking stylus is provided whereby the course of the at least one sawed grooved can be transferred from the front side of the wafer to the back, and scribed there in the form of auxiliary lines.

Abstract: A method of manufacturing a polysilicon plug in an integrated circuit semiconductor device wherein the polysilicon plug is selectively doped to act as a resistive load or alternatively to act as a diode load. The polysilicon load can be used in an SRAM memory cell.

Abstract: The subject invention relates to a hybrid reinforcement material comprising a refractory metal core having a first coating comprising aluminum, oxygen and nitrogen, this coating of the general formula:Al.sub.x O.sub.y N.sub.zwhereinx is up to about 670 atomic % of the coatingy is from about 20 atomic % to about 55 atomic % ofthe coating; andz is from about 5 atomic % to about 45 atomic % of the coating, with the proviso that x+y+z=100, and having a second SiC coating.The subject invention further relates to a high strength, high temperature performance composite containing the hybrid reinforcement specified above.