Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.

Abstract: Embodiments relate to placing one or more light emitting diodes (LEDs) onto a printed circuit board (PCB). Voltage differences are applied to the PCB such that, if properly placed, the one or more LEDs emit light. A camera records the placement and any light emitted from the one or more LEDs. Based upon the images from the camera, a controller can adjust placement parameters of the LEDs until they emit light. Among other advantages, the placement of the LEDs on the PCB can be adjusted in real time and allows insight into the causes of failed LED placement.

Abstract: In a micro-device integration process, a donor substrate is provided on which to conduct the initial manufacturing and pixelation steps to define the micro devices, including functional, e.g. light emitting layers, sandwiched between top and bottom conductive layers. The micro-devices are then transferred to a system substrate for finalizing and electronic control integration. The transfer may be facilitated by various means, including providing a continuous light emitting functional layer, breakable anchors on the donor substrates, temporary intermediate substrates enabling a thermal transfer technique, or temporary intermediate substrates with a breakable substrate bonding layer.

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract: Creating a localized region of material having a target chemical composition by defining an electrical circuit on a substrate, and depositing on the electrical circuit one or more layers of materials having one or more chemical compositions. An electrical current pulse is applied to the electrical circuit to create a self-aligned localized region having the target chemical composition. Applying the electrical current pulse causes a portion of the one or more layers of materials to be heated, resulting in the target chemical composition.

Abstract: An apparatus and method for programming an electronically programmable semiconductor fuse applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective electromigration while avoiding exceeding temperature limits of the fuse link.

Abstract: System and methods offset mechanism elements during fabrication of Micro-Electro-Mechanical Systems (MEMS) devices. An exemplary embodiment applies a voltage across an offset mechanism element and a bonding layer of a MEMS device to generate an electrostatic charge between the offset mechanism element and the bonding layer, wherein the electrostatic charge draws the offset mechanism element to the bonding layer. The offset mechanism element and the bonding layer are then bonded.

Abstract: A nonvolatile semiconductor memory device of the present invention includes a substrate (1), first wires (2), memory cells each including a resistance variable element (5) and a portion of a diode element (6), second wires (11) which respectively cross the first wires (2) to be perpendicular to the first wires (2) and each of which contains a remaining portion of the diode element (6), and upper wires (13) formed via an interlayer insulating layer (12), respectively, and the first wires (2) are connected to the upper wires (13) via first contacts (14), respectively, and the second wires (11) are connected to the upper wires (13) via second contacts (15), respectively.

Abstract: A nonvolatile semiconductor memory device of the present invention includes a substrate (1), first wires (2), memory cells each including a resistance variable element (5) and a portion of a diode element (6), second wires (11) which respectively cross the first wires (2) to be perpendicular to the first wires (2) and each of which contains a remaining portion of the diode element (6), and upper wires (13) formed via an interlayer insulating layer (12), respectively, and the first wires (2) are connected to the upper wires (13) via first contacts (14), respectively, and the second wires (11) are connected to the upper wires (13) via second contacts (15), respectively.

Abstract: Creating a localized region of material having a target chemical composition by defining an electrical circuit on a substrate, and depositing on the electrical circuit one or more layers of materials having one or more chemical compositions. An electrical current pulse is applied to the electrical circuit to create a self-aligned localized region having the target chemical composition. Applying the electrical current pulse causes a portion of the one or more layers of materials to be heated, resulting in the target chemical composition.

Abstract: Proposed is the method for forming selective emitters, field-induced emitters, back-surface field regions, and contacts to the functional regions of a solar cell by essentially electrical means and without conventional thermal diffusion and masking processes. The process includes forming conductive layers on both sides of an intermediate solar-cell structure, performing electrical and thermal treatment by passing electrical current independently through the front-side conductive layer and the back-side conductive layer, thus forming the selective emitters, the selective BSF regions, selective emitter contact regions, and contacts to the selective BSF regions. The obtained structure is then subjected to pulse electrical treatment by applying a voltage pulse or pulses between the front and back conductive layers to form the field-induced emitter and the field-induced BSF region. After the conductive layers are removed, a final solar cell is obtained.

Abstract: An improved crack stop structure (and method of forming) is provided within a die seal ring of an integrated circuit die to increase crack resistance during the dicing of a semiconductor wafer. The crack stop structure includes a stack layer (of alternating insulating and conductive layers) and an anchor system extending from the stack layer to a predetermined point below the surface of the substrate. A crack stop trench is formed in the substrate and filled with material having good crack resistance to anchor the stack layer to the substrate.

Abstract: According to one embodiment, a nonvolatile memory device includes a memory layer and a control unit. The memory layer includes a first conductive layer, a second conductive layer and a resistance change layer. The resistance change layer is provided between the first and second conductive layers and transits between a high resistance state and a low resistance state by at least one of an applied electric field and an applied current. The control unit is electrically connected to the first and second conductive layers and configured to apply a first signal with a first polarity between the first and second conductive layers prior to applying a second signal with a second polarity different from the first polarity between the first and second conductive layers to cause the resistance change layer to transit from the high resistance state to the low resistance state.

Abstract: A method of manufacturing a solid-state image pickup device according to an embodiment includes forming first and second holes in a semiconductor substrate, forming insulating films on surfaces of the first and second holes, forming a contact and an alignment mark by embedding a conducting material in the first and second holes, forming a photodiode in the semiconductor substrate, forming a wiring layer including a connecting part for connecting to the contact and a wiring for connecting to the connecting part, bonding a supporting substrate on the wiring layer, exposing the contact and the alignment mark on the surface of the semiconductor substrate by reducing the semiconductor substrate in thickness, and forming a filter and a lens on the photodiode based on the alignment mark.

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract: A phase change memory including an ovonic threshold switch is formed using a pulsed direct current (DC) deposition chamber using pulsed DC. Pulsed DC is used to deposit a chalcogenide film. Pulsed DC may be also used to deposit a carbon film.

Abstract: A phase-change material and a memory unit using the phase-change material are provided. The phase-change material is in a single crystalline state and includes a compound of a metal oxide or nitroxide, wherein the metal is at least one selected from a group consisting of indium, gallium and germanium. The memory unit includes a substrate; at least a first contact electrode formed on the substrate; a dielectric layer disposed on the substrate and formed with an opening for a layer of the phase-change material to be formed therein; and at least a second contact electrode disposed on the dielectric layer. As the phase-change material is in a single crystalline state and of a great discrepancy between high and low resistance states, the memory unit using the phase-changed material can achieve a phase-change characteristic rapidly by pulse voltage and avert any incomplete reset while with a low critical power.

Abstract: A coating process to infill high aspect-ratio vias and trenches in semiconductor substrates with dense boron for the production of neutron detectors and other devices uses a vacuum cathodic arc or other source of fully ionized boron plasma. Biasing of the substrate is used to impart energies to the plasma ions directing them toward the substrate, while repulsing the electrons. The full ionization produced by the source allows control of the energies of the boron ions by means of the bias voltage. The bias is alternated between coating deposition at low ion energies and sputtering of already coated material by energetic ions. Most of the sputtered material comes off the substrate top surface and between the trenches or vias and much of it is redeposited, thereby contributing to the infill. The process is suitable for carbon, boron or similar light elements, and is of particular interest for 10B, an element having exceptionally high thermal neutron cross-section.

Abstract: A monolithically integrated semiconductor assembly having a power component, and a method for manufacturing a semiconductor assembly, are proposed, a monolithically integrated resistor element being provided between a first terminal and the second region, and a comparatively low-impedance electrical connection through the first region being provided between the resistor element and the second region.

Abstract: A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die.

Abstract: An electrically tunable resistor and related methods are disclosed. In one embodiment, the resistor includes a first resistive layer, at least one second resistive layer, and an intermediate interdiffused layer of the first resistive layer and the at least one second resistive layer. One method may include providing a first plurality of layers of different materials surrounded by at least one insulating layer, and passing a current pulse through the first plurality of layers to affect a conductivity structure of the first plurality of layers in order to obtain a first predetermined resistance value for the resistor.

Abstract: The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to an e-fuse device including an opening, a first via and a second via in an interlayer dielectric, wherein the opening, the first via and the second via are connected to an interconnect below the interlayer dielectric; a dielectric layer that encloses the first via and the second via; and a metal layer over the dielectric layer, wherein the metal layer fills the opening with a metal, and wherein the first via and the second via are substantially empty to allow for electromigration of the interconnect during re-programming of the e-fuse device.

Abstract: The present invention essentially relates to a method of preparing an electrically insulating film at the surface of an electrical conductor or semiconductor substrate, such as a silicon substrate. According to the invention, this method comprises: a) bringing said surface into contact with a liquid solution comprising: a protic solvent; at least one diazonium salt; at least one monomer that is chain-polymerizable and soluble in said protic solvent; at least one acid in a sufficient quantity to stabilize said diazonium salt by adjusting the pH of said solution to a value less than 7, preferably less than 2.5; b) the polarization of said surface according to a potentio- or galvano-pulsed mode for a duration sufficient to form a film having a thickness of at least 60 nanometres, and preferably between 80 and 500 nanometres. Application: Metallization of through-vias, especially of 3D integrated circuits.

Abstract: Substrate having a first partial substrate with a carrier layer and a second partial substrate, which is bonded to the first partial substrate. The second partial substrate has an insulator layer, which is applied on the carrier layer and has at least two regions each having a different thickness, thereby forming a stepped surface of the insulator layer, and a semiconductor layer, which is applied to the stepped surface of the insulator layer and is formed at least partially epitaxially, wherein the semiconductor layer has a planar surface which is opposite to the stepped surface of the insulator layer. Transistors are formed on the semiconductor layer.

Abstract: A method comprises applying a first electric field pulse to a nanowire comprising a channel and a charge trapping region configured to control conductivity of the channel, the first electric field pulse having a first polarity and a relatively large magnitude of integral of electric field during the pulse and, thereafter, applying at least one further electric field pulse to the nanowire, each further electric pulse having a second, opposite polarity and each respective further electric field pulse having a relatively small magnitude of integral of electric field during the pulse.

Abstract: A monolithically integrated semiconductor assembly having a power component, and a method for manufacturing a semiconductor assembly, are proposed, a monolithically integrated resistor element being provided between a first terminal and the second region, and a comparatively low-impedance electrical connection through the first region being provided between the resistor element and the second region.

Abstract: Three-dimensional structures are electrochemically fabricated by depositing a first material onto previously deposited material through voids in a patterned mask where the patterned mask is at least temporarily adhered to a substrate or previously formed layer of material and is formed and patterned onto the substrate via a transfer tool patterned to enable transfer of a desired pattern of precursor masking material. In some embodiments the precursor material is transformed into masking material after transfer to the substrate while in other embodiments the precursor is transformed during or before transfer. In some embodiments layers are formed one on top of another to build up multi-layer structures. In some embodiments the mask material acts as a build material while in other embodiments the mask material is replaced each layer by a different material which may, for example, be conductive or dielectric.

Abstract: A method of repairing a defective one of devices mounted on substrate is provided. Devices are arrayed on a substrate and electrically connected to wiring lines connected to a drive circuit, to be thus mounted on the substrate. The devices mounted on the substrate are then subjected to an emission test. If a defective device is detected in this test, a repair device is mounted at a position corresponding to a position of the defective device. At this time, after wiring lines connected to the defective device are cut off, the repair device is electrically connected to portions of the wiring lines, the portions of the wiring lines being located at positions nearer to the drive circuit side than the cut-off positions of the wiring lines.

Abstract: A method for stably activating pn-successive layers in a semiconductor element in a short time is disclosed. Pulsed beams, each of which has a pulse shape that is approximately rectangular, are projected from respective laser irradiation devices and successively combined into a pulsed beam equivalent to one pulse, with which the doped layer region is irradiated. By successively projecting the pulsed beams onto the doped layer region in this way, an effect is obtained which is the same as that of irradiating the doped layer region with a single pulsed beam having a long full-width at half maximum. A high activation ratio from a shallow region to a deep region of the doped layer region is enabled. This can stably activate the semiconductor element having the pn-successive layers as the doped layer region in a short time, making possible the manufacture of semiconductor elements having superior device characteristics.

Abstract: The present invention provides a novel method for increasing the amount of deuterium incorporated into trap sites of a transistor device during a deuterium passivation anneal by electrically pre-stressing the fabricated device prior to a deuterium anneal. The method of the present invention equally applies to SOI and CMOS technology. As a result, the incorporation of more deuterium during a deuterium anneal in the process flow reduces the number of undesirable trap sites.

Abstract: A nonvolatile read-only memory device, wherein a word line is on a substrate and the word line includes a metal layer a polysilicon line. A trapping layer is further located between the word line and the substrate. A polysilicon protection line is formed over the substrate and the polysilicon protection line connects the word line and a grounded doped region in the substrate, wherein the resistance of the polysilicon protection line is higher than that of the word line.

Abstract: In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.

Abstract: A method and a means for determining an IDDQ test limit of an integrated circuit are provided. In particular, a method is provided which includes measuring the IDDQ value of a test structure formed upon a die derived from the same lot of wafers as an integrated circuit. The method may further include setting the IDDQ test limit based upon the measured IDDQ value. In some embodiments, setting the IDDQ test limit may include correlating the IDDQ value of the test structure to calibration data. Accordingly, a means for conducting such a method may include one or more test structures formed upon a die and calibration data adapted to correlate a test structure IDDQ value to an IDDQ test limit of an integrated circuit. In some cases, the means for determining the IDDQ test limit may further include a means for increasing a substrate leakage current of the test structure.

Abstract: A heating conductor, in particular for a sensor for determining at least one gas component in the exhaust gases of internal combustion engines. The heating conductor formed from a cermet which contains platinum, at least one metal oxide, and at least two further precious metals. A method for manufacturing the heating conductor by applying a paste containing a platinum powder, a metal oxide powder, and at least two further precious metals, to a ceramic foil and sintering the paste and ceramic foil combination.

Abstract: A cathode includes a carbon nanotube layer, which is optimized with a low work function material, such as an alkali. The inclusion of the alkali material improves the field emission properties of the carbon nanotube layer.

Abstract: A liquid precursor for forming a thin film of ferroelectric metal oxide in an integrated circuit contains metal oxides in excess of the stoichiometrically balanced amount. When the precursor comprises strontium, bismuth, tantalum and niobium for forming strontium bismuth tantalum niobate, the precursor contains excess amounts of at least one of tantalum and niobium. Capacitors containing thin films of layered superlattice material made from a precursor containing excess tantalum and niobium show good polarizability and low percentage imprint after 1010 negative polarization switching pulses at 75° C., and after 109 negative polarization switching pulses at 125° C.

Abstract: The present invention discloses a method of manufacturing a thin film transistor, including: depositing an amorphous silicon layer, an insulating layer, and a gate metal layer on a substrate sequentially; patterning the insulating layer and the gate metal layer to form a gate insulating layer and a gate electrode; treating an impurity and a catalyst metal on the amorphous silicon layer using the gate electrode as a mask; and applying a DC voltage to both terminals of the amorphous silicon layer to form a polysilicon layer, the polysilicon layer having source and drain regions and an active area.

Abstract: A silicon carbide transistor (10) is formed from a silicon carbide film (14) that is formed on a silicon carbide substrate bulk (37). A conductor pattern layer (25) is formed on the silicon carbide film (14) and the silicon carbide film (14) removed from the silicon carbide substrate bulk (37) and attached to a substrate (11) of a dissimilar semiconductor material.

Abstract: An integrated circuit is formed containing a metal-oxide ferroelectric thin film. An voltage-cycling recovery process is conducted to reverse the degradation of ferroelectric properties caused by hydrogen. The voltage-cycling recovery process is conducted by applying from 104 to 1011 voltage cycles with a voltage amplitude of from 1 to 15 volts. Conducting voltage-cycling at a higher temperature in the range 30-200° C. enhances recovery. Preferably the metal oxide thin film comprises layered superlattice material. Preferably the layered superlattice material comprises strontium bismuth tantalate or strontium bismuth tantalum niobate. If the integrated circuit manufacture includes a forming-gas anneal, then the voltage-cycling recovery process is performed after the forming-gas anneal.

Abstract: The object of this invention is to provide a method whereby, during flip-chip connection using a thermosetting resin, it is possible to prevent the development of voids in the resin when the resin is hardened by pulse heating. The object is fulfilled by providing a method comprising heating a chip 4 to thereby harden a thermosetting resin 3 while applying a pressure to the chip 4 towards a substrate 1 to put a bump electrode 6 into contact with a wiring 2, wherein heating temperatures are adjusted appropriately according to:a first stage I of heating the thermosetting resin 3 to thereby spread it over the whole surface of substrate 1 which will carry the bump electrode 6 to thereby wet the surface with the resin 3;a second stage II of stimulating the gelation of thermosetting resin 3 by heating at a higher temperature than used in the first stage; anda third stage III of stimulating the hardening of thermosetting resin 3 by heating at a higher temperature than used in the second stage.

Abstract: A composite that protects thermal barrier coatings from the deleterious effects of environmental contaminants at operational temperatures is discovered. The thermal barrier coated parts have least two outer protective coatings that decrease infiltration of molten contaminant eutectic mixtures into openings in the thermal barrier coating.

Abstract: An article of manufacture having at least in part the surface appearance of brass includes a ceramic barrier coating applied to a base layer of Cu/Ni/Cr. The ceramic barrier coating includes an initial layer of ZrCn and an additional layer which is a nitrite, carbide or oxide of Zr, Ti, Si, Al or Hf.

Abstract: Disclosed is a method for programming an antifuse structure. The antifuse structure is programmed by applying an alternating current having alternating current pulses between a bottom and a top electrode to generate a conduction path through an antifuse material sandwiched between the electrodes. The conduction path is formed incrementally due to an electron flow produced as a result of each alternating current pulse thereby defining the conduction path at a substantially centered portion of the antifuse material.

Abstract: A very thin coating layer having a thickness of the order of 1-100 angstroms of a hydroxymethyl substituted phenol is applied to the surface of a metal material. The hydroxylmethyl substituted phenol, such as saligenin, is applied in the gaseous phase to the surface of the metal material maintained at a high temperature.By forming this ultra-thin coating layer, the heat bondability of a thermoplastic resin layer to the metal material can be effectively improved. This technique is advantageously used in various fields, for example, for production of bonded cans. The metal material comprises a steel plate substrate and a chromium-containing layer on the surface of the substrate, and the very thin layer is applied on the chromium-containing layer.