By Vibrating Or Impacting Patents (Class 438/472)
  • Patent number: 10290785
    Abstract: A laminating structure of an electronic device using a transferring element according to the present disclosure includes a target substrate, a bottom electrode formed on the target substrate, an electronic device which is bonded to the bottom electrode, a top contact formed on the electronic device, a transferring element which is placed between the bottom electrode and the electronic device on the target substrate, and a top electrode connected to the electronic device, wherein the transferring element attached to the carrier substrate comes into contact with the electronic device, and is then transferred onto the target substrate.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: May 14, 2019
    Assignee: CENTER FOR INTEGRATED SMART SENSORS FOUNDATION
    Inventors: Keon Jae Lee, Han Eol Lee, Do Hyun Kim, Jung Ho Shin, Seong Kwang Hong
  • Patent number: 9887125
    Abstract: A method of manufacturing a semiconductor device includes forming a field stop zone by irradiating a portion of a semiconductor body with a laser beam through a first surface of the semiconductor body. The portion has an oxygen concentration in a range of 5×1016 cm?3 and 5×1017 cm?3. Then the semiconductor body is irradiated with protons through the first surface and annealed in a temperature range of 300° C. to 550° C.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: February 6, 2018
    Assignee: Infineon Technologies AG
    Inventors: Holger Schulze, Hans-Joachim Schulze
  • Patent number: 9082936
    Abstract: A flexible light sheet includes a thin substrate that allows light to pass through it, a transparent first conductor layer overlying the substrate, an array of vertical light emitting diodes (VLEDs) printed as an ink over the first conductor layer, each of the VLEDs having a bottom electrode electrically contacting the first conductor layer, a dielectric material between the VLEDs overlying the first conductor layer, and a transparent second conductor layer overlying the VLEDs and dielectric layer, each of the VLEDs having a top electrode electrically contacting the transparent second conductor layer. Each individual VLED may emit light bidirectionally. The VLEDs are illuminated by a voltage differential between the first conductor layer and the second conductor layer such that bidirectional light passes through the first conductor layer and the second conductor layer. Phosphor layers may be deposited on both sides to create white light using blue VLEDs.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: July 14, 2015
    Assignee: Nthdegree Technologies Worldwide Inc.
    Inventors: Jeff Baldridge, Mark David Lowenthal, Bradley Steven Oraw, Thomas Frederick Soules
  • Patent number: 9006584
    Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: April 14, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas Dyer Bonifield, Byron Williams, Shrinivasan Jaganathan, David Larkin, Dhaval Atul Saraiya
  • Patent number: 8993996
    Abstract: A superlattice layer including a plurality of periods, each of which is formed from a plurality of sub-layers is provided. Each sub-layer comprises a different composition than the adjacent sub-layer(s) and comprises a polarization that is opposite a polarization of the adjacent sub-layer(s). In this manner, the polarizations of the respective adjacent sub-layers compensate for one another. Furthermore, the superlattice layer can be configured to be at least partially transparent to radiation, such as ultraviolet radiation.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 31, 2015
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Remigijus Gaska, Jinwei Yang, Alexander Dobrinsky
  • Patent number: 8951886
    Abstract: A method for mechanically separating a laminar structure from a first carrier assembly, comprising or consisting of a first carrier, wherein the laminar structure comprises a wafer and a second, stretchable carrier is disclosed. Also disclosed are the use of a particular separating aid for separating a laminar structure and a device for carrying out the method.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: February 10, 2015
    Assignee: Thin Materials AG
    Inventor: Franz Richter
  • Patent number: 8440546
    Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: May 14, 2013
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Ralph G. Nuzzo, John A. Rogers, Etienne Menard, Keon Jae Lee, Dahl-Young Khang, Yugang Sun, Matthew Meitl, Zhengtao Zhu
  • Patent number: 8421006
    Abstract: A device for generating sprays of charged droplets, and resulting nanoparticles, the device comprising a first needle connected to an electrical potential line to generate a first spray of charged particles from the first needle, and a second needle spaced apart from and facing the first needle, and connected to an electrical line configured to ground the second needle or to apply a voltage to the second needle that is the same polarity as the voltage applied to the first needle. The device also comprising an electric field modifier connected to the first needle, and configured to modify an electrical field to generate a second spray of charged particles from the second needle.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: April 16, 2013
    Assignee: MSP Corporation
    Inventors: Amir A. Naqwi, Christopher W. Fandrey, Zeeshan H. Syedain
  • Patent number: 8377801
    Abstract: A method of fabricating a nitride semiconductor light-emitting device providing a nitride semiconductor light-emitting device with a GaN layer, bringing the nitride semiconductor light-emitting device into contact with hydrogen separation metal, vibrating the nitride semiconductor light-emitting device and the hydrogen separation metal, removing hydrogen from the GaN layer of the nitride semiconductor light-emitting device and separating the hydrogen separation metal from the nitride semiconductor light-emitting device.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: February 19, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventor: Ho Sang Yoon
  • Publication number: 20120083099
    Abstract: The present invention provides a high yield pathway for the fabrication, transfer and assembly of high quality printable semiconductor elements having selected physical dimensions, shapes, compositions and spatial orientations. The compositions and methods of the present invention provide high precision registered transfer and integration of arrays of microsized and/or nanosized semiconductor structures onto substrates, including large area substrates and/or flexible substrates. In addition, the present invention provides methods of making printable semiconductor elements from low cost bulk materials, such as bulk silicon wafers, and smart-materials processing strategies that enable a versatile and commercially attractive printing-based fabrication platform for making a broad range of functional semiconductor devices.
    Type: Application
    Filed: October 11, 2011
    Publication date: April 5, 2012
    Applicant: The Board of Trustees of the University of Illinois
    Inventors: Ralph G. NUZZO, John A. ROGERS, Etienne MENARD, Keon Jae LEE, Dahl-Young KHANG, Yugang SUN, Matthew MEITL, Zhengtao ZHU, Heung Cho KO, Shawn MACK
  • Patent number: 8124437
    Abstract: Disclosed herein is a method for manufacturing a solar cell. The method includes the following steps. A substrate is provided. An article having a plurality of protrusions touches the surface of the substrate and thereby forming a plurality of indentations thereon. Subsequently, a transparent conductive layer is formed on the indented surface of the substrate, a photovoltaic layer is formed on the transparent conductive layer, and then a back electrode is form above the photovoltaic layer.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: February 28, 2012
    Assignee: Du Pont Apollo Limited
    Inventors: Chu-Wan Huang, Ching-Yee Chak
  • Patent number: 8124502
    Abstract: A semiconductor device manufacturing method is provided, including: providing a semiconductor substrate, forming on the semiconductor substrate a layer including a semiconductor compound and a dope additive, and thereafter forming an emitter region and gettering impurities by annealing the semiconductor substrate including the layer.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: February 28, 2012
    Assignee: Applied Materials, Inc.
    Inventor: Rafel Ferre i Tomas
  • Patent number: 8093077
    Abstract: The present invention relates to a method for manufacturing a crack free monocrystalline nitride layer having the composition AlxGa1-xN, where 0?x?0.3, on a substrate that is likely to generate tensile stress in the layer and to structures containing such layer and substrate. The method includes forming a nucleation layer on the substrate; forming a monocrystalline intermediate layer of aluminum or gallium nitride at a selected thickness on the nucleation layer; forming a monocrystalline seed layer of an AlBN compound in which the boron content is between 0 and 10% at a selected temperature and thickness on the intermediate layer with the thicknesses of the seed and intermediate layers being in a ratio of between 0.05 and 1; and forming the monocrystalline nitride layer of AlxGa1-xN nitride at a selected temperature on the seed layer, with the temperature of formation of the seed layer being 50 to 150° C.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: January 10, 2012
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventor: Hacene Lahreche
  • Patent number: 7943491
    Abstract: The present invention provides methods, systems and system components for transferring, assembling and integrating features and arrays of features having selected nanosized and/or microsized physical dimensions, shapes and spatial orientations. Methods of the present invention utilize principles of ‘soft adhesion’ to guide the transfer, assembly and/or integration of features, such as printable semiconductor elements or other components of electronic devices. Methods of the present invention are useful for transferring features from a donor substrate to the transfer surface of an elastomeric transfer device and, optionally, from the transfer surface of an elastomeric transfer device to the receiving surface of a receiving substrate. The present methods and systems provide highly efficient, registered transfer of features and arrays of features, such as printable semiconductor element, in a concerted manner that maintains the relative spatial orientations of transferred features.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: May 17, 2011
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Ralph G. Nuzzo, John A. Rogers, Etienne Menard, Keon Jae Lee, Dahl-Young Khang, Yugang Sun, Matthew Meitl, Zhengtao Zhu
  • Publication number: 20100289124
    Abstract: The present invention provides a high yield pathway for the fabrication, transfer and assembly of high quality printable semiconductor elements having selected physical dimensions, shapes, compositions and spatial orientations. The compositions and methods of the present invention provide high precision registered transfer and integration of arrays of microsized and/or nanosized semiconductor structures onto substrates, including large area substrates and/or flexible substrates. In addition, the present invention provides methods of making printable semiconductor elements from low cost bulk materials, such as bulk silicon wafers, and smart-materials processing strategies that enable a versatile and commercially attractive printing-based fabrication platform for making a broad range of functional semiconductor devices.
    Type: Application
    Filed: July 27, 2010
    Publication date: November 18, 2010
    Applicant: The Board of Trustees of the University of Illinois
    Inventors: Ralph G. NUZZO, John A. ROGERS, Etienne MENARD, Keon Jae LEE, Dahl-Young KHANG, Yugang SUN, Matthew MEITL, Zhengtao ZHU, Heung Cho KO, Shawn MACK
  • Patent number: 7790579
    Abstract: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: September 7, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Kohji Kanamori, Teiichirou Nishizaka, Noriaki Kodama, Isao Katayama, Yoshihiro Matsuura, Kaoru Ishihara, Yasushi Harada, Naruaki Minenaga, Chihiro Oshita
  • Patent number: 7772088
    Abstract: A multilayered substrate structure comprising one or more devices, e.g., optoelectronic, integrated circuit. The structure has a handle substrate, which is characterized by a predetermined thickness and a Young's modulus ranging from about 1 Mega Pascal to about 130 Giga Pascal. The structure also has a thickness of substantially crystalline material coupled to the handle substrate. Preferably, the thickness of substantially crystalline material ranges from about 100 microns to about 5 millimeters. The structure has a cleaved surface on the thickness of substantially crystalline material and a surface roughness characterizing the cleaved film of less than 200 Angstroms. At least one or more optoelectronic devices is provided on the thickness of material.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: August 10, 2010
    Assignee: Silicon Genesis Corporation
    Inventors: Francois J. Henley, Harry Robert Kirk, James Andrew Sullivan
  • Patent number: 7763500
    Abstract: First, a base structure provided with the main parts of a memory cell is prepared, and a lower electrode comprising a polycrystalline silicon film is thereafter formed on the base structure. Next, the surface of the lower electrode is thermally nitrided at a predetermined temperature to form a silicon nitride film. In the thermal nitridation of the lower electrode, the temperature is increased to a predetermined nitriding temperature, after which the temperature is reduced at a rate that is more gradual than usual. Aluminum oxide (Al2O3) or another metal oxide dielectric film is thereafter formed as the capacitive insulating film on the lower electrode, and an upper electrode is formed on the capacitive insulating film.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: July 27, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Takashi Arao, Kenichi Koyanagi, Kenji Komeda, Naruhiko Nakanishi, Hideki Gomi
  • Patent number: 7674692
    Abstract: Provided is a method of fabricating a nitride semiconductor light-emitting device comprising; providing a nitride semiconductor light-emitting device with a GaN layer, bringing the nitride semiconductor light-emitting device into contact with hydrogen separation metal, vibrating the nitride semiconductor light-emitting device and the hydrogen separation metal, removing hydrogen from the GaN layer of the nitride semiconductor light-emitting device and separating the hydrogen separation metal from the nitride semiconductor light-emitting device.
    Type: Grant
    Filed: July 8, 2005
    Date of Patent: March 9, 2010
    Assignee: LG Innotek Co., Ltd.
    Inventor: Ho Sang Yoon
  • Patent number: 7622367
    Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: November 24, 2009
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Ralph G. Nuzzo, John A. Rogers, Etienne Menard, Keon Jae Lee, Dahl-Young Khang, Yugang Sun, Matthew Meitl, Zhengtao Zhu
  • Patent number: 7615470
    Abstract: The present invention provides to a gallium nitride (GaN) semiconductor and a method of manufacturing the same, capable of reducing crystal defects caused by a difference in lattice parameters, and minimizing internal residual stress. In particular, since a high-quality GaN thin film is formed on a silicon wafer, manufacturing costs can be reduced by securing high-quality wafers with a large diameter at a low price, and applicability to a variety of devices and circuit can also be improved.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: November 10, 2009
    Assignee: Siltron Inc.
    Inventors: Yong Jin Kim, Dong Kun Lee
  • Patent number: 7166505
    Abstract: A method for making a semiconductor device is described. That method includes forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. The dielectric layer is modified so that it will be compatible with a gate electrode to be formed on the dielectric layer, and then a gate electrode is formed on the dielectric layer.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: January 23, 2007
    Assignee: Intel Corporation
    Inventors: Robert Chau, Reza Arghavani, Mark Doczy
  • Patent number: 7153760
    Abstract: Acoustic energy may be utilized to generate phonons for activating implanted species. As a result, greater activation may be achieved with lower thermal budgets. Higher temperatures utilized in conventional processes may result in damage to semiconductor wafers. In some embodiments, the acoustic energy may be coupled with rapid thermal annealing, laser annealing, or other annealing processes. The acoustic energy may be developed by vibrational sources, laser energy, or other sources.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: December 26, 2006
    Assignee: Intel Corporation
    Inventor: Reza M. Golzarian
  • Patent number: 7060510
    Abstract: Disclosed are electronic, plasmonic and opto-electronic components that are prepared using patterned photodeposited nanoparticles on a substrate surface. Also disclosed are ferroelectric nanolithography methods for preparing components, circuits and devices.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: June 13, 2006
    Assignee: The Trustees of the University of Pennsylvania
    Inventors: Dawn A. Bonnell, Xiaojun Lei, David Joseph Conklin
  • Patent number: 6828690
    Abstract: A process for heat-treating a single crystal silicon segment to influence the profile of minority carrier recombination centers in the segment. The segment has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the segment is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The segment is then cooled from the temperature of said heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a segment having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the segment. Platinum atoms are then in-diffused into the silicon matrix such that the resulting platinum concentration profile is substantially related to the concentration profile of the crystal lattice vacancies.
    Type: Grant
    Filed: August 4, 1999
    Date of Patent: December 7, 2004
    Assignee: MEMC Electronic Materials, Inc.
    Inventor: Robert J. Falster
  • Patent number: 6825100
    Abstract: A method for fabricating an Al—Si—containing alloy line, which is adapted to form a conductive line on a substrate, is described. A first conductive layer, a second conductive layer and an Al—Si—containing alloy layer are sequentially formed on the substrate. Then, the substrate temperature is rapidly lowered to between about 0° C. and 25° C. in about 1 second to 10 seconds. A patterned photo-resist layer is formed on the third conductive layer. The patterned photo-resist layer is used as a mask, and the third conductive layer, the Al—Si—containing alloy layer, the second conductive layer and the first conductive layer are etched to form the conductive line.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: November 30, 2004
    Assignee: Winbond Electronics Corporation
    Inventor: Ching-Tsai Chang
  • Publication number: 20030087071
    Abstract: A cover structure for an electronic device includes a plastic cover, an aluminum or aluminum alloy layer on the plastic cover, and an oxide layer of aluminum or aluminum alloy on the aluminum or aluminum alloy layer. A method of manufacturing the cover structure includes: (1) injection molding the plastic cover; (2) forming the aluminum or aluminum alloy layer on the plastic cover; and (3) anodizing the aluminum or aluminum alloy layer to form an oxide layer thereof.
    Type: Application
    Filed: December 20, 2001
    Publication date: May 8, 2003
    Inventor: Che-Yuan Hsu
  • Publication number: 20030010065
    Abstract: Methods of forming optical filament circuit patterns with planar and non-planar portions are provided. An optical filament circuit pattern is scribed by moving a filament guide and a substrate relative to one another at a speed between about 110 inches/minute and about 190 inches/minute, and dispensing an optical filament on, or in the vicinity of, a surface of the substrate. The filament or the substrate or both have adhesive surface(s). The adhesive surface is capable of being adhesively actuated by application of energy. Energy is applied simultaneous with, or subsequent to, scribing. Preferably, ultrasound energy is applied having an output power between about 2.0 watts and about 3.5 watts while applying a pressure to the filament between about 1.177 Newtons and about 1.324 Newtons. A portion of the filament circuit pattern is planar and another portion is non-planar. The non-planar portion traverses but does not contact or adhere to a pre-selected area of the substrate.
    Type: Application
    Filed: July 29, 2002
    Publication date: January 16, 2003
    Inventor: Raymond S. Keogh
  • Patent number: 6316335
    Abstract: Wafers, each including an MOS semiconductor component thereon, are introduced one by one into a single-wafer heat treatment system. First, hydrogen is introduced into the system and the wafer is heated up to a predetermined temperature in Step 1. Next, while the wafer temperature is kept constant at the predetermined temperature, the hydrogen sintering process is performed in Step 2. Then, the wafer is cooled down to another predetermined temperature or less within the system in Step 3. Finally, the wafer is taken out in Step 4. The time taken to perform a single cycle of the sintering process may be within three minutes. Accordingly, compared to a conventional process using a diffusion furnace, the throughput can be increased and the temperature response and uniformity of the wafer can also be improved. By taking the wafer out of the system after sintering and then cooling down it once, the damage caused in MOS interface states, for example, by a previous process step can be repaired in a short time.
    Type: Grant
    Filed: October 13, 1999
    Date of Patent: November 13, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshinori Takamori, Toru Nishiwaki
  • Patent number: 6313013
    Abstract: There are a device and method for protecting semiconductor material, wherein semiconductor material is processed on a surface of stabilized ice made from ultrapure water and particles of semiconductor material.
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: November 6, 2001
    Assignee: Wacker-Chemie GmbH
    Inventors: Dirk Flottmann, Gerhard Ast, Reinhard Wolf
  • Patent number: 6063697
    Abstract: A device for protecting semiconductor material includes a support and a surface made of ice formed from ultrapure water. Semiconductor material is situated on this support surface.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: May 16, 2000
    Assignee: Wacker-Chemie GmbH
    Inventors: Reinhard Wolf, Dirk Flottmann, Matthaus Schantz
  • Patent number: 5914189
    Abstract: A composite that protects thermal barrier coatings from the deleterious effects of environmental contaminants at operational temperatures is discovered. The thermal barrier coated parts have least two outer protective coatings that decrease infiltration of molten contaminant eutectic mixtures into openings in the thermal barrier coating.
    Type: Grant
    Filed: April 8, 1997
    Date of Patent: June 22, 1999
    Assignee: General Electric Company
    Inventors: Wayne Charles Hasz, Marcus Preston Borom, Curtis Alan Johnson
  • Patent number: 5710077
    Abstract: A method for the generation of stacking-fault-induced damage on the back of emiconductor wafers is by treating the back with loose hard-material particles which are suspended in a liquid. The back of the semiconductor wafer is brought into contact with the suspended hard-material particles and the hard-material particles are propelled tangentially to the back, under which circumstances they exert on the back of the semiconductor wafer forces which have essentially only tangentially directed components.
    Type: Grant
    Filed: July 9, 1996
    Date of Patent: January 20, 1998
    Assignee: Wacker Siltronic Gesellschaft fur Halbleitermaterialien AG
    Inventors: Gerhard Brehm, Rudolf Mayrhuber, Johann Niedermeier