Abstract: The present invention provides a method for producing an n-type Group III nitride semiconductor product having a high Si concentration and exhibiting favorable crystallinity. In the production method, specifically, an AlN buffer layer is formed on a sapphire substrate by MOCVD, and then a first layer (thickness: 2 ?m) is formed from undoped GaN on the buffer layer by MOCVD at 1,140° C. Subsequently, a second layer (thickness: 200 nm) is formed from SiO2 on the first layer by plasma CVD, and then the second layer is removed by use of BHF (buffered hydrofluoric acid). Next, a GaN layer (thickness: 50 nm) is grown, by MOCVD at 1,140° C., on the first layer exposed by removal of the second layer without supply of an n-type dopant gas. Thus, on the first layer is provided a third layer formed of n-type GaN doped with Si at a high concentration and exhibiting favorable crystallinity.

Abstract: The invention relates to the manufacture of an epitaxial layer, with the following steps: providing a semiconductor substrate; providing a Si—Ge layer on the semiconductor substrate, having a first depth; —providing the semiconductor substrate with a doped layer with an n-type dopant material and having a second depth substantially greater than said first depth; performing an oxidation step to form a silicon dioxide layer such that Ge atoms and n-type atoms are pushed into the semiconductor substrate by the silicon dioxide layer at the silicon dioxide/silicon interface, wherein the n-type atoms are pushed deeper into the semiconductor substrate than the Ge atoms, resulting in a top layer with a reduced concentration of n-type atoms; removing the silicon dioxide layer; growing an epitaxial layer of silicon on the semiconductor substrate with a reduced outdiffusion or autodoping.

Abstract: Methods of forming semiconductor devices with a layered structure of thin and well defined layer of activated dopants, are disclosed. In a preferred method, a region in a semiconductor substrate is amorphized, after which the region is implanted with a first dopant at a first doping concentration. Then a solid phase epitaxy regrowth step is performed on a thin layer of desired thickness of the amorphized region, in order to activate the first dopant only in this thin layer. Subsequently, a second dopant is implanted in the remaining amorphous region at a second doping concentration. Subsequent annealing of the substrate activates the second dopant only in said remaining region, so a very abrupt transition between dopant characteristics of the thin layer with first dopant and the region with the second dopant is obtained.

Abstract: A method of manufacturing a semiconductor device, which method comprises the step of epitaxially growing a stack comprising an n-type doped layer of a semiconductor material followed by at least one further layer of a semiconductor material, the stack being grown in one continuous cycle.

Abstract: A method of making a silicon-based electronic device is provided. The method includes, for example, the steps of forming a doped silicon layer on a surface of a substrate material and forming an undoped silicon capping layer on the doped silicon layer. The thin “capping” layers of undoped silicon prevent outgassing of the dopants underneath the cap. In this manner, the next deposition of doped silicon is not subject to autodoping by the previous doped silicon deposition.

Abstract: A solid-state pickup element achieves both improvement in sensitivity and reduction of pixel size and a method thereof, includes a first conductive type semiconductor area, which is formed at least so as to include the inside of the semiconductor substrate upward of the overflow barrier area inside the semiconductor substrate, and a charge accumulating area at the position corresponding to the first conductive type semiconductor area of the light receptive sensor part in the epitaxial layer on the semiconductor substrate. An overflow barrier area is formed in the semiconductor substrate, and the first conductive type semiconductor area is formed on the surface, respectively, wherein an epitaxial layer is formed on the semiconductor substrate, and a charge accumulating area is formed at the position corresponding to the first conductive type semiconductor area on the surface side of the epitaxial layer, thereby producing a solid-state pickup element.

Abstract: When the temperature of a silicon substrate is increased, a first annealing gas which is mainly composed of argon or the like that does not react with said silicon substrate with a trace of oxygen added thereto, is supplied to the position of the silicon substrate to prevent any unwanted reaction from occurring on the silicon substrate whose temperature is increasing. When the temperature of the silicon substrate is lowered, a second annealing gas which is mainly composed of nitrogen or the like which has a high thermal conductivity is supplied to the silicon substrate to quickly lower the temperature of the silicon substrate and prevent a doped impurity from being undesirably diffused.

Abstract: A method to prevent threshold shifts in MOS transistors due to auto-doping from heavily doped polysilicon layers. Isolation regions are provided in a semiconductor substrate separating active areas. A gate oxide layer is formed over the surface of the semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A tungsten silicide layer is deposited overlying the polysilicon layer. The tungsten silicide layer and the first polysilicon layer are etched to form MOS gates and bottom electrodes for dual polysilicon capacitors. An interpoly dielectric layer is deposited overlying entire surface of the semiconductor substrate. A doped polysilicon layer is deposited overlying the interpoly dielectric layer. A sealing oxide layer is deposited overlying the doped polysilicon layer to prevent out-diffusion of impurity ions into the semiconductor substrate and thereby preventing auto-doping. The tungsten silicide layer is annealed. Ions are implanted to form drain and source regions.

Abstract: There is disclosed a method for producing an epitaxial silicon single crystal wafer comprising the steps of growing a silicon single crystal ingot wherein nitrogen is doped by Czochralski method, slicing the silicon single crystal ingot to provide a silicon single crystal wafer, and forming an epitaxial layer in the surface layer portion of the silicon single crystal wafer. There can be manufactured easily and in high productivity an epitaxial silicon monocrystal wafer which has high gettering capability when a substrate having a low boron concentration is used, a low concentration of heavy metal impurity, and an excellent crystallinity.

Abstract: A method for controlling the autodoping during epitaxial silicon deposition. First, the substrate (10) is cleaned to remove any native oxide. After being cleaned, the substrate (10) is transferred to the deposition chamber in an inert or vacuum atmosphere to inhibit the growth of a native oxide on the surface of the wafers. A lower temperature (i.e., 500-850.degree. C.) capping layer (14) is deposited to prevent autodoping. Then, the temperature is increased to the desired deposition temperature and the remainder of the epitaxial layer (18) is deposited.

Abstract: The present invention provides an interconnect system. The interconnect system includes a substrate, a first dielectric layer deposited upon the substrate. The interconnect system further includes at least two electrically conductive interconnect lines formed upon the first dielectric layer. Each of the at least two interconnect lines have a top surface and side surfaces. Adjacent side surfaces of two adjacent interconnect lines define therebetween a space that has a dielectric constant substantially equal to 1. A dielectric film is bonded upon the top surface of the at least two interconnect lines. The dielectric film substantially prevents obstruction of the space by further process.

Abstract: A new method for planarization of shallow trench isolation is disclosed by the wet etching and plasma etching, due to the surface sensitivity of SACVD O.sub.3 -TEOS that depends on substrate. The method described herein includes a pad oxide layer, a silicon nitride layer, and a doped polysilicon oxide layer formed on a silicon substrate. A shallow trench is formed by photolithography and dry etching process to etch the doped polysilicon oxide layer, the silicon nitride layer, the pad oxide layer, and the silicon substrate. A SACVD O.sub.3 -TEOS layer is subsequently formed on the on the doped polysilicon oxide layer and filling into the trench, the deposition rate of the ozone-TEOS layer on the doped polysilicon oxide layer is slower than the deposition rate of the ozone-TEOS layer on the silicon wafer, the wet etching rate of the ozone-TEOS layer on the doped polysilicon oxide layer is faster than the etching rate of the ozone-TEOS layer on the silicon wafer.