Abstract: A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

Abstract: A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel unit is connected to the pixel TFT through a hole bored in at least a protective insulation film formed of an inorganic insulating material and formed above a gate electrode of the pixel TFT, and in an inter-layer insulation film disposed on the insulation film in close contact therewith. These process steps use 6 to 8 photo-masks.

Abstract: A method includes epitaxially growing a germanium (Ge) layer onto a Ge substrate and incorporating a compensating species with a compensating atomic radius into the Ge layer. The method includes implanting an n-type dopant species with a dopant atomic radius into the Ge layer. The method includes selecting the n-type dopant species and the compensating species in such manner that the size of the Ge atomic radius is inbetween the n-type dopant atomic radius and the compensating atomic radius.

Abstract: A method of manufacturing a semiconductor device, wherein thermal annealing of the source/drain regions is performed before reverse Halo implantation to form a reverse Halo implantation region. The method comprises: removing the dummy gate to expose the gate dielectric layer, so as to form an opening; performing reverse Halo implantation on the substrate via the opening, so as to form a reverse Halo implantation region in the channel of the device; activating the dopants in the reverse Halo implantation region by annealing; and performing subsequent device processing. Deterioration of the gate stack due to the reverse Halo ions implantation may be avoided by the present invention, such that the reverse Halo ions implantation may be applied to the device with a metal gate stack, and the short channel effects may be alleviated and controlled, thereby the performance of the device is enhanced.

Abstract: A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

Abstract: A method for generating n-type carriers in a semiconductor is disclosed. The method includes supplying a semiconductor having an atomic radius. Implanting an n-type dopant species into the semiconductor, which n-type dopant species has a dopant atomic radius. Implanting a compensating species into the semiconductor, which compensating species has a compensating atomic radius. Selecting the n-type dopant species and the compensating species in such manner that the size of the semiconductor atomic radius is inbetween the dopant atomic radius and the compensating atomic radius. A further method is disclosed for generating n-type carriers in germanium (Ge). The method includes setting a target concentration for the carriers, implanting a dose of an n-type dopant species into the Ge, and selecting the dose to correspond to a fraction of the target carrier concentration. Thermal annealing the Ge in such manner as to activate the n-type dopant species and to repair a least a portion of the implantation damage.

Abstract: An integrated circuit arrangement includes a Shockley diode or a thyristor. An inner region of the diode or of the thyristor is completely or partially shielded during the implantation of a p-type well. This gives rise to a Shockley diode or a thyristor having improved electrical properties, in particular with regard to the use as an ESD protection element.

Abstract: A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

Abstract: A method for forming a high-voltage drain metal-oxide-semiconductor (HVD-MOS) device includes providing a semiconductor substrate; forming a well region of a first conductivity type; and forming an embedded well region in the semiconductor substrate and only on a drain side of the HVD-MOS device, wherein the embedded region is of a second conductivity type opposite the first conductivity type. The step of forming the embedded well region includes simultaneously doping the embedded well region and a well region of a core regular MOS device, and simultaneously doping the embedded well region and a well region of an I/O regular MOS device, wherein the core and I/O regular MOS devices are of the first conductivity type. The method further includes forming a gate stack extending from over the embedded well region to over the well region.

Abstract: A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods such as deposition of layers at an elevated temperature provide easy formation of semiconductor structures with a modified lattice constant that permits an improved epitaxial interface.

Abstract: A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods such as deposition of layers at an elevated temperature provide easy formation of semiconductor structures with a modified lattice constant that permits an improved epitaxial interface.

Abstract: A p-channel field-effect transistor is formed on a semiconductor substrate. The transistor has an n-doped gate electrode, a buried channel, a p-doped source and a p-doped drain. The transistor is fabricated by a procedure in which, after an implantation for defining an n-type well, an oxidation is performed to form a gate-oxide layer and n-doped polysilicon is subsequently deposited. The latter is doped with boron or boron fluoride particles either in situ or by a dedicated implantation step. In a thermal process, the boron acceptors penetrate through the oxide layer into the substrate of the n-type well, where they form a p-doped zone, which serves for counter doping and sets the threshold voltage. This results in a steep profile that permits a shallow buried channel. The control of the number particles penetrating through the oxide layer is achieved by nitriding the oxide layer in an N2O atmosphere.

Abstract: A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, an LDD structure. A pixel TFT has LDD structure. A pixel electrode disposed in a pixel unit is connected to the pixel TFT through a hole bored in at least a protective insulation film formed of an inorganic insulating material and formed above a gate electrode of the pixel TFT, in an inter-layer insulation film disposed on the insolation film in close contact therewith. These process steps use 6 to 8 photo-masks.

Abstract: The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying sub-regions. The invention also includes a semiconductor construction that has transistor constructions with insulative spacers along gate sidewalls. Each transistor construction is between a pair source/drain regions that extend beneath the spacers. A source/drain extension extends the source/drain region farther beneath the transistor constructions on only one side of each of the transistor constructions. The invention also includes methods of forming semiconductor constructions.

Abstract: A semiconductor device comprising a gate having an approximately 0.05 &mgr;m channel length, an oxide layer below the gate, a self-aligned compensation implant below the oxide layer, a halo implant surrounding the self-aligned compensation implant below the oxide layer; and gate and drain regions on opposite sides of the halo implant and below the oxide layer.

Abstract: A process (10) for the production of a transistor device with reduced gate depletion is disclosed. The system includes providing a semiconductor substrate, forming a gate dielectric on an active area on the upper surface portion of the substrate and depositing a gate layer on top of the gate oxide. Next, the gate is implanted (12) with Boron and the N-doped regions of gate are patterned (14) and implanted (16).

Abstract: A thin film photovoltaic devices is described, having a glass substrate 11 over which is formed a thin film silicon device having an n++ layer 12, a p layer 13 and a dielectric layer 14 (typically silicon oxide or silicon nitride). To create a connection through the p layer 13 to the underlying n++ layer 12, a column of semi-conductor material is heated, the column passing through the various doped layers and the material in the column being heated or melted to allow migration of dopant between layer of the device in the region of the column.

Abstract: A method of manufacturing a MOS transistor. A substrate having a gate oxide layer, a gate electrode and spacers attached to the sidewalls of the gate electrode is provided. A source/drain (S/D) implantation is conducted to form a source/drain region in the substrate on each side of the gate electrode. A self-aligned silicide (Salicide) process is carried out to form a self-aligned silicide layer over the exposed gate electrode and source/drain region. A silicon nitride layer serving as an etching stop is formed over the substrate. A fluoride blanket implantation of the silicon nitride etching stop layer is carried out using an implantation dosage of about 5×1013˜5×1014 cm−2 and at an implantation energy level between 2 KeV˜5 KeV. The fluorides implanted into the silicon nitride layer capture hydrogen within the silicon nitride layer, thereby reducing free hydrogen concentration and increasing threshold voltage stability of the MOS transistor.

Abstract: The method of fabricating a semiconductor device includes the steps of selectively forming an insulating oxide layer in a semiconductor substrate having a first conductivity type, wherein the semiconductor substrate has first and second regions; forming impurity layers having a second conductivity type in the first and second regions of the semiconductor substrate; forming a first mask layer in the second region of the semiconductor substrate; forming impurity layers having the second conductivity type in the first region of the semiconductor substrate by performing serial ion implantations with different doses of dopants at different acceleration energies; forming a second mask layer in the first region of the semiconductor substrate; and forming impurity layers having the first conductivity type in the second region of the semiconductor substrate by performing serial ion implantations with different doses of dopants at different acceleration energies.

Abstract: The present invention provides a flash memory having a split gate structure and virtual ground array structure, wherein a high impurity concentration region of a first conductivity type is provided in a drain adjacent region of a channel region under a floating gate electrode, and the high impurity concentration region has a highest impurity concentration in the channel region, and wherein a low impurity concentration region of a first conductivity type is provided in the channel region but at a part not covered by the floating gate.

Abstract: A method for incorporating an ion implanted channel stop layer under field isolation for a twin-well CMOS process is described in which the layer is placed directly under the completed field isolation by a blanket boron ion implant over the whole wafer. The channel stop implant follows planarization of the field oxide and is thereby essentially at the same depth in both field and active regions. Subsequently implanted p- and n-wells are formed deeper than the channel stop layer, the n-well implant being of a sufficiently higher dose to over compensate the channel stop layer, thereby removing it's effect from the n-well. A portion of the channel stop implant under the field oxide adjacent the p-well provides effective anti-punchthrough protection with only a small increase in junction capacitance. The method is shown for, and is particularly effective in, processes utilizing shallow trench isolation.

Abstract: This invention obtains desired operating characteristics from an MISFET in which a p-type silicon gate electrode is used by preventing the leakage of boron into the channel region in the following way. N-type amorphous silicon 9n is formed by ion-implanting phosphorus into an amorphous silicon. Next, boron is ion-implanted in n-type amorphous silicon 9n to convert it into p-type amorphous silicon 9p. Amorphous silicon 9p is then crystallized. Finally, the gate electrode of the MISFET is constructed of the p-type polycrystalline silicon, which has been obtained in the above steps, and in which phosphorus and boron have been implanted.

Abstract: In a method is described for producing an MOS transistor structure with elevated body conductivity, a substrate layer is prepared and body regions are formed therein the body regions defining a main surface of the transistor structure and at least one channel region is also formed. Gate oxide and gate electrodes are formed in the region of the main surface, and source regions are formed that extend from the main surface into the body regions. An implantation of dopant of a first conductivity type occurs in at least a part of the channel region, this implantation dosage being controlled such that a re-doping of the body region into an area of the first conductivity type does not occur in the implantation region.

Abstract: A method of contact ion implantation is disclosed. Only one mask and a dosage-enhanced implantation is utilized to form different types of doped contact regions. A blanket ion implantation is first carried out, and all the contact regions of first and second type are formed with the first conductive type impurities. Then a mask is defined to cover the first type contact regions and expose the second type regions. A second ion implantation is now carried out to implant impurity ions of second conductive type into the second type contact regions. The dosage of these second conductive type ions is determined so that, the second type contact regions are convert from the first conductive type into section conductive type.

Abstract: A nonvolatile semiconductor memory device having a semiconductor substrate of a first conductive type, a floating gate and a control gate provided on the semiconductor substrate, at least a pair of impurity diffusion layers of a second conductive type defining source and drain and disposed in the semiconductor substrate in a spaced relation to each other so as to define a channel having a region covered with the floating gate and a region uncovered with the floating gate, the region uncovered with the floating gate defining a split gate, a first impurity diffusion layer region formed in the semiconductor substrate so as to be disposed at least at an area between the pair of diffusion layers, and a second impurity diffusion layer region having an impurity concentration lower than the first impurity diffusion layer region and formed in the semiconductor substrate so as to be disposed at the split gate.

Abstract: Semiconductor device and method for fabricating the same, is disclosed, which can maintain a threshold voltage constant despite of decreased channel width, the device including a first, and a second conductive type wells in a substrate, a first, and a second gate insulating films on the first, and the second conductive type wells, a first gate electrode on the first gate insulating film, the first gate electrode being doped with a second conductive type except for edges of the first gate electrode in a channel width direction counter doped with a first conductive type, a second gate electrode on the second gate insulating film, the second gate electrode being doped with a first conductive type except for edges of the second gate electrode in a channel width direction counter doped with a second conductive type, and isolating regions formed between the first, and second conductive type wells, the first, and second gate insulating films, and the first, and second gate electrodes.

Abstract: A field effect transistor with reduced corner device problems comprises source and drain regions formed in a substrate, a channel region between the source and drain regions, isolation regions in the substrate adjacent the source, channel and drain regions; and a gate having a gate dopant over the channel region and separated therefrom by a gate dielectric. The isolation regions define corner regions of the channel along interfaces between the channel and isolation regions. The gate includes regions depleted of the gate dopant and overlapping at least the channel region and the isolation regions, such that voltage thresholds of the channel corner regions beneath depleted portions of the gate conductor layer are increased compared to regions of the channel between the corner regions.The field effect transistor with reduced dopant concentration on the MOSFET gate "corner" has an improved edge voltage tolerance.

Abstract: A semiconductor device is formed on a semiconductor substrate with an N-well and a P-well with source/drain sites in the N-well and in the P-well by the following steps. Form a gate oxide layer and a gate electrode layer patterned into a gate electrode stack with sidewalls over a substrate with N-well and P-well. Form N- LDS/LDD regions in the P-well. Form N- LDS/LDD regions in the P-well and P- lightly doped halo regions in the P-well below the source site and the drain site in the P-well. Form a counter doped halo region doped with N type dopant below the source region site in the P-well. Form spacers on the gate electrode sidewalls. Then, form lightly doped regions self-aligned with the gate electrode in the source/drain sites. Form N+ type doped source/drain regions deeper than the N- LDS/LDD regions in the P-well in the source/drain sites. Form P+ type doped source/drain regions deeper than the P- LDS/LDD regions in the N-well in the source/drain sites.

Abstract: An epitaxial layer with a doping of approximately 10.sup.12 atoms per cm.sup.2 is used in accordance with the resurf condition for the high-voltage circuit element in high-voltage integrated circuits of the resurf type. If the circuit comprises a zone which is provided in the epitaxial layer, which is of the same conductivity type as the substrate, and to which a high voltage is applied, the doping between this zone and the substrate must in addition be sufficiently high for preventing punch-through between the zone and the substrate. A known method of complying with these two requirements is to make the epitaxial layer very thick. It is found in practice, however, that this method is often not very well reproducible. According to the invention, the epitaxial layer is provided in the form of a high-ohmic layer which is doped from the upper side (3a) and from a buried layer (3b).

Abstract: A method for controlling the implantation of ions into a target. An ion source chamber having a filament for causing evolution of the ions to be implanted is provided. An ion source reactant gas is provided for providing a source of the ion species to be implanted. A counteracting gas is provided to counter the chemical transport from or to the filament depending on the reaction between the ion source gas ions and the filament and to compensate for the reaction. The ion source reactant is introduced into the ion source chamber. Parameters regarding electrical or physical characteristics of the filament are measured. The counteracting gas is introduced based upon the measured parameters, wherein the counteracting gas forms ions to compensate for removal or deposition of material on the filament. The ions to be implanted are extracted from ion source chamber and directed to the target.

Abstract: The life of a source filament in an ion implantation tool is extended by providing in the ion implantation tool both an ion source reactant gas for providing a source of ion species to be implanted and a counteracting gas to counter the chemical transport from or to the filament, depending upon the reaction that occurs between the ion source gas ions and the source filament.

Abstract: In fabricating a buried p-channel MOS transistor using an n-type substrate, a shallow n-type diffused layer is formed by ion implantation in each of intended source and drain regions so as to become oppositely adjacent to the shallow p-type diffused layer under the gate electrode. After that p-type diffused layers to serve as source and drain are formed by ion implantation through the n-type diffused layers, and the implanted impurities are activated. In consequence, impurity concentration at the substrate surface becomes lower in the section right under each end of the gate electrode than in the gate middle sections. This measure brings about suppression of the short channel effect inherent to conventional buried-channel MOS transistors and makes it possible to shorten the physical gate length.

Abstract: A fabrication method of a semiconductor device with the CMOS structure, which suppresses the sheet resistance of silicide layers of a refractory metal in an n-channel MOSFET at a satisfactorily low level while preventing the junction leakage current in a p-channel MOSFET from increasing. An n-type dopant is selectively ion-implanted into surface areas of a first pair of n-type source/drain regions and a surface area of a first gate electrode in an NMOS region at a first acceleration energy, thereby forming a first plurality of amorphous regions in the NMOS region. The n-type dopant is ion-implanted into surface areas of the second pair of p-type source/drain regions and a surface area of the second gate electrode in a PMOS region at a second acceleration energy lower than the first acceleration energy, thereby forming second plurality of amorphous regions in the PMOS region.

Abstract: A P-type impurity is doped by oblique ion implantation into N-type impurity diffusion layers formed respectively on both sides of a gate electrode of a Pch MOS transistor, thereby canceling the impurity of at least a portion of an N-type region overlapped by the gate electrode, to thereby suppress a rise in the threshold voltage of the P-channel type MIS transistor due to the N-type impurity diffusion layer and suppress fluctuations in the amount of current that can be made to flow and the current-driving capacity.

Abstract: First and second conductivity type regions are produced in a polysilicon layer using only a single masking step. In one embodiment, the polysilicon layer is doped to a first conductivity type. A first oxide layer is then formed and patterned over the polysilicon layer to cover a first region and expose a second region of the polysilicon layer. The exposed second region of the polysilicon layer is then counter-doped, with the first oxide layer acting as a mask to prevent counter-doping of the underlying first region of the polysilicon layer. In accordance with the present invention, n-channel devices with n-type or p-type polysilicon gates and p-channel devices with p-type or n-type polysilicon gates can be formed without having to add a single process step. Thus, n-channel and p-channel devices with two different threshold voltages can be realized without adding a single process step.

Abstract: A method for forming twin-tub wells in a semiconductor substrate is disclosed. The present invention includes forming a first silicon oxide layer on the substrate. A silicon nitride layer is patterned on a portion of the first silicon oxide layer by a photoresist mask. First-type ions are implanted over the substrate not covered by the silicon nitride layer. Next, a second silicon oxide layer formed by a liquid phase deposition method is deposited on a portion of the first silicon oxide layer not covered by the silicon nitride layer. After the silicon nitride layer is removed, second-type ions are implanted over the substrate not covered by the second silicon oxide layer. Finally, the substrate is drived-in such that a first-type well and a second-type well are formed under the first silicon oxide layer.

Abstract: The number of surface defects in semiconductor materials having a volatile species, particulary group-III nitride-based semiconductor devices, are reduced by first implanting species atoms into the semiconductor sample to fill some of the surface layer species vacancies created by growth and device fabrication processes, and then rapid thermal annealing the sample to repair broken bonds and crystalline defects and to move implanted species atoms from interstitial to substitutional sites. An optional third step deposits a dummy layer on the sample surface prior to implantation, making possible an implantation profile that places a higher density of species atoms in the surface layer than is attainable without the dummy layer and to inhibit species atoms from leaving the sample during high-temperature processing steps that follow.

Abstract: A semiconductor device fabrication process in which an active region of a semiconductor device is formed by diffusing a dopant out of a sidewall spacer. According to the process, a gate electrode is formed on a substrate and an active region of the substrate adjacent the gate electrode is doped with a first dopant of a first conductivity type to form a heavily-doped region in the active region. A spacer layer having a second dopant disposed therein is then formed. The second dopant has a second conductivity type opposite of the first conductivity type. Portions of the spacer layer are removed to form a spacer containing the second dopant on a sidewall of the gate electrode. The second dopant is diffused out of the spacer into a portion of the heavily-doped region to form a lower conductivity region in the active region. The lower conductivity region may form an LDD region of an LDD structure.

Abstract: A BiCMOS method and device. The BiCMOS device achieves improved performance through the use of wrap-around silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, and through separate implants for base regions of the bipolar transistors and source/drains of the MOSFETS.

Abstract: A photoconductive switching device is disclosed that has an enhanced speed of response so that its closed (low) and open (high) resistive states are obtained in response to optical illumination in the less than nanosecond regime. The enhanced speed of response is achieved by neutron irradiation of a material preferably comprising GaAs:Si:Cu. An application of the improved photoconductive switching devices is disclosed which allows the realization of a high-power, frequency-agile RF source topology.