Abstract: A thin-film transistor (1) of the present invention includes an insulating substrate (2), a gate electrode (3) which has a predetermined shape and is formed on the insulating substrate (2), a gate insulating film (4) formed on the gate electrode (3), and a semiconductor layer (5) which is polycrystalline ZnO and is formed on the gate insulating film (4). The semiconductor layer (5) is immersed in a solution in which impurities are dissolved so that the impurities are selectively added to a grain boundary part of the polycrystalline ZnO film. Subsequently, a source electrode (6) and a drain electrode (7) are formed so as to have a predetermined shape. Next, a protection layer (8) is formed on the source electrode (6) and the drain electrode (7). Thus, a thin-film transistor which has a good subthreshold characteristic and has a zinc oxide film as a base of an active layer can be realized.

Abstract: An integrated circuit arrangement includes a Shockley diode or a thyristor. An inner region of the diode or of the thyristor is completely or partially shielded during the implantation of a p-type well. This gives rise to a Shockley diode or a thyristor having improved electrical properties, in particular with regard to the use as an ESD protection element.

Abstract: Methods of developing or removing a select region of block copolymer films using a polar supercritical solvent to dissolve a select portion are disclosed. In one embodiment, the polar supercritical solvent includes chlorodifluoromethane, which may be exposed to the block copolymer film using supercritical carbon dioxide (CO2) as a carrier or chlorodiflouromethane itself in supercritical form. The invention also includes a method of forming a nano-structure including exposing a polymeric film to a polar supercritical solvent to develop at least a portion of the polymeric film. The invention also includes a method of removing a poly(methyl methacrylate-b-styrene) (PMMA-b-S) based resist using a polar supercritical solvent.

Abstract: Diffusion of As in SiGe of MOS transistors based on Si/SiGe is prevented by ion implanting boron. Embodiments include forming As source/drain extension implants in a strained Si/SiGe substrate, ion implanting boron at between the As source/drain extension implant junctions and subsequently annealing to activate the As source/drain extensions, thereby preventing distortion of the originally formed junction.

Abstract: Methods and apparatus for fabricating stacked capacitor structures, which include barrier layers, are disclosed. According to one aspect of the present invention, a method for reducing outdiffusion within an integrated circuit includes forming a gate oxide layer over a substrate, and further forming a silicon plug over a portion of the gate oxide layer. A silicon dioxide layer is then formed over the gate oxide layer, and is arranged around the silicon plug. A first barrier film is formed over the silicon plug, and a dielectric layer is formed over the silicon dioxide layer. In one embodiment, forming the first barrier film includes forming a first oxide layer over the silicon plug, nitridizing the first oxide layer, and etching the nitridized first oxide layer.

Abstract: A method for fabricating an anti-fuse cell using an undoped polysilicon film as a mask in defining the anti-fuse window is described. A layer of silicon oxide is provided over the surface of a semiconductor substrate. A first undoped polysilicon layer is deposited overlying the silicon oxide layer. The first undoped polysilicon layer is covered with a photoresist layer patterned to form a mask. The first undoped polysilicon layer and a portion of the silicon oxide layer are etched away where they are not covered by the mask to form a cell opening. The mask and the remaining silicon oxide within the cell opening are removed. An insulating layer is deposited over the surface of the first undoped polysilicon layer and within the cell opening. A second polysilicon layer is deposited overlying the insulating layer and doped. The second polysilicon layer is patterned to form an anti-fuse cell. Gate electrodes and source and drain regions are formed completing the fabrication of the integrated circuit device.