Abstract: A method for fabricating a high-voltage transistor with an extended drain region includes forming in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls; then partially filling each of the trenches with a dielectric material that covers the first and second sidewalls. The remaining portions of the trenches are then filled with a conductive material to form first and second field plates. Source and body regions are formed in an upper portion of the mesa, with the body region separating the source from a lower portion of the mesa. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: Methods and structures for controlling wafer curvature during fabrication of integrated circuits caused by stressed films. The methods include controlling the conductor density of wiring levels, adding compensating stressed film layers and disturbing the continuity of stress films with the immediately lower layer. The structure includes integrated circuits having compensating stressed film layers.

Abstract: A power MOSFET device and manufacturing method thereof, includes the steps of selectively depositing a first conductive material in the middle region at the bottom of a contact trench and contacting with light-doped N-type epitaxial layer to form a Schottky junction and depositing a second conductive material at the side wall and bottom corner of the contact trench and contacting with P-type heavy-doped body region to form an ohmic junction. The first and second conductive materials can respectively optimize the performance of the ohmic contact and the Schottky contact without compromise. Meanwhile, the corner of the contact trench is surrounded by P-type heavy-doped region thereby effectively reducing the leakage currents accumulated at the corner of the contact trench.

Abstract: A power MOSFET device and manufacturing method thereof, includes the steps of selectively depositing a first conductive material in the middle region at the bottom of a contact trench and contacting with light-doped N-type epitaxial layer to form a Schottky junction and depositing a second conductive material at the side wall and bottom corner of the contact trench and contacting with P-type heavy-doped body region to form an ohmic junction. The first and second conductive materials can respectively optimize the performance of the ohmic contact and the Schottky contact without compromise. Meanwhile, the corner of the contact trench is surrounded by P-type heavy-doped region thereby effectively reducing the leakage currents accumulated at the corner of the contact trench.

Abstract: Mask patterns used for forming patterns or trenches may include first mask patterns, which may be formed by a typical photolithography process, and second mask patterns, which may be formed in a self-aligned manner between adjacent first mask patterns. A sacrificial layer may be deposited and planarized such that the tops of the first mask patterns and the second mask patterns have planar surfaces. After the planarization of the sacrificial layer, the remaining the sacrificial layer may be removed by an ashing process.

Abstract: A high-voltage transistor includes first and second trenches that define a mesa in a semiconductor substrate. First and second field plate members are respectively disposed in the first and second trenches, with each of the first and second field plate members being separated from the mesa by a dielectric layer. The mesa includes a plurality of sections, each section having a substantially constant doping concentration gradient, the gradient of one section being at least 10% greater than the gradient of another section. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A semiconductor device fabricating method for forming a boron doped silicon film includes the step of forming the boron doped silicon film on a substrate at an inner temperature of the reaction furnace ranging from about 460 to 600° C. or at an average velocity of reaction gases in the reaction furnace being not great than about 2200 cm/min. Further, a substrate processing apparatus for forming a boron doped silicon film on a substrate includes a gas supply line for supplying BCl3 to the reaction furnace. The gas supply line is installed in a portion of the reaction furnace opposite to a heater, and has an outlet for discharging BCl3. The outlet of the gas supply line is provided at an upstream side of gas flow in the reaction furnace.

Abstract: A lithography method for fabricating structures of etch-resistant metal-semiconductor compound on a substrate with sub-micrometer scale resolutions is described. Superposed layers of metal and semiconductor capable of reacting with each other to form etch-resistant metal/semiconductor compound are deposited on the substrate. Radiation from a X-ray/EUV source propagates through a patterned X-ray transparent/EUV reflective mask and is projected on the superposed metal and semiconductor layers. The X-ray transparent mask includes X-ray absorbing patterns imparted to the X-ray radiation while the EUV reflective mask includes EUV absorbing patterns also imparted to the EUV radiation. The energy of X-ray/EUV photons is absorbed locally by the metal and semiconductor layers. Absorption of this energy induces a reaction between the two layers responsible for the formation of etch-resistant metal/semiconductor compound with structures corresponding to the patterns imparted to the radiation by the X-ray/EUV mask.

Abstract: A method and an apparatus for growing a layer on one surface of a wafer by liquid phase deposition are provided. At first, a first wafer is putted on a first wafer-holder by its first surface. Then, a growth-liquid vessel having a first opening at the bottom is mounted on the first wafer-holder. Thereafter, a growth liquid is poured into the growth-liquid vessel to expose a second surface of the first wafer to the growth liquid for growing the layer on the second surface of the first wafer. Then, the, first wafer is taken out from the first wafer-holder to obtain a wafer with a layer grown only on one surface.

Abstract: Lifetime of a short-channel NMOS device is increased by modifying distributions of electrically active LDD dopant at boundaries of the device's LDD regions. The LDD dopant distributions are modified by implanting counter-dopants at the boundaries of the LDD regions. Group III counter-dopants such as boron and group IV elements such as silicon alter activation properties of the LDD dopant. The dopant distributions are modified at the device's n-junctions to reduce the maximum electric field displacement at an interface defined by the device's gate and substrate. The dopant distributions can be further modified to shape the n-junctions such that hot carriers are injected away from the gate.

Abstract: A compound semiconductor device is manufactured by forming a carbon-doped compound semiconductor device at a predetermined growth temperature on a compound semiconductor substrate, stopping the growth and changing the growth temperature of the compound semiconductor layer, including the carbon-doped compound semiconductor layer, to a predetermined temperature under an atmosphere comprising an alkylarsine, thereby avoiding the formation of free atomic hydrogen and preventing hydrogen contamination of the C-doped compound semiconductor layer. As a result, the amount of coupling between hydrogen and carbon in the carbon-doped compound semiconductor layer is significantly reduced, thereby preventing lowering of the carbon carrier concentration. The present method enables formation of a C-doped GaAs base layer without deterioration of electrical characteristics, and formation of a laser having a second clad layer of C-doped compound semiconductor layer with improved reliability.

Abstract: This invention pertains to the embedding of a information storage device within, or attached to, the carriers used to transport work in progress from step to step in the semiconductor manufacturing process. The carrier can be a tray having sites for several semiconductor dies, tubes for carrying several dies together, lead frames, wafer cassettes or individual die sockets. The information storage device can be formed integrally with the carrier or formed separately and attached or secured to the carrier.

Abstract: A method for making a semiconductor device comprises: depositing at least one Group II-VI compound semiconductor layer comprising at least one Group II element selected from the group consisting of zinc, magnesium, manganese, beryllium, cadmium and mercury and at least one Group VI element selected from the group consisting of oxygen, sulfur, selenium and tellurium onto a Group III-V compound semiconductor layer comprising at least one Group III element selected from the group consisting of gallium, aluminum, boron and indium and at least one Group V element selected from the group consisting of nitrogen, phosphorus, arsenic, antimony and bismuth; whereinbefore depositing the Group II-VI compound semiconductor layer, a particle beam composed of at least one Group II element selected from the group consisting of zinc, magnesium, beryllium, cadmium and mercury is radiated onto the Group III-V compound semiconductor layer in a dose of 8.times.10.sup.-4 Torr.multidot.sec or more.

Abstract: A fabricating method of compound semiconductor device is proposed which has a step of varying selective growth ratio of crystal by changing either a mean free path of material gas in gas atmosphere for use in crystal growth or a thickness of a stagnant layer of the material gas, using selective growth mask having opening portion consisting of first region having a narrow width and second region having a wide width.

Abstract: A method for forming an in-situ doped amorphous or polycrystalline silicon thin film on a substrate is provided. The method includes placing the substrate in a reaction chamber of a CVD reactor and introducing a silicon gas species into the reaction chamber. The flow of the silicon gas species is continued for a time period sufficient to dehydrate the substrate and form a thin layer of silicon. Following formation of the thin layer of silicon, a dopant gas species is introduced into the reaction chamber and continued with the flow of the silicon gas species to form the doped silicon thin film. In an illustrative embodiment a phosphorus doped amorphous silicon thin film for a cell plate of a semiconductor capacitor is formed in a LPCVD reactor.

Abstract: A compound semiconductor light emitting device of high performance and a method which can industrially prepare the same are provided. The compound semiconductor light emitting device includes a GaAs substrate, a buffer layer consisting of GaN, having a thickness of 10 nm to 80 nm, which is formed on the substrate, an epitaxial layer consisting of Al.sub.x Ga.sub.1-x N(0.ltoreq.x<1) which is formed on the buffer layer, an incommensurate plane which is located on the interface between the buffer layer and the epitaxial layer, a light emitting layer which is formed on the epitaxial layer, and a cladding layer which is formed on the light emitting layer. The buffer layer is formed by organic metal chloride vapor phase epitaxy at a first temperature, while the epitaxial layer is formed by organic metal chloride vapor phase epitaxy at a second temperature which is higher than the first temperature. The light emitting layer preferably consists of In.sub.y Ga.sub.1-y N (0<y<1) which is doped with Mg.

Abstract: On a surface of a p-type GaAs (111)B substrate 11, a mesa groove is formed along a [211]A direction. TDMAAs as a group V material and TMGa as a group III material are supplied at 8.times.10.sup.-3 Pa and 8.times.10.sup.-4 Pa, respectively, to grow n-type GaAs 13 dominantly on a side surface of a mesa 12. Subsequently, the group V material is changed to metal As. As.sub.4 and MAGa are supplied at 5.times.10.sup.-3 Pa and 8.times.10.sup.-4 Pa, respectively, to grow p-type GaAs 14 only on a side surface of the GaAs 13. Then, the group V material is again changed to TDMAAs. TDMAAs and TMGa are supplied both at 8.times.10.sup.-4 Pa to grow p-type GaAs 15.

Abstract: In a method for growing a III-V group compound semiconductor crystal, as a Si dopant, a compound including a Si atom bonded to an alkyl group and a hydrogen atom is used. Also, a compound including two Si atoms in one molecule thereof, at least one of said Si atoms being bonded to a hydrogen atom, and at least the other of said Si atoms being bonded to an alkyl group can be used. Further, a compound including two Si atoms in one molecule thereof, at least one of said Si atoms being bonded to a hydrogen atom, and at least the other of said Si atoms being bonded to a phenyl group or a compound including a Si atom bonded to an organic amino group can be used. Si can be doped evenly at a high concentration at a low temperature with a safe operation by the invention.

Abstract: A doped film forming method comprising, the steps of preparing gas source for supplying a film forming gas into the process tube, gas source for supplying doping gases, in which a dope is included, into the process tube, a dry pump for exhausting the process tube, and an apparatus for burning a not-reacted element in waste gas, arranging a plurality of substrates in the process tube in such a way that they are separated from their adjacent ones by a certain interval, exhausting the process tube to keep it reduced in pressure, heating the substrates in the process tube to a temperature range of 500.degree.-600.degree. C., controlling amounts of the doping and film forming gases, while exhausting the process tube, at the ratio of the amount of the film forming gas to the amount of the doping gases being in the range of 1 to 1.625.times.10.sup.-3 to 2.125.times.10.sup.-3, and causing the doping and film forming gases to be reacted with the substrates.