Sheet Resistance (i.e., Dopant Parameters) Patents (Class 438/934)
  • Patent number: 7018856
    Abstract: A multi-point calibration standards and a method of fabricating calibration standards which are used to quantify the dose or concentration of a dopant or impurity in a silicon matrix. The calibration standards include a set of calibration standard wafers for each dopant or impurity to be quantified. On each calibration standard wafer in the set is provided a silicon matrix incorporated with one of various concentrations, by weight, of the dopant or impurity in the silicon. The atomic concentration of the dopant or impurity in the silicon on each wafer in the set is measured. A calibration curve is then prepared in which the silicon/dopant or silicon/impurity ratio on each calibration standard wafer in the set is plotted versus the atomic concentration of the dopant or impurity in the silicon on the wafer.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: March 28, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chia-Ching Wan, Min-Ta Yu
  • Patent number: 6579730
    Abstract: Generally, a method for monitoring a process of removing native oxides from an at least partially exposed layer disposed on a substrate is provided. In one embodiment, a method for monitoring includes disposing the substrate in a process chamber, exposing the at least partially exposed layer to a reactive pre-clean process, removing the substrate from the process chamber and measuring a sheet resistance of the exposed layer. In another embodiment, a method includes disposing the substrate in a process chamber, exposing the at least partially exposed conductive layer to a reactive pre-clean process that comprises an oxide reduction step, removing the substrate from the process chamber, contacting the conductive layer with one or more contact members, measuring a sheet resistance of the exposed conductive layer between the contact members, and comparing the measured resistance to a known value.
    Type: Grant
    Filed: July 18, 2001
    Date of Patent: June 17, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Haojiang Li, Peijun Ding, Suraj Rengarajan
  • Patent number: 6218301
    Abstract: A method of forming tungsten films on oxide layers is disclosed. The tungsten films are formed on the oxide layers by treating the oxide using a silane based gas mixture followed by the thermal decomposition of a W(CO)6 precursor. After the W(CO)6 precursor is thermally decomposed, additional layer of tungsten may be optionally formed thereon from the thermal decomposition of tungsten hexafluoride (WF6).
    Type: Grant
    Filed: July 31, 2000
    Date of Patent: April 17, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Hyungsuk Alexander Yoon, Michael X. Yang, Ming Xi
  • Patent number: 6043143
    Abstract: A method of improving contact resistance in a multi-layer heterostructure comprising the steps of providing a substrate, growing a crystalline material on the substrate, and doping close to an interface of the substrate and the crystalline material with n-silicon to provide continuity at the interface.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: March 28, 2000
    Assignee: Motorola, Inc.
    Inventor: Kumar Shiralagi
  • Patent number: 5872017
    Abstract: A method for preparing an epitaxial silicon wafer in a reactor is provided. The method comprises the steps of depositing an epitaxial layer on a surface of a silicon wafer contained in the reactor at an elevated temperature; purging the reactor with hydrogen after the epitaxial deposition; and cooling the reactor to an appropriate temperature which allows hydrogen passivation of the surface of the epitaxial layer. This prevents the formation of an oxide layer on the surface of the epitaxial layer for a sufficient amount of time to allow an accurate measurement of a carrier density profile of the epitaxial silicon wafer.
    Type: Grant
    Filed: January 24, 1997
    Date of Patent: February 16, 1999
    Assignee: SEH America, Inc.
    Inventors: Mark R. Boydston, Dena C. A. Mitchell
  • Patent number: 5624869
    Abstract: A method and a device directed to the same, for stabilizing cobalt di-silicide/single crystal silicon, amorphous silicon, polycrystalline silicon, germanide/crystalline germanium, polycrystalline germanium structures or other semiconductor material structures so that high temperature processing steps (above 750.degree. C.) do not degrade the structural quality of the cobalt di-silicide/silicon structure. The steps of the method include forming a di-silicide or germanide by either reacting cobalt with the substrate material and/or the codeposition of the di-silicide or germanide on a substrate, adding a selective element, either platinum or nitrogen, into the cobalt and forming the di-silicide or germanide by a standard annealing treatment. Alternatively, the cobalt di-silicide or cobalt germanide can be formed after the formation of the di-silicide or germanide respectively. As a result, the upper limit of the annealing temperature at which the di-silicide or germanide will structurally degrade is increased.
    Type: Grant
    Filed: April 13, 1994
    Date of Patent: April 29, 1997
    Assignee: International Business Machines Corporation
    Inventors: Paul D. Agnello, Cyril Cabral, Jr., Lawrence A. Clevenger, Matthew W. Copel, Francois M. d'Heurle, Qi-Zhong Hong
  • Patent number: 5624871
    Abstract: A method for producing an interconnect on a semiconductor device has silicon containing conductive surfaces and dielectric surfaces. The process includes forming separate regions of a blanket first refractory metal silicide on the silicon containing conductive surfaces, the first refractory metal silicide being composed of a first refractory metal and silicon from the surfaces, forming a blanket second refractory metal layer over the device, forming a blanket .alpha.-Si layer over the second refractory metal layer, forming a mask over the device to pattern an interconnect between the separate regions, then etching away the unwanted portions of the refractory metal layers and the .alpha.-Si layer, performing a rapid thermal annealing process on the device forming a low resistance refractory metal silicide between the .alpha.-Si layer and the second refractory metal layer, and then etching away the unwanted portions of the refractory metal layers that are not covered by the refractory metal silicide.
    Type: Grant
    Filed: August 19, 1996
    Date of Patent: April 29, 1997
    Assignee: Chartered Semiconductor Manufacturing Pte LTD
    Inventors: Yeow M. Teo, Kah S. Seah, Lap Chan, Che-Chia Wei
  • Patent number: 5620920
    Abstract: A process is disclosed for fabricating a CMOS structure with ESD protection. The outside transistors are covered with a protective oxide layer which is so masked as to cover the areas of the respective source and drain regions adjoining the field-oxide regions and the gate regions. The protective oxide layer is then subjected to a heat treatment, after which a siliciding process is carried out.
    Type: Grant
    Filed: March 11, 1996
    Date of Patent: April 15, 1997
    Assignee: Deutsche ITT Industries GmbH
    Inventor: Klaus Wilmsmeyer