Hillock Prevention Patents (Class 438/937)
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Patent number: 9041128Abstract: A Micro-Electro-Mechanical System (MEMS). The MEMS includes a lower chamber with a wiring layer and an upper chamber which is connected to the lower chamber. A MEMS beam is suspended between the upper chamber and the lower chamber. A lid structure encloses the upper chamber, which is devoid of structures that interfere with a MEMS beam. The lid structure has a surface that is conformal to a sacrificial material vented from the upper chamber.Type: GrantFiled: February 15, 2013Date of Patent: May 26, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: George A. Dunbar, III, Jeffrey C. Maling, William J. Murphy, Anthony K. Stamper
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Patent number: 8865497Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a lower wiring layer on a substrate. The method further includes forming a plurality of discrete wires from the lower wiring layer. The method further includes forming an electrode beam over the plurality of discrete wires. The at least one of the forming of the electrode beam and the plurality of discrete wires are formed with a layout which minimizes hillocks and triple points in subsequent silicon deposition.Type: GrantFiled: December 20, 2010Date of Patent: October 21, 2014Assignee: International Business Machines CorporationInventors: George A. Dunbar, III, Zhong-Xiang He, Jeffrey C. Maling, William J. Murphy, Anthony K. Stamper
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Patent number: 8030737Abstract: A semiconductor device including: a substrate; an insulating film formed over the substrate; a copper interconnect, having a plurality of hillocks formed over the surface thereof, buried in the insulating film; a first insulating interlayer formed over the insulating film and the copper interconnect; a second insulating interlayer formed over the first insulating interlayer; and an electroconductive layer formed over the second insulating interlayer, wherein the top surface of at least one hillock highest of all hillocks is brought into contact with the lower surface of the second insulating interlayer is provided.Type: GrantFiled: January 10, 2008Date of Patent: October 4, 2011Assignee: Renesas Electronics CorporationInventors: Daisuke Oshida, Toshiyuki Takewaki, Takuji Onuma, Koichi Ohto
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Patent number: 7745335Abstract: A method of fabricating an interconnect structure, comprising exposing an empty deposition chamber to a process that includes generating reactive species produced from a source gas in the presence of a plasma. The method further comprises terminating the plasma and then introducing a semiconductor substrate with a metal layer thereon into the chamber while the reactive species are present in the chamber.Type: GrantFiled: December 21, 2006Date of Patent: June 29, 2010Assignee: Texas Instruments IncorporatedInventors: Ju-Ai Ruan, Changming Jin, Sopa Chevacharoenkul, Satyavolu Papa Rao, Tae Seung Kim
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Patent number: 7727865Abstract: To provide a method of controlling a conductivity of a Ga2O3 system single crystal with which a conductive property of a ?-Ga2O3 system single crystal can be efficiently controlled. The light emitting element includes an n-type ?-Ga2O3 substrate, and an n-type ?-AlGaO3 cladding layer, an active layer, a p-type ?-AlGaO3 cladding layer and a p-type ?-Ga2O3 contact layer which are formed in order on the n-type ?-Ga2O3 substrate. A resistivity is controlled to fall within the range of 2.0×10?3 to 8×102 ?cm and a carrier concentration is controlled to fall within the range of 5.5×1015 to 2.0×1019/cm3 by changing a Si concentration within the range of 1×10?5 to 1 mol %.Type: GrantFiled: January 14, 2005Date of Patent: June 1, 2010Assignee: Waseda UniversityInventors: Noboru Ichinose, Kiyoshi Shimamura, Kazuo Aoki, Encarnacion Antonia Garcia Villora
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Patent number: 7531370Abstract: It is an object of the present invention to provides the light emitting diode having a light emitting part of an AlGaInP type, and having a current diffusion layer which includes In on a light emitting side of the light emitting part, so that the generation of hillocks is effectively inhibited and the brightness of the light emitting diode is increased.Type: GrantFiled: October 24, 2005Date of Patent: May 12, 2009Assignee: Sharp Kabushiki KaishaInventors: Kazuaki Sasaki, Junichi Nakamura
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Patent number: 7105451Abstract: A resist pattern formed so as to expose a wafer edge region is used to expose an edge surface region of an Si support substrate by dry etching. Next, a conductive layer constituted as wirings by subsequent patterning is formed by sputtering.Type: GrantFiled: January 22, 2004Date of Patent: September 12, 2006Assignee: Oki Electric Industry Co., Ltd.Inventor: Koichi Kishiro
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Patent number: 6893905Abstract: An aluminum-containing film having an oxygen content within the film. The aluminum-containing film is formed by introducing hydrogen gas and oxygen gas along with argon gas into a sputter deposition vacuum chamber during the sputter deposition of aluminum or aluminum alloys onto a semiconductor substrate. The aluminum-containing film so formed is hillock-free and has low resistivity, relatively low roughness compared to pure aluminum, good mechanical strength, and low residual stress.Type: GrantFiled: June 26, 2002Date of Patent: May 17, 2005Assignee: Micron Technology, Inc.Inventors: Kanwal K. Raina, David H. Wells
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Patent number: 6764951Abstract: The electromigration resistance of nitride capped Cu lines is significantly improved by treating the exposed planarized surface of inlaid Cu with a plasma containing NH3, depositing a silicon nitride capping layer at reduced temperatures, and then laser thermal annealing in N2 to densify the silicon nitride capping layer. The resulting silicon nitride capping layer also exhibits improved barrier resistance to Cu migration and improved etch stop properties. Embodiments include Cu dual damascene structures formed in dielectric material dielectric constant (k) less than about 3.9.Type: GrantFiled: February 28, 2002Date of Patent: July 20, 2004Assignee: Advanced Micro Devices, Inc.Inventor: Minh van Ngo
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Patent number: 6573127Abstract: A thin-film transistor includes a substrate and a gate including a double-layered structure-having first metal layer formed of a material exhibiting tensile stress and second metal layer formed of a metal exhibiting compressive stress, the first metal layer being wider than the second metal layer by about 1 to 4 &mgr;m. A method of making such a thin film transistor includes the steps of: depositing a first metal layer comprising a material exhibiting tensile stress on a substrate, depositing a second metal layer exhibiting compressive stress on the first metal layer; patterning the second metal layer and the first metal layer such that the first metal layer is wider than the second metal layer.Type: GrantFiled: October 25, 2001Date of Patent: June 3, 2003Assignee: LG Electronics Inc.Inventor: Hyun-Sik Seo
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Patent number: 6518179Abstract: A method of forming metal thin film of a memory device includes the steps of forming a metal layer on a semiconductor substrate, forming uniform grains on a surface of the metal layer, and forming a dielectric layer on the metal layer.Type: GrantFiled: March 10, 2000Date of Patent: February 11, 2003Assignee: LG Semicon Co., Ltd.Inventor: Jae-Hyun Joo
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Publication number: 20030022448Abstract: A gate insulating film is provided on a channel region. A gate electrode includes a lower part and an upper part. The lower part has a lower surface and sides, and the upper part has a lower surface. The lower surface of the lower part contacts the gate insulating film. The upper part is longer than the lower part in a lengthwise direction of a gate electrode. The first insulating film is interposed between the lower surface of the upper part of the gate electrode and a semiconductor substrate. The first insulating film surrounds at least the sides of the lower part of the gate electrode, which face drain and source regions, and having parts interposed between the lower surface of the upper part of the gate electrode and the semiconductor substrate and made thicker than the other parts.Type: ApplicationFiled: November 8, 2001Publication date: January 30, 2003Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Atsushi Azuma, Satoshi Matsuda
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Patent number: 6455939Abstract: An aluminum-containing film having an oxygen content within the film. The aluminum-containing film is formed by introducing hydrogen gas and oxygen gas along with argon gas into a sputter deposition vacuum chamber during the sputter deposition of aluminum or aluminum alloys onto a semiconductor substrate. The aluminum-containing film so formed is hillock-free and has low resistivity, relatively low roughness compared to pure aluminum, good mechanical strength, and low residual stress.Type: GrantFiled: May 15, 2000Date of Patent: September 24, 2002Assignee: Micron Technology, Inc.Inventors: Kanwal K. Raina, David H. Wells
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Patent number: 6268274Abstract: This invention provides an in situ low temperature, two step deposition HDP-CVD process separated by a cooldown period, for forming an inter-metal dielectric passivation layer for an integrated circuit structure. Said process mitigating metal line defects such as distortion or warping caused by excessive heat generated during the etching/deposition process.Type: GrantFiled: October 14, 1999Date of Patent: July 31, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Ying-Lang Wang, Chun-Ching Tsan, Jowei Dun, Hung-Ju Chien
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Patent number: 6222271Abstract: Aluminum containing films having an oxygen content within the films. The aluminum-containing film is formed by introducing hydrogen gas along with argon gas into a sputter deposition vacuum chamber during the sputter deposition of aluminum or aluminum alloys onto a semiconductor substrate. The aluminum-containing film so formed is hillock-free and has low resistivity, relatively low roughness compared to pure aluminum, good mechanical strength, and low residual stress.Type: GrantFiled: July 15, 1997Date of Patent: April 24, 2001Assignee: Micron Technology, Inc.Inventors: Kanwal K. Raina, David H. Wells
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Patent number: 6211075Abstract: A method for increasing electromigration resistance within the metal stack layer of Wolfram plugs by applying air exposure or plasma treatment to the top surface of the first layer of metal within the metal stack layer that is formed on top of metal plugs. The remainder of the process of the formation of the metal stack layer is not affected by the present invention.Type: GrantFiled: February 5, 1999Date of Patent: April 3, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chung-Shi Liu, Shau-Lin Shue, Chen-Hua Yu, Hung-Ju Chien
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Patent number: 6194783Abstract: Aluminum-containing films having an oxygen content within the films. The aluminum-containing film is formed by introducing hydrogen gas along with argon gas into a sputter deposition vacuum chamber during the sputter deposition of aluminum or aluminum alloys onto a semiconductor substrate. The aluminum-containing film so formed is hillock-free and has low resistivity, relatively low roughness compared to pure aluminum, good mechanical strength, and low residual stress.Type: GrantFiled: October 23, 1998Date of Patent: February 27, 2001Assignee: Micron Technology, Inc.Inventor: Kanwal K. Raina
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Patent number: 6107688Abstract: An aluminum-containing film having an oxygen content within the film. The aluminum-containing film is forced by introducing hydrogen gas and oxygen gas along with aragon gas into a sputter deposition vacuum chamber during the sputter deposition of aluminum or aluminum alloys onto a semiconductor substrate. The aluminum-containing film so formed is hillock-free and has low resistivity, relatively low roughness compared to pure aluminum, good mechanical strength, and low residual stress.Type: GrantFiled: April 12, 1999Date of Patent: August 22, 2000Assignee: Micron Technology, Inc.Inventors: Kanwal K. Raina, David H. Wells
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Patent number: 6071796Abstract: The invention provides a method of making silicon-on-glass substrates used in the manufacture of flat panel displays. A layer of amorphous silicon film is deposited on a glass substrate. The amorphous silicon is annealed by excimer laser annealing, transforming the amorphous silicon into polycrystalline silicon. The excimer laser annealing is carried out in a predominantly air ambient environment at atmospheric pressure and room temperature. The process requires no environmental chamber to house the substrate during excimer laser annealing. The process displaces the ambient air immediately surrounding the target region on the surface of the silicon film, where the laser beam strikes the silicon film, with inert gas. As a result, the ambient environment at the point of annealing on the substrate is depleted of oxygen and the oxygen content of the resultant polycrystalline silicon layer is kept below a predetermined level.Type: GrantFiled: October 30, 1998Date of Patent: June 6, 2000Assignee: Sharp Laboratories of America, Inc.Inventor: Tolis Voutsas
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Patent number: 6060386Abstract: The present invention is a method and apparatus for filling voids in a substrate with a desired material to form conductive components and/or other features on the substrate. In one embodiment in accordance with the principles of the present invention, a substrate with voids is covered with a first layer of material and then a second layer of material is formed on top of the first layer. The first layer is deformable at a deformation temperature, while the second layer has a higher yield strength than the first layer and is substantially non-deformable at the deformation temperature. The second layer, for example, may be a rigid and/or substantially incompressible layer that distributes a driving force to the first layer. The second layer is then pressed against the first layer at a temperature equal to or greater than the deformation temperature to drive portions of the first layer into the voids in the substrate.Type: GrantFiled: August 21, 1997Date of Patent: May 9, 2000Assignee: Micron Technology, Inc.Inventor: John H. Givens
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Patent number: 6057238Abstract: An aluminum-containing film having an oxygen content within the film. The aluminum-containing film is formed by introducing hydrogen gas and oxygen gas along with argon gas into a sputter deposition vacuum chamber during the sputter deposition of aluminum or aluminum alloys onto a semiconductor substrate. The aluminum-containing film so formed is hillock-free and has low resistivity, relatively low roughness compared to pure aluminum, good mechanical strength, and low residual stress.Type: GrantFiled: March 20, 1998Date of Patent: May 2, 2000Assignee: Micron Technology, Inc.Inventors: Kanwal K. Raina, David H. Wells
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Patent number: 6025892Abstract: An active matrix substrate of the present invention includes: a substrate; a plurality of first lines formed on the substrate to be parallel to each other; an insulating film covering the first lines; a plurality of second lines formed on the substrate extending to cross the first lines with the insulating film interposed therebetween; a plurality of switching elements provided near respective crossings of the first lines and the second lines; and a plurality of pixel electrodes which are arranged in a matrix on the insulating film and which are connected to the switching elements, respectively. The insulating film is partially removed prior to forming the second lines and the pixel electrodes so that the removed portions of the insulating film correspond to the gaps.Type: GrantFiled: April 17, 1997Date of Patent: February 15, 2000Assignee: Sharp Kabushiki KaishaInventors: Katsuhiro Kawai, Shinya Yamakawa, Masaya Okamoto, Mikio Katayama
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Patent number: 6010958Abstract: A method for improving the planarization of a dielectric layer in the fabrication of metallic interconnects wherein a rapid thermal processing operation is used in order to consolidate exposed surfaces of a dielectric layer after local planarization of the dielectric layer. This method avoids damage to the dielectric layer caused during a pre-metal etching operation, and consequently, prevents residual tungsten from becoming lodged in fissures during subsequent tungsten deposition to produce stringers which may cause short circuiting on coming in contact with metal wiring.Type: GrantFiled: August 6, 1997Date of Patent: January 4, 2000Assignee: United Microelectronics Corp.Inventors: Tung-Po Chen, Bing-Chang Wu, Hong-Tsz Pan
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Patent number: 5759912Abstract: An Al alloy interconnection layer is deposited on a silicon oxide layer, and a first carbon layer is formed on the Al alloy interconnection layer. Then, the first carbon layer and the Al alloy interconnection layer are patterned, thereby forming a first interconnection layer consisting of the Al alloy interconnection layer and the first carbon layer. Sequentially, a second carbon layer is formed on the first interconnection layer and the silicon oxide layer. The second carbon layer is entirely etched by the RIE method, thereby leaving the second carbon layer only on side surfaces of the first interconnection layer. A high temperature layer made of SiO.sub.2 is deposited on the second carbon layer, the first interconnection layer and the silicon oxide layer. Thereafter, the high temperature layer is etched back until the first carbon layer is exposed, thus being flattened. An interlayer insulating layer is deposited on the high temperature layer and the first interconnection layer.Type: GrantFiled: May 28, 1996Date of Patent: June 2, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Kazuya Mori, Kenichi Otsuka