Lattice Strain Control Or Utilization Patents (Class 438/938)
  • Patent number: 9034705
    Abstract: A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: May 19, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang, Chin-Cheng Chien, Tien-Wei Yu, Hsin-Kuo Hsu, Yu-Shu Lin, Szu-Hao Lai, Ming-Hua Chang
  • Patent number: 8932940
    Abstract: Embodiments of the invention provide a method for direct heteroepitaxial growth of vertical III-V semiconductor nanowires on a silicon substrate. The silicon substrate is etched to substantially completely remove native oxide. It is promptly placed in a reaction chamber. The substrate is heated and maintained at a growth temperature. Group III-V precursors are flowed for a growth time. Preferred embodiment vertical Group III-V nanowires on silicon have a core-shell structure, which provides a radial homojunction or heterojunction. A doped nanowire core is surrounded by a shell with complementary doping. Such can provide high optical absorption due to the long optical path in the axial direction of the vertical nanowires, while reducing considerably the distance over which carriers must diffuse before being collected in the radial direction. Alloy composition can also be varied. Radial and axial homojunctions and heterojunctions can be realized. Embodiments provide for flexible Group III-V nanowire structures.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: January 13, 2015
    Assignee: The Regents of the University of California
    Inventors: Deli Wang, Cesare Soci, Xinyu Bao, Wei Wei, Yi Jing, Ke Sun
  • Patent number: 8927963
    Abstract: A semiconductor memory cell, a semiconductor memory device, and a method for manufacturing the same are disclosed. The semiconductor memory cell may comprise: a substrate; a channel region on the substrate; a gate region above the channel region; a source region and a drain region on the substrate and at opposite sides of the channel region; and a buried layer, which is disposed between the substrate and the channel region and comprises a material having a forbidden band narrower than that of a material for the channel region material. The buried layer material has a forbidden band narrower than that of the channel region material, so that a hole barrier is formed in the buried layer. Due to the barrier, it is difficult for holes stored in the buried layer to leak out, resulting in an improved information holding duration of the memory cell utilizing the floating-body effect.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: January 6, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zongliang Huo, Ming Liu
  • Patent number: 8906789
    Abstract: The present disclosure relates to a method of forming an epitaxial layer through asymmetric cyclic deposition etch (CDE) epitaxy. An initial layer growth rate of one or more cycles of the CDE process are designed to enhance a crystalline quality of the epitaxial layer. A growth rate of the epitaxial material may be altered by adjusting a flow rate of one or more silicon-containing precursors within a processing chamber wherein the epitaxial growth takes place. An etch rate may also be altered by adjusting a temperature or partial pressure of one or more vapor etchants, or the temperature within the processing chamber. In some embodiments, an initial layer thickness that is greater than a critical thickness of the epitaxial material for strain relaxation is achieved with a low growth rate, followed by a high growth rate for the remainder of epitaxial growth. Other methods are also disclosed.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun Hsiung Tsai, Yi-Fang Pai, Chien-Chang Su, Tzu-Chun Tseng, Meng-Yueh Liu
  • Patent number: 8803194
    Abstract: Semiconductor structures are provided comprising a substrate and a epitaxial layer formed over the substrate, wherein the epitaxial layer comprises B; and one or more element selected from the group consisting of Zr, Hf and Al and has a thickness greater than 50 nm. Further, methods for integrating Group III nitrides onto a substrate comprising, forming an epitaxial buffer layer of a diboride of Zr, Hf, Al, or mixtures thereof, over a substrate; and forming a Group III nitride layer over the buffer layer, are provided which serve to thermally decouple the buffer layer from the underlying substrate, thereby greatly reducing the strain induced in the semiconductor structures upon fabrication and/or operation.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: August 12, 2014
    Assignee: Arizona Board of Regents, a body corporate of the State of Arizona Acting for and on Behalf of Arizona State University
    Inventors: John Kouvetakis, Radek Roucka
  • Patent number: 8796666
    Abstract: A device includes a substrate, insulation regions extending into the substrate, and a semiconductor fin higher than top surfaces of the insulation regions. The semiconductor fin has a first lattice constant. A semiconductor region includes sidewall portions on opposite sides of the semiconductor fin, and a top portion over the semiconductor fin. The semiconductor region has a second lattice constant different from the first lattice constant. A strain buffer layer is between and contacting the semiconductor fin and the semiconductor region. The strain buffer layer includes an oxide.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Tung Ying Lee, Chung-Hsien Chen, Chi-Wen Liu
  • Patent number: 8772097
    Abstract: In a method for fabricating a field effect transistor, a first source/drain region and a second source/drain region are formed in a substrate. A channel region is formed between the first source/drain region and the second source/drain region. A gate region is formed on the channel region. Micro-cavities are formed in the substrate at least below the channel region, and the micro-cavities are oxidized.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: July 8, 2014
    Assignee: Infineon Technologies AG
    Inventors: Luis-Felipe Giles, Frank Lau, Rainer Liebmann
  • Patent number: 8741726
    Abstract: Methods are disclosed of forming and removing a reacted layer on a surface of a recess to provide mechanisms for improving thickness uniformity of a semiconductor material formed in the recess. The improved thickness uniformity in turn improves the uniformity of device performance.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Te Lin, Chih-Lin Wang, Yi-Huang Wu, Tzong-Sheng Chang
  • Patent number: 8691644
    Abstract: A method of forming stressed-channel NMOS transistors and strained-channel PMOS transistors forms p-type source and drain regions before an n-type source and drain dopant is implanted and a stress memorization layer is formed, thereby reducing the stress imparted to the n-channel of the PMOS transistors. In addition, a non-conductive layer is formed after the p-type source and drain regions are formed, but before the n-type dopant is implanted. The non-conductive layer allows shallower n-type implants to be realized, and also serves as a buffer layer for the stress memorization layer.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: April 8, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Seung-Chul Song, Amitabh Jain, Deborah J. Riley
  • Patent number: 8647941
    Abstract: A method of forming a semiconductor device includes the following steps. A semiconductor substrate having a first strained silicon layer is provided. Then, an insulating region such as a shallow trench isolation (STI) is formed, where a depth of the insulating region is substantially larger than a depth of the first strained silicon layer. Subsequently, the first strained silicon layer is removed, and a second strained silicon layer is formed to substitute the first strained silicon layer.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: February 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • Patent number: 8642435
    Abstract: A method includes forming a gate stack over a semiconductor substrate, wherein the gate stack includes a gate dielectric and a gate electrode over the gate dielectric. A portion of the semiconductor substrate adjacent to the gate stack is recessed to form a recess. A semiconductor region is epitaxially grown in the recess. The semiconductor region is implanted with a p-type impurity or an n-type impurity. A dry treatment is performed on the semiconductor region.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: February 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Po-Chi Wu, Chang-Yin Chen, Zhe-Hao Zhang, Yi-Chen Huang
  • Patent number: 8643061
    Abstract: A semiconductor structure is provided. The structure includes an n-type field-effect-transistor (NFET) being formed directly on top of a strained silicon layer, and a p-type field-effect-transistor (PFET) being formed on top of the same stained silicon layer but via a layer of silicon-germanium (SiGe). The strained silicon layer may be formed on top of a layer of insulating material or a silicon-germanium layer with graded Ge content variation. Furthermore, the NFET and PFET are formed next to each other and are separated by a shallow trench isolation (STI) formed inside the strained silicon layer. Methods of forming the semiconductor structure are also provided.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Haizhou Yin, Dae-Gyu Park, Oleg Gluschenkov, Zhijiong Luo, Dominic Schepis, Jun Yuan
  • Patent number: 8633078
    Abstract: A semiconductor device is formed with a gate pattern formed on a substrate, and a recrystallized region having a stacking fault defect in the substrate at one side of the gate pattern. The semiconductor device can have a reduced leakage current and improved channel conductivity.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: January 21, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwan-Yong Lim, Chung-Geun Koh, Sang-Bom Kang, Ui-Hui Kwon, Hyun-Jung Lee, Tae-Ouk Kwon, Seok-Hoon Kim
  • Patent number: 8617945
    Abstract: A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm?2 to be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: December 31, 2013
    Assignee: Intel Corporation
    Inventors: Mantu K. Hudait, Mohamad A. Shaheen, Loren A. Chow, Peter G. Tolchinsky, Joel M. Fastenau, Dmitri Loubychev, Amy W. K. Liu
  • Patent number: 8603887
    Abstract: A method for depositing a silicon oxide layer on a substrate including a silicon region and a silicon-germanium region, including the steps of: forming a very thin silicon layer having a thickness ranging from 0.1 to 1 nm above silicon-germanium; and depositing a silicon oxide layer on the substrate.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: December 10, 2013
    Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS, International Business Machines Corporation
    Inventors: Didier Dutartre, Nicolas Breil, Yves Campidelli, Olivier Gourhant
  • Patent number: 8545627
    Abstract: Semiconductor structures are provided comprising a substrate and a epitaxial layer formed over the substrate, wherein the epitaxial layer comprises B; and one or more element selected from the group consisting of Zr, Hf and Al and has a thickness greater than 50 nm. Further, methods for integrating Group III nitrides onto a substrate comprising, forming an epitaxial buffer layer of a diboride of Zr, Hf, Al, or mixtures thereof, over a substrate; and forming a Group III nitride layer over the buffer layer, are provided which serve to thermally decouple the buffer layer from the underlying substrate, thereby greatly reducing the strain induced in the semiconductor structures upon fabrication and/or operation.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: October 1, 2013
    Assignee: Arizona Board of Regents
    Inventors: John Kouvetakis, Radek Roucka
  • Patent number: 8524012
    Abstract: A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface. The planar films and substrates are: (1) {1011} gallium nitride (GaN) grown on a {100} spinel substrate miscut in specific directions, (2) {1013} gallium nitride (GaN) grown on a {110} spinel substrate, (3) {1122} gallium nitride (GaN) grown on a {1100} sapphire substrate, and (4) {1013} gallium nitride (GaN) grown on a {1100} sapphire substrate.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: September 3, 2013
    Assignees: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: Troy J. Baker, Benjamin A. Haskell, Paul T. Fini, Steven P. DenBaars, James S. Speck, Shuji Nakamua
  • Patent number: 8486793
    Abstract: A semiconductor device including a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: July 16, 2013
    Assignee: Sony Corporation
    Inventor: Takuji Matsumoto
  • Patent number: 8466520
    Abstract: In a transistor, a strain-inducing semiconductor alloy, such as silicon/germanium, silicon/carbon and the like, may be positioned very close to the channel region by providing gradually shaped cavities which may then be filled with the strain-inducing semiconductor alloy. For this purpose, two or more “disposable” spacer elements of different etch behavior may be used in order to define different lateral offsets at different depths of the corresponding cavities. Consequently, enhanced uniformity and, thus, reduced transistor variability may be accomplished, even for sophisticated semiconductor devices.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: June 18, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stephan Kronholz, Vassilios Papageorgiou, Gunda Beernink
  • Patent number: 8394691
    Abstract: Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a gate structure overlying a region of semiconductor material, wherein the width of the gate structure is aligned with a <100> crystal direction of the semiconductor material. The method continues by forming recesses about the gate structure and forming a stress-inducing semiconductor material in the recesses.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: March 12, 2013
    Assignee: Globalfoundries, Inc.
    Inventors: Bin Yang, Man Fai Ng
  • Patent number: 8361893
    Abstract: An undoped semiconductor substrate is doped by applying stress at a side of the undoped semiconductor substrate to release self interstitials in the substrate and implanting chalcogen atoms into the side of the substrate. The substrate is annealed to form a first semiconductor region containing the chalcogen atoms and a second semiconductor region devoid of the chalcogen atoms. The first semiconductor region has a doping concentration higher than the doping concentration of the second semiconductor region. The indiffusion of chalcogen atoms into a semiconductor material in the presence of self interstitials can also be used to form field stop regions in power semiconductor devices.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: January 29, 2013
    Assignee: Infineon Technologies AG
    Inventors: Gerhard Schmidt, Hans-Joachim Schulze, Bernd Kolbesen
  • Patent number: 8343780
    Abstract: The invention relates to a method for straining or deforming a pattern or a thin layer (24), starting from an initial component comprising the said thin layer and a prestressed layer (20), this method comprising: an etching step of the prestressed layer, perpendicular to its surface.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: January 1, 2013
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Jean-Charles Barbe, Thomas Ernst
  • Patent number: 8343872
    Abstract: The present disclosure provides a method of fabricating that includes providing a semiconductor substrate; forming a gate structure on the substrate; performing an implantation process to form a doped region in the substrate; forming spacers on sidewalls of the gate structure; performing an first etching to form a recess in the substrate, where the first etching removes a portion of the doped region; performing a second etching to expand the recess in the substrate, where the second etching includes an etchant and a catalyst that enhances an etching rate at a remaining portion of the doped region; and filling the recess with a semiconductor material.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: January 1, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsueh-Chang Sung, Hsien-Hsin Lin, Kuan-Yu Chen, Chien-Chang Su, Tsz-Mei Kwok, Yi-Fang Pai
  • Patent number: 8304276
    Abstract: An apparatus comprising a microelectromechanical system. The microelectromechanical system includes a crystalline structural element having dislocations therein. For at least about 60 percent of adjacent pairs of the dislocations, direction vectors of the dislocations form acute angles of less than about 45 degrees.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: November 6, 2012
    Assignee: Alcatel Lucent
    Inventor: George Patrick Watson
  • Patent number: 8293609
    Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: October 23, 2012
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Rohit Pal, Frank Bin Yang, Michael J. Hargrove
  • Patent number: 8274071
    Abstract: A semiconductor structure includes a semiconductor substrate having a first lattice constant; a gate dielectric on the semiconductor substrate; a gate electrode on the semiconductor substrate; and a stressor having at least a portion in the semiconductor substrate and adjacent the gate electrode. The stressor has a tilted sidewall on a side adjacent the gate electrode. The stressor includes a first stressor layer having a second lattice constant substantially different from the first lattice constant; and a second stressor layer on the first stressor layer, wherein the second stressor has a third lattice constant substantially different from the first and the second lattice constants.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: September 25, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hua Yu, Mong-Song Liang, Tze-Liang Lee, Jr.-Hung Li
  • Patent number: 8232581
    Abstract: Manufacturing an III-V engineered substrate involves providing a base substrate comprising an upper layer made of a first III-V compound with a <110> or a <111> crystal orientation, forming an intermediate layer comprising at least a buffer layer of a second III-V compound, wherein the intermediate layer is overlying and in contact with the upper layer of the base substrate. Then a pseudomorphic passivation layer made of a group IV semiconductor material is grown so as to be overlying and in contact with the intermediate layer. This can enable an unpinned interface. The substrate surface can be smoother, implying fewer problems from surface stress. It can be used in electronic devices such as metal-oxide-semiconductor field effect transistors (MOSFETs), high electron mobility transistors (HEMTs), tunneling field effect transistors (TFETs), and optoelectronic devices.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: July 31, 2012
    Assignee: IMEC
    Inventors: Geoffrey Pourtois, Clement Merckling, Guy Brammertz, Matty Caymax
  • Patent number: 8232171
    Abstract: A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Sebastian Ulrich Engelmann, Nicholas C. M. Fuller, Eric Andrew Joseph, Isaac Lauer, Ryan M. Martin, James Vichiconti, Ying Zhang
  • Patent number: 8232191
    Abstract: A method of manufacturing a semiconductor device including forming a gate insulating film and a gate electrode over a Si substrate; forming a recess in the Si substrate at both sides of the gate electrode; forming a first Si layer including Ge in the recess; forming an interlayer over the first Si layer; forming a second Si layer including Ge over the interlayer; wherein the interlayer is composed of Si or Si including Ge, and a Ge concentration of the interlayer is less than a Ge concentration of the first Si layer and a Ge concentration of the second Si layer.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: July 31, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masahiro Fukuda, Yosuke Shimamune
  • Patent number: 8227791
    Abstract: A strain balanced active-region design is disclosed for optoelectronic devices such as light-emitting diodes (LEDs) and laser diodes (LDs) for better device performance. Lying below the active-region, a lattice-constant tailored strain-balancing layer provides lattice template for the active-region, enabling balanced strain within the active-region for the purposes of 1) growing thick, multiple-layer active-region with reduced defects, or 2) engineering polarization fields within the active-region for enhanced performance. The strain-balancing layer in general enlarges active-region design and growth windows. In some embodiments of the present invention, the strain-balancing layer is made of quaternary InxAlyGa1-x-yN (0?x?1, 0?y?1, x+y?1), whose lattice-constant is tailored to exert opposite strains in adjoining layers within the active-region. A relaxation-enhancement layer can be provided beneath the strain-balancing layer for enhancing the relaxation of the strain-balancing layer.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: July 24, 2012
    Assignee: Invenlux Limited
    Inventor: Chunhui Yan
  • Patent number: 8207040
    Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode on a semiconductor substrate and a sidewall spacer on the gate electrode. Then, a portion of the semiconductor substrate at both sides of the sidewall spacer is partially etched to form a trench. A SiGe mixed crystal layer is formed in the trench. A silicon layer is formed on the SiGe mixed crystal layer. A portion of the silicon layer is partially etched using an etching solution having different etching rates in accordance with a crystal direction of a face of the silicon layer to form a capping layer including a silicon facet having an (111) inclined face.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: June 26, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoi-Sung Chung, Dong-Suk Shin, Dong-Hyuk Kim, Jung-Shik Heo, Myung-Sun Kim
  • Patent number: 8207523
    Abstract: A method of fabrication of a metal oxide semiconductor field effect transistor is disclosed. At first, a substrate on which a gate structure is formed is provided. Afterward, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a plurality of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: June 26, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Chen-Hua Tsai, Bang-Chiang Lan, Yu-Hsin Lin, Yi-Cheng Liu, Cheng-Tzung Tsai
  • Patent number: 8187957
    Abstract: A field-effect transistor that increases the operation speeds of complementary field-effect transistors. Each of an nMOSFET and a pMODFET has a Ge channel and source and drain regions formed of an NiGe layer. The height of Schottky barriers formed at a junction between a channel region and the source region of the nMOSFET and at a junction between the channel region and the drain region of the nMOSFET is changed by very thin high-concentration segregation layers formed by making As atoms, Sb atoms, S atoms or the like segregate at the time of forming the NiGe layer. As a result, Schottky barrier height suitable for the nMOSFET and the pMODFET can be obtained, this being capable of realizing high-speed CMOSFETS.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: May 29, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Keiji Ikeda
  • Patent number: 8128756
    Abstract: A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface. The planar films and substrates are: (1) {10 11} gallium nitride (GaN) grown on a {100} spinel substrate miscut in specific directions, (2) {10 13 } gallium nitride (GaN) grown on a {110} spinel substrate, (3) {11 22} gallium nitride (GaN) grown on a {1 100} sapphire substrate, and (4) {10 13} gallium nitride (GaN) grown on a {1 100} sapphire substrate.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: March 6, 2012
    Assignees: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: Troy J. Baker, Benjamin A. Haskell, Paul T. Fini, Steven P. DenBaars, James S. Speck, Shuji Nakamua
  • Patent number: 8124473
    Abstract: A strain enhanced semiconductor device and methods for its fabrication are provided. One method comprises embedding a strain inducing semiconductor material in the source and drain regions of the device to induce a strain in the device channel. Thin metal silicide contacts are formed to the source and drain regions so as not to relieve the induced strain. A layer of conductive material is selectively deposited in contact with the thin metal silicide contacts, and metallized contacts are formed to the conductive material.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: February 28, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James N. Pan, Sey-Ping Sun, Andrew M. Waite
  • Patent number: 8110478
    Abstract: If the size of a single crystal silicon layer attached is not appropriate, even when a large glass substrate is used, the number of panels to be obtained cannot be maximized. Therefore, in the present invention, a substantially quadrangular single crystal semiconductor substrate is formed from a substantially circular single crystal semiconductor wafer, and a damaged layer is formed by irradiation with an ion beam into the single crystal semiconductor substrate. A plurality of the single crystal semiconductor substrates are arranged so as to be separated from each other over one surface of a supporting substrate. By thermal treatment, a crack is generated in the damaged layer and the single crystal semiconductor substrate is separated while a single semiconductor layer is left over the supporting substrate. After that, one or a plurality of display panels is manufactured from the single crystal semiconductor layer bonded to the supporting substrate.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: February 7, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideto Ohnuma, Jun Koyama
  • Patent number: 8063413
    Abstract: A semiconductor structure is provided. The semiconductor structure includes one or more III-IV material-based semiconductor layers. A tensile-strained Ge layer is formed on the one or more a III-IV material-based semiconductor layers. The tensile-strained Ge layer is produced through lattice-mismatched heteroepitaxy on the one or more a III-IV material-based semiconductor layers.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: November 22, 2011
    Assignee: Massachusetts Institute of Technology
    Inventors: Yu Bai, Minjoo L. Lee, Eugene A. Fitzgerald
  • Patent number: 8049280
    Abstract: A semiconductor device according to one embodiment includes: a gate electrode formed on a semiconductor substrate via a gate insulating film; Si:C layers formed on the semiconductor substrate in sides of the gate electrode; p-type source/drain regions formed in sides of the gate electrode in the semiconductor substrate, and a part of the p-type source/drain regions being formed in the Si:C layers; and silicide layers formed on the Si:C layers.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: November 1, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akira Hokazono
  • Patent number: 7981750
    Abstract: In one aspect, a method of fabricating a semiconductor device is provided. The method includes forming at least one capping layer over epitaxial source/drain regions of a PMOS device, forming a stress memorization (SM) layer over the PMOS device including the at least one capping layer and over an adjacent NMOS device, and treating the SM layer formed over the NMOS and PMOS devices to induce tensile stress in a channel region of the NMOS device.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: July 19, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hion-suck Baik, Jong-bong Park, Jung-yun Won, Hwa-sung Rhee, Byung-seo Kim, Ho Lee, Myung-sun Kim, Ji-hye Yi
  • Patent number: 7968911
    Abstract: A crystalline wafer comprising of a support substrate, a first layer and an interface layer. The first layer is of a first material in a relaxed state having a lattice parameter that is substantially equal to the nominal lattice parameter of the first material. The interface layer is in an at least partially molten state disposed between the support substrate and the first layer. The first material is preferably silicon germanium, and the interface layer includes germanium in a higher concentration than that of first material.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: June 28, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventor: George K Celler
  • Patent number: 7923785
    Abstract: According to one exemplary embodiment, a FET which is situated over a substrate, comprises a channel situated in the substrate. The FET further comprises a first gate dielectric situated over the channel, where the first gate dielectric has a first coefficient of thermal expansion. The FET further comprises a first gate electrode situated over the first gate dielectric, where the first gate electrode has a second coefficient of thermal expansion, and where the second coefficient of thermal expansion is different than the first coefficient of thermal expansion so as to cause an increase in carrier mobility in the FET. The second coefficient of thermal expansion may be greater that the first coefficient of thermal expansion, for example. The increase in carrier mobility may be caused by, for example, a tensile strain created in the channel.
    Type: Grant
    Filed: August 18, 2003
    Date of Patent: April 12, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Qi Xiang, Boon-Yong Ang, Jung-Suk Goo
  • Patent number: 7902008
    Abstract: A method for fabricating a stressed MOS device in and on a semiconductor substrate is provided. The method comprises the steps of forming a gate electrode overlying the semiconductor substrate and etching a first trench and a second trench in the semiconductor substrate, the first trench and the second trench formed in alignment with the gate electrode. A stress inducing material is selectively grown in the first trench and in the second trench and conductivity determining impurity ions are implanted into the stress inducing material to form a source region in the first trench and a drain region in the second trench. To preserve the stress induced in the substrate, a layer of mechanically hard material is deposited on the stress inducing material after the step of ion implanting.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: March 8, 2011
    Assignee: GlobalFoundries Inc.
    Inventors: Igor Peidous, Mario M. Pelella
  • Patent number: 7892905
    Abstract: A process for forming a strained channel region for a MOSFET device via formation of adjacent silicon-germanium source/drain regions, has been developed. The process features either blanket deposition of a silicon-germanium layer, or selective growth of a silicon-germanium layer on exposed portions of a source/drain extension region. A laser anneal procedure results in formation of a silicon-germanium source/drain region via consumption of a bottom portion of the silicon-germanium layer and a top portion of the underlying source/drain region. Optimization of the formation of the silicon-germanium source/drain region via laser annealing can be achieved via a pre-amorphization implantation (PAI) procedure applied to exposed portions of the source/drain region prior to deposition of the silicon-germanium layer. Un-reacted top portions of the silicon-germanium layer are selectively removed after the laser anneal procedure.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: February 22, 2011
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Kuang Kian Ong, Kin Leong Pey, King Jien Chui, Ganesh Samudra, Yee Chia Yeo, Yung Fu Chong
  • Patent number: 7867860
    Abstract: A strained channel transistor is provided. The strained channel transistor comprises a substrate formed of a first material. A source region comprised of a second material is formed in a first recess in the substrate, and a drain region comprised of the second material is formed in a second recess in the substrate. A strained channel region formed of the first material is intermediate the source and drain region. A gate stack formed over the channel region includes a gate electrode overlying a gate dielectric. A gate spacer formed along a sidewall of the gate electrode overlies a portion of at least one of said source region and said drain region. A cap layer may be formed over the second material, and the source and drain regions may be silicided.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: January 11, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chun Huang, Yen-Ping Wang, Chih-Hsin Ko
  • Patent number: 7868317
    Abstract: A semiconductor structure includes a semiconductor substrate having a first lattice constant; a gate dielectric on the semiconductor substrate; a gate electrode on the semiconductor substrate; and a stressor having at least a portion in the semiconductor substrate and adjacent the gate electrode. The stressor has a tilted sidewall on a side adjacent the gate electrode. The stressor includes a first stressor layer having a second lattice constant substantially different from the first lattice constant; and a second stressor layer on the first stressor layer, wherein the second stressor has a third lattice constant substantially different from the first and the second lattice constants.
    Type: Grant
    Filed: May 18, 2009
    Date of Patent: January 11, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hua Yu, Mong-Song Liang, Tze-Liang Lee, Jr-Hung Li
  • Patent number: 7838354
    Abstract: By performing a planarization process, for instance based on a planarization layer, prior to forming a resist mask for selectively removing a portion of a stressed contact etch stop layer, the strain-inducing mechanism of a subsequently deposited further contact etch stop layer may be significantly improved.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: November 23, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kai Frohberg, Sven Mueller, Christoph Schwan
  • Patent number: 7838934
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed, in which an insulating layer may be formed in a strained silicon layer under source/drain regions to substantially overcome conventional problems resulting from a channel decrease in the semiconductor device.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: November 23, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Myung Jin Jung
  • Patent number: 7812374
    Abstract: A semiconductor device includes a first MIS transistor on a first active region of a semiconductor substrate, the first MIS transistor including: a first gate insulating film provided on the first active region; a first gate electrode provided on the first gate insulating film; a first stressor insulating film provided on an upper face and side faces facing in a gate length direction of the first gate electrode such that first stress acts on a channel of the first MIS transistor in the gate length direction; and a first base insulating film provided on side faces of the first gate electrode facing in a gate width direction, wherein the side faces of the first gate electrode facing in the gate width direction are not covered with the first stressor insulating film.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: October 12, 2010
    Assignee: Panasonic Corporation
    Inventors: Nobuyuki Tamura, Ken Suzuki, Katsuhiro Ootani
  • Patent number: 7791144
    Abstract: The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: September 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Ricardo A. Donaton, William K. Henson, Kern Rim
  • Patent number: 7768041
    Abstract: A field effect transistor (“FET”) is provided which includes an active semiconductor region including a channel region, a first source-drain region and a second source-drain region. A major surface of the active semiconductor region is divided into a mutually exclusive first portion and a second portion. A first liner applies a first stress to the first portion of the major surface, and a second liner applies a second stress to the second portion of the major surface. The first and second stresses are each selected from high tensile stress, high compressive stress and neutral stress, with the first stress being different from the second stress. The liners can help to differentiate a first operating current conducted by the first portion of the FET under one operating condition and a second operating current that is conducted by the second portion of the FET under a different operating condition.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: August 3, 2010
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, David M. Onsongo