Laser Ablative Material Removal Patents (Class 438/940)
  • Patent number: 7625810
    Abstract: A method of processing a wafer having a device area where a plurality of devices are formed on the front surface and an extra area surrounding the device area and comprising electrodes which are formed in the device area, comprising: a reinforcement forming step for removing an area, which corresponds to the device area, in the back surface of the wafer to reduce the thickness of the device area to a predetermined value and keeping an area, which corresponds to the extra area, in the back surface of the wafer to form an annular reinforcement; and a via-hole forming step for forming a via-hole in the electrodes of the wafer which has been subjected to the reinforcement forming step.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: December 1, 2009
    Assignee: Disco Corporation
    Inventors: Keiichi Kajiyama, Koichi Kondo, Yasuomi Kaneuchi
  • Patent number: 7615499
    Abstract: A method is presented in which a layer which is to be oxidized is processed, in a single-substrate process. The process temperature during the processing is recorded directly at the substrate or at a holding device for the substrate. The method includes introducing a substrate, which bears a layer to be oxidized uncovered in an edge region in a layer stack, into a heating device, passing an oxidation gas onto the substrate, heating the substrate to a process temperature, which is recorded during the processing via a temperature of a holding device which holds the substrate, and controlling the substrate temperature to a desired temperature or temperature curve during the processing.
    Type: Grant
    Filed: July 26, 2003
    Date of Patent: November 10, 2009
    Assignee: Infineon Technologies AG
    Inventors: Hin-Yiu Chung, Thomas Gutt
  • Patent number: 7582848
    Abstract: An energy-efficient method and system for processing target material such as microstructures in a microscopic region without causing undesirable changes in electrical and/or physical characteristics of material surrounding the target material is provided. The system includes a controller for generating a processing control signal and a signal generator for generating a modulated drive waveform based on the processing control signal. The waveform has a sub-nanosecond rise time. The system also includes a gain-switched, pulsed semiconductor seed laser for generating a laser pulse train at a repetition rate. The drive waveform pumps the laser so that each pulse of the pulse train has a predetermined shape. Further, the system includes a laser amplifier for optically amplifying the pulse train to obtain an amplified pulse train without significantly changing the predetermined shape of the pulses.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: September 1, 2009
    Assignee: GSI Group Corp
    Inventor: Donald V. Smart
  • Patent number: 7521383
    Abstract: A first layer (an insulating layer), a second layer (a metal layer), and a third layer (an insulating layer) are formed over a substrate. Then, a fourth layer including a semiconductor element is formed over the third layer. After applying an organic resin film covering the fourth layer, laser light is irradiated to sections of a rear surface side of the substrate. By irradiating the second layer with laser light, the state of being covered with the organic resin film can be maintained at the same time as forming a space under the organic resin film by ablating (alternatively, evaporating or breaking down) an irradiated region of the second layer, to cause a lift in the film in a periphery thereof.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: April 21, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masafumi Morisue, Ryosuke Watanabe, Junya Maruyama, Daiki Yamada
  • Patent number: 7482551
    Abstract: A set (50) of laser pulses (52) is employed to sever a conductive link (22) in a memory or other IC chip. The duration of the set (50) is preferably shorter than 1,000 ns; and the pulse width of each laser pulse (52) within the set (50) is preferably within a range of about 0.1 ps to 30 ns. The set (50) can be treated as a single “pulse” by conventional laser positioning systems (62) to perform on-the-fly link removal without stopping whenever the laser system (60) fires a set (50) of laser pulses (52) at each link (22). Conventional IR wavelengths or their harmonics can be employed.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: January 27, 2009
    Assignee: Electro Scientific Industries, Inc.
    Inventors: Yunlong Sun, Edward J. Swenson, Richard S. Harris
  • Patent number: 7465977
    Abstract: There is described a method for producing a packaged integrated circuit. The method comprises a first step of building an integrated circuit having a micro-structure suspended above a micro-cavity, and having a heating element on the micro-structure capable of heating itself and its immediate surroundings. A layer of protective material is then deposited on said micro-structure such that at least a top surface of the micro-structure and an opening of the micro-cavity is covered, wherein the protective material is in a solid state at room temperature and can protect the micro-structure during silicon wafer dicing procedures and subsequent packaging. The integrated circuit is packaged and an electric current is passed through the heating element such that a portion of the protective material is removed and an unobstructed volume is provided above and below the micro-structure.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: December 16, 2008
    Assignee: Microbridge Technologies Inc.
    Inventors: Leslie M. Landsberger, Oleg Grudin
  • Patent number: 7449347
    Abstract: A repairing method of thin film transistor array is provided. The repairing method of thin film transistor array can remove a residue between pixel electrodes so as to prevent the residue from electrically connecting pixel electrodes adjacent to each other. The repairing method of thin film transistor array can also be provided to remove a portion of the pixel electrodes above a particle or a defect, which may cause leakage of a storage capacity. The parameters of repairing method of the thin film transistor array precisely controlled and the yield of the thin film transistor array can be effectively improved.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: November 11, 2008
    Assignee: AU Optronics Corporation
    Inventor: Han-Chung Lai
  • Patent number: 7442629
    Abstract: The present invention generally provides semiconductor substrates having submicron-sized surface features generated by irradiating the surface with ultra short laser pulses. In one aspect, a method of processing a semiconductor substrate is disclosed that includes placing at least a portion of a surface of the substrate in contact with a fluid, and exposing that surface portion to one or more femtosecond pulses so as to modify the topography of that portion. The modification can include, e.g., generating a plurality of submicron-sized spikes in an upper layer of the surface.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: October 28, 2008
    Assignee: President & Fellows of Harvard College
    Inventors: Eric Mazur, Mengyan Shen
  • Patent number: 7442644
    Abstract: To remove the disparate substrate from nitride semiconductor layer grown over the disparate substrate, that is made of a material different from nitride semiconductor, by irradiating the disparate substrate with laser beam having a wavelength shorter than the band gap wavelength of the nitride semiconductor layer, while supplying an acidic or alkaline etching solution to the interface between the disparate substrate and the nitride semiconductor layer.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: October 28, 2008
    Assignee: Nichia Corporation
    Inventor: Yoichi Nogami
  • Patent number: 7419912
    Abstract: Light extraction features are provided for a light emitting device having a substrate and a semiconductor light emitting element on the substrate by shaping a surface of a layer of semiconductor material utilizing a laser to define three dimensional patterns in the layer of semiconductor material. The layer of semiconductor material may be the substrate. In particular embodiments of the present invention, the surface of the layer of semiconductor material is shaped by applying laser light to the layer of semiconductor material at an energy sufficient to remove material from the layer of semiconductor material. The laser light may also by applied in a blanket manner at a level below the ablation threshold. The application of laser light to the layer of semiconductor material may be followed by etching the substrate. The layer of semiconductor material may be anisotropically etched. A mask could also be patterned utilizing laser light and the layer of semiconductor material etched using the mask.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: September 2, 2008
    Assignee: Cree, Inc.
    Inventor: Matthew Donofrio
  • Patent number: 7396706
    Abstract: A specially shaped laser pulse energy profile characterized by different laser wavelengths at different times of the profile provides reduced, controlled jitter to enable semiconductor device micromachining that achieves high quality processing and a smaller possible spot size.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: July 8, 2008
    Assignee: Electro Scientific Industries, Inc.
    Inventors: Yunlong Sun, Richard Harris, William J. Jordens, Lei Sun
  • Patent number: 7348261
    Abstract: A chip module having a chip with a flexible multilayer redistribution thin film attached thereto for connection to a substrate. The thin film acts as both a redistribution medium with multiple layers of redistribution metallurgy for chip power and signals and as a compliant medium to relieve stresses caused by thermal expansion mismatch between chip and substrate. Modules comprising chip and thin film may be fabricated at the chip or wafer level. The upper surface of the thin film has an array of pads matching the array of pads on the chip or wafer while the lower surface has pads matching those of the substrate. The multilayer thin film is first formed on a temporary substrate and then the chip is attached to the thin film before release from the temporary substrate. After release, the module is ready for mounting to the second level packaging substrate, such as a chip carrier or PCB. Where the multilayer thin film is formed directly on a wafer, the wafer is then diced to form the module.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: March 25, 2008
    Assignee: International Business Machines Corporation
    Inventors: David Vincent Caletka, Seungbae Park, Sanjeev Balwant Sathe
  • Patent number: 7338843
    Abstract: A method for producing an electronic component, especially a memory chip, using a laser-induced correction to equalize an integrated circuit by means of at least one laser via in a layer at least partially covering the circuit. The component comprises a rewiring of the contact pads. The inventive method comprises the following steps: each laser via is closed by means of a separate covering layer which is to be applied locally; a rewiring extending between the local covering layers is created; the local covering layers are removed; and the laser-induced correction is carried out by means of the open laser vias.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: March 4, 2008
    Assignee: Infineon Technologies AG
    Inventors: Harry Hedler, Roland Irsigler, Barbara Vasquez
  • Patent number: 7316936
    Abstract: A decapsulation apparatus 100 has a laser 8 that removes plastic encapsulant from a device 24. Chamber 20 is sealed. Exhaust port 9 removes debris and fumes. The device 24 is positioned and scanned using an X, Y table 2. A hinged end 4 rotates the device to an acute angle of incidence with respect to a laser 8. Endpoint detector 10 senses the exposed integrated circuit and moves or shuts down the laser 8.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: January 8, 2008
    Assignee: Intersil Americans Inc.
    Inventor: Robert K. Lowry
  • Publication number: 20070293057
    Abstract: A new technique and Method of Direct Coulomb Explosion in Laser Ablation of Semiconductor Structures in semiconductor materials is disclosed. The Method of Direct Coulomb Explosion in Laser Ablation of Semiconductor Structures provides activation of the “Coulomb explosion” mechanism in a manner which does not invoke or require the conventional avalanche photoionization mechanism, but rather utilizes direct interband absorption to generate the Coulomb explosion threshold charge densities. This approach minimizes the laser intensity necessary for material removal and provides optimal machining quality. The technique generally comprises use of a femtosecond pulsed laser to rapidly evacuate electrons from a near surface region of a semiconductor or dielectric structure, and wherein the wavelength of the laser beam is chosen such that interband optical absorption dominates the carrier production throughout the laser pulse.
    Type: Application
    Filed: June 20, 2007
    Publication date: December 20, 2007
    Inventor: William W. Chism
  • Patent number: 7285428
    Abstract: In a production method of an electron source wherein a plurality of electron-emitting devices are connected by and driven by matrix wirings, the upper wiring of the matrix wiring is partially removed at a short circuit region at a cross portion between the matrix wirings, thereby removing the short circuit and effectively repairing an electrical connecting relation of the matrix wirings.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: October 23, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshimi Uda, Kazuya Ishiwata
  • Patent number: 7241669
    Abstract: A method of forming a scribe line having a sharp snap line entails directing a UV laser beam along a ceramic or ceramic-like substrate such that a portion of the thickness of the substrate is removed. The UV laser beam forms a scribe line in the substrate without appreciable substrate melting so that a clearly defined snap line forms a region of high stress concentration extending into the thickness of the substrate. Consequently, multiple depthwise cracks propagate into the thickness of the substrate in the region of high stress concentration in response to a breakage force applied to either side of the scribe line to effect clean fracture of the substrate into separate circuit components. The formation of this region facilitates higher precision fracture of the substrate while maintaining the integrity of the interior structure of each component during and after application of the breakage force.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: July 10, 2007
    Assignee: Electro Scientific Industries, Inc.
    Inventors: Edward J. Swenson, Yunlong Sun, Manoj Kumar Sammi, Jay Christopher Johnson, Doug Garcia, Rupendra M. Anklekar
  • Patent number: 7227172
    Abstract: In a Group-III-element nitride semiconductor device including a Group-III-element nitride crystal layer stacked on a Group-III-element nitride crystal substrate, the substrate is produced by allowing nitrogen of nitrogen-containing gas and a Group III element to react with each other to crystallize in a melt (a flux) containing at least one of alkali metal and alkaline-earth metal, and a thin film layer is formed on the substrate and the thin film has a lower diffusion coefficient than that of the substrate with respect to impurities contained in the substrate. The present invention provides a semiconductor device in which alkali metal is prevented from diffusing.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: June 5, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuo Kitaoka, Hisashi Minemoto, Isao Kidoguchi, Kazuyoshi Tsukamoto
  • Patent number: 7135405
    Abstract: Embodiments of methods, apparatuses, devices, and/or systems for forming an interconnect are described.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: November 14, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jian-Gang Weng, Ravi Prasad, Cary G. Addington, Peter S. Nyholm
  • Patent number: 7122489
    Abstract: A patterned, multi-layered thin film structure is patterned using ultra-fast lasers and absorption spectroscopy without damaging underlying layers of the layered structure. The structure is made by selecting ablatable layers based on their thermal, strength and absorption spectra and by using an ultra-fast laser programmed with the appropriate wavelength (?), pulse width (?), spectral width (??), spot size, bite size and fluence. The end structure may have features (such as vias, insulating areas, or inkjet printed areas) patterned in the last (top) layer applied or at deeper layers within the layered structure, and can be used as components of organic light emitting didoes (OLEDs) and organic thin film transistors (OTFTs). The method of the present invention includes determining the product's specifications, providing a substrate, selecting a layer, applying the layer, patterning the layer and determining if more layers need to be added to the multi-layered thin film structure.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: October 17, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Chen-Hsiung Cheng, Xinbing Liu, Atsushi Sogami, Kazuo Nishimura
  • Patent number: 7115514
    Abstract: The present invention relates to methods and systems for ablation based material removal configuration for use in semiconductor manufacturing that includes the steps of generating an initial wavelength-swept-with-time optical pulse in an optical pulse generator, amplifying the initial pulse, compressing the amplified pulse to a duration of less than about 10 picoseconds and applying the compressed optical pulse to the wafer surface, to remove material from, e.g., wafer surface.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: October 3, 2006
    Assignee: Raydiance, Inc.
    Inventor: Richard Stoltz
  • Patent number: 7115503
    Abstract: A method and apparatus for processing a thin metal layer on a substrate to control the grain size, grain shape, and grain boundary location and orientation in the metal layer by irradiating the metal layer with a first excimer laser pulse having an intensity pattern defined by a mask to have shadow regions and beamlets. Each region of the metal layer overlapped by a beamlet is melted throughout its entire thickness, and each region of the metal layer overlapped by a shadow region remains at least partially unmelted. Each at least partially unmelted region adjoins adjacent melted regions. After irradiation by the first excimer laser pulse, the melted regions of the metal layer are pemitted to resolidify. During resolidification, the at least partially unmelted regions seed growth of grains in adjoining melted regions to produce larger grains.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: October 3, 2006
    Assignee: The Trustees of Columbia University in the City of New York
    Inventor: James S. Im
  • Patent number: 6998220
    Abstract: A method for manufacturing thin-film chip resistors, in which method a resistor layer (14) and a contact layer (15, 16) are applied onto the upper surface of a substrate (10) and structured using laser light so as to form on said substrate (10) a plurality of adjacent, separate resistor lands (24) having a predetermined approximate resistance value, allows the simplified and cheap manufacturing by performing the electrical insulation of the resistor elements (24) and the structuring of the individual resistor lands (24) for the entire resistor land simultaneously by means of a laser-lithographic direct exposure method.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: February 14, 2006
    Assignee: BC Components Holdings B.V.
    Inventors: Wolfgang Werner, Horst Wolf, Reiner Wilhelm Kuehl
  • Patent number: 6995035
    Abstract: A method of making a top-emitting OLED device, includes providing over a substrate laterally spaced and optically opaque lower electrodes and upper electrode busses which are electrically insulated from the lower electrodes; depositing an organic EL medium structure over the lower electrodes and the upper electrode busses; selectively removing the organic EL medium structure over at least portions of the upper electrode busses to reveal at least upper surfaces of the upper electrode busses; and depositing a light transmissive upper electrode over the organic EL medium structure so that such upper electrode is in electrical contact with at least upper surfaces of the upper electrode busses.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: February 7, 2006
    Assignee: Eastman Kodak Company
    Inventors: Ronald S. Cok, Steven A. Van Slyke
  • Patent number: 6967125
    Abstract: A quad flat no-lead (QFN) grid array semiconductor package and method for making the same is disclosed. The package includes a semiconductor die and a lead frame having a plurality of conductive elements patterned in a grid-type array. A plurality of bond pads on the semiconductor die is coupled to the plurality of conductive elements, such as by wire bonding. The semiconductor die and at least a portion of the lead frame are encapsulated in an insulative material, leaving the conductive elements exposed along a bottom major surface of the package for subsequent electrical connection with higher-level packaging. Individual conductive lead elements, as well as the grid array pattern, are formed by wire bonding multiple bond pads to a single lead at different locations and subsequently severing the lead between the bonding locations to form multiple conductive elements from each individual lead.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: November 22, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Setho Sing Fee, Lim Thiam Chye
  • Patent number: 6894747
    Abstract: A flat organic insulating layer is formed on a substrate provided with thin film transistors by coating and baking. Next, a pulse-shaped laser beam is irradiated on the organic insulating layer and a contact hole and an undulation are formed in and on the organic insulating layer by ablation. The undulation is formed in such a way as to have four or more height levels.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: May 17, 2005
    Assignee: NEC LCD Technologies, Ltd.
    Inventor: Hiroshi Okumura
  • Patent number: 6887804
    Abstract: A set (50) of one or more laser pulses (52) is employed to remove passivation layer (44) over a conductive link (22). The link (22) can subsequently be removed by a different process such as chemical etching. The duration of the set (50) is preferably shorter than 1,000 ns; and the pulse width of each laser pulse (52) within the set (50) is preferably within a range of about 0.05 ps to 30 ns. The set (50) can be treated as a single “pulse” by conventional laser positioning systems (62) to perform on-the-fly material removal without stopping whenever the laser system (60) fires a set (50) of laser pulses (52) at each target area (51). Conventional wavelengths in the IR range or their harmonics in the green or UV range can be employed.
    Type: Grant
    Filed: February 7, 2003
    Date of Patent: May 3, 2005
    Assignee: Electro Scientific Industries, Inc.
    Inventors: Yunlong Sun, Robert F. Hainsey, Lei Sun
  • Patent number: 6881687
    Abstract: An improved semiconductor wafer processing apparatus 10 includes a series of processing stations combined in one form, coupled together by computer-controlled cluster tooling. Wafers are supplied in a pod to an input station 28 which initiates a data record for recording processing results at each station. A sacrificial film 140 is applied to the surface 135 of each wafer. Individual wafers are transferred to a computer-controlled defect-mapping station 14 where particulate defects 130 are identified and their position coordinates recorded. Defect-mapped wafers are transferred to a computer-controlled laser area cleaning station 11 which lifts the defects and sweeps the wafer surface clean, except for stubborn defects. Clean wafers are transferred to a final mapping station 20 or 22, followed by transfer of the wafers to an output station 30.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: April 19, 2005
    Inventor: Paul P. Castrucci
  • Patent number: 6878567
    Abstract: A method and apparatus for fabrication of passivated microfluidic structures is disclosed. The method includes providing a substrate having a microfluidic structure formed therein. The microfluidic structure is embedded by an embedding layer. The method further includes passivating the embedded microfluidic structure by locally heating the microfluidic structure surface in a reactive atmosphere, wherein the passivated microfluidic structure is suitable for transporting a fluid.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: April 12, 2005
    Assignee: Intel Corporation
    Inventors: Paul Winer, George P. Vakanas
  • Patent number: 6872649
    Abstract: A light emitting-layer is provided on a substrate. A p-type semiconductor layer is provided on the light-emitting layer. An upper electrode is provided on the p-type semiconductor layer. The upper electrode includes an Au thin film coming into contact with the p-type semiconductor layer and an n-type transparent conductor film formed thereon. The n-type transparent conductor film is formed by laser ablation. Particularly, the method involves placing a substrate in a vacuum chamber, placing a target of the film material in the chamber, introducing oxygen into the chamber, laser-irradiating the target to emit atoms or molecular ions by ablation, and then depositing and oxidizing the atoms or ions to grow the transparent conductor film.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: March 29, 2005
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hideki Matsubara
  • Patent number: 6790689
    Abstract: A ring-type laser including a traveling wave cavity which incorporates at least first and second straight cavity sections and at least one curved cavity section. Corresponding first ends of the straight cavity sections are interconnected at a first light-emitting facet, and second ends of the straight sections are interconnected by the curved waveguide. Additional curved and straight sections can be linked to provide various ring configurations.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: September 14, 2004
    Assignee: BinOptics Corporation
    Inventor: Alex Behfar
  • Publication number: 20040126704
    Abstract: A method for manufacturing thin-film chip resistors, in which method a resistor layer (14) and a contact layer (15, 16) are applied onto the upper surface of a substrate (10) and structured using laser light so as to form on said substrate (10) a plurality of adjacent, separate resistor lands (24) having a predetermined approximate resistance value, allows the simplified and cheap manufacturing by performing the electrical insulation of the resistor elements (24) and the structuring of the individual resistor lands (24) for the entire resistor land simultaneously by means of a laser-lithographic direct exposure method.
    Type: Application
    Filed: August 26, 2003
    Publication date: July 1, 2004
    Inventors: Wolfgang Werner, Horst Wolf, Reiner Wilhelm Kuehl
  • Patent number: 6753253
    Abstract: Herein disclosed are a variety of techniques relating to the wiring and logic corrections on a chip by making use of the focused ion beam (which is shortly referred to as “FIB”) or the laser selection metal CVD. The time periods for the wiring corrections and for debugging and developing an electronic system are shortened by making use of the processing characteristics of the FIB. Illustratively, a hole is bored in an insulating film above a portion of a wiring which is to be connected to another wiring by means of a focused ion beam. The inside of the hole and a predetermined region on the insulating film are irradiated with either a laser beam or an ion beam in a metal compound gas to deposit metal in the hole and on said region and a connecting wiring is formed by means of optically pumped CVD.
    Type: Grant
    Filed: September 18, 1990
    Date of Patent: June 22, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Takahiko Takahashi, Fumikazu Itoh, Akira Shimase, Mikio Hongo, Satoshi Haraichi, Hiroshi Yamaguchi
  • Patent number: 6734083
    Abstract: Provision is made of a dicing apparatus, for dicing a plate-like workpiece, comprising a disk-like blade which rotates to form a groove in one surface of the workpiece; a water discharging portion which discharges water toward a bottom of the groove of the one surface of the workpiece to form a stream of water; and a laser light irradiating portion which irradiates a laser light in the stream of water and impinges the laser light onto the bottom of the groove while reflecting the laser light by an inner wall of the stream of water to remove the portion of the workpiece extending from the bottom of the groove to the other surface of the workpiece, so as to dice the workpiece.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: May 11, 2004
    Assignee: Tokyo Seimitsu Co., Ltd.
    Inventor: Kazuo Kobayashi
  • Patent number: 6720240
    Abstract: A nanowire, nanosphere, metallized nanosphere, and methods for their fabrication are outlined. The method of fabricating nanowires includes fabricating the nanowire under thermal and non-catalytic conditions. The nanowires can at least be fabricated from metals, metal oxides, metalloids, and metalloid oxides. In addition, the method of fabricating nanospheres includes fabricating nanospheres that are substantially monodisperse. Further, the nanospheres are fabricated under thermal and non-catalytic conditions. Like the nanowires, the nanospheres can at least be fabricated from metals, metal oxides, metalloids, and metalloid oxides. In addition, the nanospheres can be metallized to form metallized nanospheres that are capable as acting as a catalyst.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: April 13, 2004
    Assignee: Georgia Tech Research Corporation
    Inventors: James L. Gole, John D. Stout, Mark G. White
  • Publication number: 20040046179
    Abstract: A radiation-emitting semiconductor component has an improved radiation efficiency. The semiconductor component has a multilayer structure with an active layer for generating radiation within the multilayer structure and also a window having a first and a second main surface. The multi-layer structure adjoins the first main surface of the window. At least one recess, such as a trench or a pit, is formed in the window from the second main surface for the purpose of increasing the radiation efficiency. The recess preferably has a trapezoidal cross section tapering toward the first main surface and can be produced for example by sawing into the window.
    Type: Application
    Filed: September 9, 2003
    Publication date: March 11, 2004
    Inventors: Johannes Baur, Dominik Eisert, Michael Fehrer, Berthold Hahn, Volker Harle, Marianne Ortmann, Uwe Strauss, Johannes Volkl, Ulrich Zehnder
  • Patent number: 6667243
    Abstract: A method of manufacturing a semiconductor device etches a feature on a substrate in accordance with a photoresist mask. The photoresist mask is removed by plasma etching. Laser thermal annealing is performed to vaporize polymer residue created during the stripping of the photoresist mask, and to repair damage to the substrate.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: December 23, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark T. Ramsbey, Nicholas H. Tripsas, Arvind Halliyal, Jeffrey A. Shields, Yider Wu
  • Patent number: 6667252
    Abstract: A compound semiconductor substrate is manufactured by forming a higher-quality compound semiconductor layer having a smaller number of crystalline defects on a single-crystal substrate, and removing the single-crystal substrate without causing damage to the compound semiconductor layer. The method comprises the steps of forming the compound semiconductor layer (first, second and third compound semiconductor layers) on the single-crystal substrate (sapphire substrate) through crystal growth so as to partially have a space between the compound semiconductor layer and the single-crystal substrate; and removing the compound semiconductor layer from the sapphire substrate by irradiating the compound semiconductor layer from a side of the sapphire substrate with a laser beam passing through the single-crystal substrate and being absorbed in the compound semiconductor layer to melt an interface between the single-crystal substrate and the compound semiconductor.
    Type: Grant
    Filed: April 3, 2002
    Date of Patent: December 23, 2003
    Assignees: Sony Corporation, NEC Corporation
    Inventors: Takao Miyajima, Shigetaka Tomiya, Akira Usui
  • Patent number: 6617249
    Abstract: A method for fabricating a resonator, and in particular, a thin film bulk acoustic resonator (FBAR), and a resonator embodying the method are disclosed. An FBAR is fabricated on a substrate by introducing a mass loading top electrode layer. For a substrate having multiple resonators, the top mass loading electrode layer is introduced for only selected resonator to provide resonators having different resonance frequencies on the same substrate.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: September 9, 2003
    Assignee: Agilent Technologies, Inc.
    Inventors: Richard C. Ruby, John D. Larson, III, Paul D. Bradley
  • Patent number: 6602790
    Abstract: A method for patterning a multilayered conductor/substrate structure includes the steps of: providing a multilayered conductor/substrate structure which includes a plastic substrate and at least one conductive layer overlying the plastic substrate; and irradiating the multilayered conductor/substrate structure with ultraviolet radiation such that portions of the at least one conductive layer are ablated therefrom. In a preferred embodiment, a projection-type excimer laser system is employed to rapidly and precisely ablate a pattern from a mask into the at least one conductive layer. Preferably, the excimer laser is controlled in consideration of how well the at least one conductive layer absorbs radiation at particular wavelengths. Preferably, a fluence of the excimer laser is controlled in consideration of an ablation threshold level of at least one conductive layer.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: August 5, 2003
    Assignee: Avery Dennison Corporation
    Inventors: Kouroche Kian, Ramin Heydarpour
  • Publication number: 20030139068
    Abstract: In the present laser illumination method, laser radiation can illuminate a Cu fuse layer in a direction traversing a longitudinal direction of the Cu fuse layer to allow the laser radiation to illuminate a single location continuously without dispersing its energy. As a result the fuse layer can effectively be heated and completely be cut.
    Type: Application
    Filed: July 8, 2002
    Publication date: July 24, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masanao Maruta, Takeshi Iwamoto
  • Patent number: 6527967
    Abstract: A method of forming a thin-piece sample for use in an electron microscope. The ion beam scanning used for etching a sample block to form a thin-wall portion is initiated from the outer perimeter of two opposite sides of the sample block to be formed, one side at a time, and the ion beam is directed from the outer perimeter of the sample block inwards towards the center of the sample block. When the two sides of the sample block are etched from the outside into the sample block, a thin wall is produced at the interior portion of the sample block. Also, a plurality of samples may be set in a known positional relationship, and a series of forming functions, including ion beam scanning, may be programmed for automation, allowing a plurality of samples to be formed all at one time easily and efficiently.
    Type: Grant
    Filed: July 16, 1999
    Date of Patent: March 4, 2003
    Assignee: Seiko Instruments, Inc.
    Inventor: Hidekazu Suzuki
  • Patent number: 6472295
    Abstract: A method and apparatus for laser cutting a target material is disclosed. The method includes the steps of generating laser pulses from a laser system and applying the laser pulses to the target material so that the laser pulses cut through the material. The laser pulses have an approximately ellipse shaped spot, have a temporal pulse width shorter than about 100 nanoseconds, and have an energy density from about 2 to about 20 times the ablation threshold energy of the target material. The laser pulses are applied to the material such that the major axis of the ellipse shaped spot moves parallel to the cutting direction. The spot has a leading edge and a trailing edge on the major axis, and the energy density of each laser pulse increases from zero to a maximum along the leading edge and decreases back to zero along the trailing edge.
    Type: Grant
    Filed: August 27, 1999
    Date of Patent: October 29, 2002
    Assignee: JMAR Research, Inc.
    Inventors: James H Morris, Michael Powers, Harry Rieger
  • Patent number: 6468902
    Abstract: After making a GaN FET by growing GaN semiconductor layers on the surface of a sapphire substrate, the bottom surface of the sapphire substrate is processed by lapping, using an abrasive liquid containing a diamond granular abrasive material and reducing the grain size of the abrasive material in some steps, to reduce the thickness of the sapphire substrate to 100 &mgr;m or less. Thereafter, the bottom surface of the sapphire substrate is processed by etching using an etchant of phosphoric acid or phosphoric acid/sulfuric acid mixed liquid to remove a strained layer by lapping followed by making a via hole by etching the bottom surface of the sapphire substrate by using a similar etchant.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: October 22, 2002
    Assignee: Sony Corporation
    Inventor: Hiroji Kawai
  • Patent number: 6461929
    Abstract: A method for the fine tuning of a passive electronic component having at least a carrier substrate and at least one electrically conducting layer containing a material having a conducting nitride, a conducting oxynitride, a semiconductor, or chromium, by means of a focused laser emission, which laser emission induces a heating effect which heating effect causes the material to be converted to a locally electrically non-conducting material.
    Type: Grant
    Filed: January 7, 2000
    Date of Patent: October 8, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Hans-Peter H. Löbl, Detlef U. Wiechert
  • Patent number: 6413839
    Abstract: A method for separating a semiconductor wafer into several thousand devices or dies by laser ablation. Semiconductor wafers are initially pre-processed to create multiple devices, such as blue LEDs, on the wafers. The wafers are then mounted with tape coated with a generally high level adhesive. The mounted wafer is then placed on a vacuum chuck (which is itself positioned on a computer controlled positioning table) to hold it in place during the cutting process. The cutting surface is then covered with a protective layer to prevent contamination from the effluent resulting from the actual cutting process. A laser beam is generated and passed through optical elements and masks to create a pattern, such as a line or multiple lines. The patterned laser projection is directed at the wafer at a substantially normal angle and applied to the wafer until at least a partial cut is achieved through it.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: July 2, 2002
    Assignee: Emcore Corporation
    Inventors: Michael G. Brown, Ivan Eliashevich, Mark Gottfried, Robert F. Karlicek, Jr., James E. Nering
  • Patent number: 6400037
    Abstract: This marking method is carried out with an object to form a mark of high visibility on a surface of a metallic layer of such as a cover plate of a semiconductor device or the like without generating metallic debris or the like. According to this method, on a marking area of a metallic layer with a matte surface (Rmax: 0.5 to 5 &mgr;m), a laser beam is illuminated, thereby the metallic layer is melted, then re-solidified, thereby minute unevenness on the surface of the metallic layer is averaged and erased to be smooth. Thus formed marking portion reflects light specularly and is different in light reflectivity from an underlying portion which scatters light (diffuse reflection). Due to the difference of reflectivity, the marking portion can be visually discerned with excellency.
    Type: Grant
    Filed: September 20, 2000
    Date of Patent: June 4, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shoko Omizo
  • Patent number: 6383893
    Abstract: A method for forming a crack stop structure and a barrier to the diffusion of oxygen and water vapor in integrated circuits is provided.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: May 7, 2002
    Assignee: International Business Machines Corporation
    Inventors: Edward S. Begle, Richard P. Volant, Kevin S. Petrarca
  • Patent number: 6348362
    Abstract: A manufacturing method of a photovoltaic device comprising a plurality of unit cells including a first electrode of zinc oxide, a photovoltaic conversion layer, and a second electrode on a surface of a substrate includes a process for forming a zinc oxide film on the surface of the substrate, a process for eliminating a predetermined part of the zinc oxide film by laser beam irradiation and dividing the zinc oxide film into a plurality of the first electrodes, and a process for etching the surface of the substrate including the plurality of the first electrodes.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: February 19, 2002
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Manabu Sasaki, Katsunobu Sayama, Eiji Maruyama
  • Patent number: 6333485
    Abstract: In one aspect the invention provides a method for laser induced breakdown of a material with a pulsed laser beam where the material is characterized by a relationship of fluence breakdown threshold (Fth) versus laser beam pulse width (T) that exhibits an abrupt, rapid, and distinct change or at least a clearly detectable and distinct change in slope at a predetermined laser pulse width value. The method comprises generating a beam of laser pulses in which each pulse has a pulse width equal to or less than the predetermined laser pulse width value. The beam is focused above the surface of a material where laser induced breakdown is desired.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: December 25, 2001
    Assignee: International Business Machines Corporation
    Inventors: Richard Alan Haight, Peter P. Longo, Daniel Peter Morris, Alfred Wagner