Abstract: A method for radiation hardening synchronous Dynamic Random Access Memory (DRAM), where Error Detection And Correction (EDAC) is implemented on-chip. Each bank includes a plurality of interleaved single chip Static Random Access Memory (SRAM) cells with bit registers configured to interface with the interleaved SRAM cells. A first column multiplexer (MUX) configured to select which bit register is accessed. A second column multiplexer is configured to select an accessed byte with the WRITE burst or a READ burst from the selected bit registers of the first column multiplexer. EDAC logic is configured to check Error Correction Code (ECC) during a READ burst and generate ECC during an WRITE burst for SRAM writeback during a PRECHARGE command.

Abstract: A total ionizing dose suppression architecture for a transistor and a transistor circuit uses an “end cap” metal structure that is connected to the lowest potential voltage to overcome the tendency of negative charge buildup during exposure to ionizing radiation. The suppression architecture uses the field established by coupling the metal structure to the lowest potential voltage to steer the charge away from the critical field (inter-device) and keeps non-local charge from migrating to the “birds-beak” region of the transistor, preventing further charge buildup. The “end cap” structure seals off the “birds-beak” region and isolates the critical area. The critical area charge is source starved of an outside charge. Outside charge migrating close to the induced field is repelled away from the critical region. The architecture is further extended to suppress leakage current between adjacent wells biased to differential potentials.

Abstract: A method of forming bipolar junction devices, including forming a mask to expose the total surface of the emitter region and adjoining portions of the surface of the base region. A first dielectric layer is formed over the exposed surfaces. A field plate layer is formed on the first dielectric layer juxtaposed on at least the total surface of the emitter region and adjoining portions of the surface of the base region. A portion of the field plate layer is removed to expose a first portion of the emitter surface. A second dielectric layer is formed over the field plate layer and the exposed portion of the emitter. A portion of the second dielectric layer is removed to expose the first portion of the emitter surface and adjoining portions of the field plate layer. A common contact is made to the exposed first portion of the emitter surface and the adjoining portions of the field plate layer. In another embodiment, the field plate and emitter contact are formed simultaneously.

Abstract: Microelectronic apparatus having protection against high frequency crosstalk radiation, comprising: a planar insulating substrate; an active semiconductor electronic device located over a first region of the insulating substrate; and a doped semiconductor located in a second region of the insulating substrate substantially surrounding the first region. Apparatus further comprising a dissipative conductor overlaying and adjacent to the doped semiconductor. Apparatus additionally comprising metallic test probe contacts making electrical connections with the active semiconductor electronic device. Application of the apparatus to dissipate crosstalk radiation having a center frequency within a range between about 1 gigahertz and about 1,000 gigahertz. Methods for making the apparatus.

Abstract: A magnetically shielded circuit board having a conductive solenoid to repel high speed charged particles away from an integrated circuit chip. The conductive solenoid is embedded in the circuit board, or located around the circuit board, or located within an integrated circuit package, the integrated circuit package have been connected to the circuit board. The conductive solenoid is used for conducting an electrical current, the electrical current forming a magnetic field. The magnetic field will repel high speed charged particles away from the integrated circuit chip, the integrated circuit chip being within the integrated circuit package. The circuit board can be used in a space vehicle.

Abstract: A method of forming bipolar junction devices, including forming a mask to expose the total surface of the emitter region and adjoining portions of the surface of the base region. A first dielectric layer is formed over the exposed surfaces. A field plate layer is formed on the first dielectric layer juxtaposed on at least the total surface of the emitter region and adjoining portions of the surface of the base region. A portion of the field plate layer is removed to expose a first portion of the emitter surface. A second dielectric layer is formed over the field plate layer and the exposed portion of the emitter. A portion of the second dielectric layer is removed to expose the first portion of the emitter surface and adjoining portions of the field plate layer. A common contact is made to the exposed first portion of the emitter surface and the adjoining portions of the field plate layer. In another embodiment, the field plate and emitter contact are formed simultaneously.

Abstract: A method of precluding diffusion of a metal into adjacent chalcogenide material upon exposure to a quanta of actinic energy capable of causing diffusion of the metal into the chalcogenide material includes forming an actinic energy blocking material layer over the metal to a thickness of no greater than 500 Angstroms and subsequently exposing the actinic energy blocking material layer to said quanta of actinic energy. In one implementation, an homogenous actinic energy blocking material layer is formed over the metal and subsequently exposed to said quanta of actinic energy. A method of forming a non-volatile resistance variable device includes providing conductive electrode material over chalcogenide material having metal ions diffused therein.

Abstract: A method of forming an electrical contact to semiconductive material includes forming an insulative layer over a contact area of semiconductive material. A contact opening is etched through the insulative layer to the semiconductive material contact area. Such etching changes an outer portion of the semiconductive material exposed by the etching. The change is typically in the form of modifying crystalline structure of only an outer portion from that existing prior to the etch. The changed outer portion of the semiconductive material is etched substantially selective relative to semiconductive material therebeneath which is unchanged. The preferred etching chemistry is a tetramethyl ammonium hydroxidde solution. A conductive material within the contact opening is formed in electrical connection with the semiconductive material.

Abstract: A structure and method for creating an integrated circuit passivation (24) comprising, a circuit (16), a dielectric (18), and metal plates (20) over which an insulating layer (26) is disposed that electrically and hermetically isolates the circuit (16), and a discharge layer (32) that is deposited to form a passivation (24) that protects the circuit (16) from electrostatic discharges caused by, e.g., a finger, is disclosed.

Abstract: A high voltage radiation hardened power integrated circuit (PIC) with resistance to TID and SEE radiation effects for application in high radiation environments, such as outer space. TID hardness modification include forming gate oxide layers after high temperature junction processes, adding implant layers to raise the parasitic MOSFET thresholds with respect to native thresholds, and suppressing CMOS drain-to-source and intrawell transistor-to-transistor leakage. In addition, radhard field oxide is utilized. SEE ruggedness is improved by reducing the epi thickness over that of non-radhard devices, and increasing the epi concentration near the substrate junction. A radhard PIC rated to 400 V and capable of operating at 600 V or more is provided. The inventive PIC can withstand 100 krads of TID and a heavy ion Linear Energy Transfer of 37 MeV/(mg/cm2) at full rated voltage.

Abstract: A high voltage radiation hardened power integrated circuit (PIC) with resistance to TID and SEE radiation effects for application in high radiation environments, such as outer space. TID hardness modification include forming gate oxide layers after high temperature junction processes, adding implant layers to raise the parasitic MOSFET thresholds with respect to native thresholds, and suppressing CMOS drain-to-source and intrawell transistor-to-transistor leakage. In addition, radhard field oxide is utilized. SEE ruggedness is improved by reducing the epi thickness over that of non-radhard devices, and increasing the epi concentration near the substrate junction. A radhard PIC rated to 400 V and capable of operating at 600 V or more is provided. The inventive PIC can withstand 100 krads of TID and a heavy ion Linear Energy Transfer of 37 MeV/(mg/cm2) at full rated voltage.

Abstract: A EEPROM 140 has a storage transistor 160 with a gate insulating layer 104 of BPSG and a polysilicon gate 112.2 of the same layer as the polysilicon gate 112.1 of the FET transistor 150. The BPSG layer 104 has POHC traps that capture holes injected into N well 103.2. A positive voltage applied to N well 103.2 programs the storage transistor 160 off. Applying a positive voltage to the gate 112.2 neutralizes the holes stored in layer 104 and erases the memory of transistor 160.

Abstract: A method of making a resistor begins with forming a field effect transistor on a silicon semiconductor substrate. Then a first insulating layer is deposited on the field effect transistor. The first insulating layer is etched by the photolithography and etching techniques to form a bit line contact, and a bit line is subsequently formed. Next, upon the entire structure, a second insulating layer is formed and etched by the photolithography and ion etching techniques to form a contact hole with high aspect ratio. A polysilicon layer is deposited across the contact hole and the polysilicon outside the contact hole is removed, forming a polysilicon plug in the contact hole. Then, a third insulating layer is formed and etched to form a contact hole for metallurgy. After a first metal interconnection is formed, a third insulating layer is formed upon the entire structure and then etched to form a via hole by the photolithography and plasma etching techniques.

Abstract: In an SRAM having P-channel thin film transistors formed on N-channel drive MOS transistors each of which is composed of a first gate electrode, a first drain layer and a first source layer, N-channel transfer MOS transistors each of which is composed of a second gate electrode, first and second diffusion layers, the MOS transistors are formed on a substrate. A first insulating film is formed on the driver and transfer MOS transistors. On the first insulating film, the p-channel thin film transistors are formed, each of which is composed of a third gate electrode, a second source layer functioning a power supply line pattern, a second drain layer and a gate insulator. Also, at the same time, there are formed another power supply line pattern to be connected to a second source layer of another p-channel thin film transistor, and a wiring layer to be connected to a third gate electrode of the other p-channel thin film transistor.

Abstract: Disclosed is a semiconductor device having an enhanced current amount ratio, and a manufacturing method thereof. The semiconductor device includes a first transistor and a second transistor. There is a selective electric current capacity difference between the first transistor and the second transistor, wherein a gate degeneracy of the first transistor is different from a gate degeneracy of the second transistor. Among the first and second transistors, the gate degeneracy of the transistor requiring a small amount of current is higher than the gate degeneracy of the transistor requiring a large amount of current.

Abstract: A manufacturing method applicable for forming a via connection to the thin film transistor in a SRAM unit which resolves the problems arising from a conventional method for forming a via for linking up the drain of a load transistor with the gate of a driver transistor in a SRAM unit by changing the processing sequence and also by forming a plug instead of a via.

Abstract: A process for the preparation of an analytical sample characterized by depositing and separating solely the impurity to be analyzed from phosphoric acid; a process for analysis of the impurity characterized by depositing and separating solely the impurity from phosphoric acid and applying the separated material to analysis; a process for preparation of high grade phosphoric acid characterized by depositing and separating solely the impurity from phosphoric acid to be purified; a process for the fabrication of a semiconductor device characterized by using phosphoric acid, the impurity content of which is not more than 10.sup.-3 Bq/mL, defined by the concentration of a contained radioactive element selected from the group consisting of Pb, Bi and Po, as a processing solution.

Abstract: The present invention pertains to methods of forming integrated circuitry, methods of forming SRAM cells, and methods of reducing alpha particle inflicted damage to SRAM cells. Additionally, the present invention pertains to integrated circuitry. In one aspect, the invention includes a method which includes: a) forming at least one second conductivity type diffusion region beneath at least one of an SRAM cell pull-down device drain of a first conductivity type and an SRAM cell access device source of the first conductivity type; and b) not forming a second conductivity type diffusion region beneath at least one of a source of the SRAM cell pull-down device and a drain of the SRAM cell access device.

Abstract: A radiation-hard, low-power semiconductor device of the complementary metal-oxide semiconductor (CMOS) type which is fabricated with a sub-micron feature size on a silicon-on-insulator (SOI) substrate (12). The SOI substrate may be of several different types. The sub-micron CMOS SOI device has both a fabrication and structural complexity favorably comparable to conventional CMOS devices which are not radiation-hard. A method for fabricating the device is disclosed.

Abstract: A semiconductor device is described, incorporating electron traps at the interface between a semiconductor substrate and a gate dielectric layer of an insulated gate field effect transistor, such device being capable of retaining charge in the electron traps for a certain time, allowing volatile memory circuits to be produced wherein each cell occupies only the area required for a single transistor.

Abstract: A new-type silicon material is produced by hydrogen ion implantation and subsequent annealing, the annealing being preferably in two steps. The present invention raises surface mobility of a silicon wafer and produces a buried high-resistivity layer beneath a silicon surface layer. The resulting products are particularly useful for the improvement of yield and speed and radiation hardness of very large scale integrated circuits.