Abstract: There is disclosed a method of manufacturing a capacitor in a semiconductor device. In a Ta2O5 capacitor using a Ru lower electrode, the method processes the Ru lower electrode at low temperature before a Ta2O5 film of a dielectric film is deposited, so that Ru crystal particles are filled with oxygen atoms to form a good quality RuO2. Therefore, the disclosed method can prevent a lift phenomenon of a thin film by prohibiting a stress of the Ta2O5 dielectric film due to RuO2 generated between the Ta2O5 dielectric film and the Ru lower electrode during the deposition process of a Ta2O5 dielectric and a subsequent annealing process. Also, the disclosed method can prevent diffusion of oxygen atoms and oxidization of a TiN film underlying the Ru film from the Ta2O5 dielectric film. As a result, the method can improve leakage current and electrical characteristics of a capacitor.

Abstract: The present invention is directed to a method of forming conductive interconnections in an integrated circuit device. In one embodiment, the method comprises forming a dielectric stack comprised of multiple layers, and determining a thickness ratio of the layers of the stack. The method further comprises determining an etching process to be performed on the dielectric stack to define an opening for a conductive interconnection based upon the determined thickness ration, and performing the determined etch process on the dielectric stack.

Abstract: A method for manufacturing an integrated circuit capacitor is provided in the present invention. First, a semiconductor substrate is etched to form a contact hole. A polysilicon contact is then formed to fill into the contact hole. A metal layer is formed on the substrate and the polysilicon contact. Next, a silicon catching layer is formed on the metal layer. An annealing step is performed to substitute the silicon contact with a portion of said metal layer for forming a metal contact, wherein the silicon atom are driven to react with the silicon catching layer for forming a compound layer underneath the silicon catching layer. After the metal layer, the silicon catching layer and the compound layer are removed, the first conduction layer is formed on the substrate and the metal contact to serve as a bottom electrode. Then, a dielectric layer is formed along the surface of the first conduction layer. The second conduction layer is next formed on the dielectric layer to serve as a top electrode.

Abstract: A method of providing a semiconductor device with a selectively deposited inorganic electrically insulative layer, the device having exposed semiconductor surfaces and electrically conductive metal end terminations, in which the device is saturated in a phosphoric acid solution to form a phosphate layer on the exposed surfaces of the semiconductor but not on the metal end terminations. The device is thereafter plated by a conventional plating process and the plating is provided only on the end terminations.

Abstract: An improved RC network integrated circuit semiconductor device is disclosed which incorporates an improved method for fabrication. The new device and method includes the use of a tantalum nitride layer as the resistive material for the resistor and a protective metal layer formed between the resistive layer and a metal interconnect layer. The capacitor uses a metal electrode as one plate of the capacitor and a heavily doped semiconductor region as the other plate of the capacitor and separated from the one plate of the capacitor by a silicon nitride insulation layer.

Abstract: A cost-effective method for fabricating MIM capacitors (120). After metal (106) deposition, the metal oxide (108) is formed using an oxidation chemistry that includes CO2 and H2. The CO2/H2 gas ratio is controlled for selective oxidation. Thus, the metal (106) is effectively protected from oxidation due to the existence of both H2 and CO2 as strong reduction reagent.

Abstract: A method for manufacturing an inductor. A silicon substrate of a first conductive type is provided. A spiral conductive layer is formed over the silicon substrate. A doped region of a second conductive type is formed in the substrate below the spiral conductive layer. A doped region of the first conductive type is next formed in the substrate around the doped region of the second conductive type. A reverse-bias voltage is applied to the doped region of the first conductive type and the doped region of the second conductive type. The application of a reverse-bias voltage creates a depletion region beneath the doped region of the second conductive type and the space between the doped regions.

Abstract: A substrate has an insulating surface; a fine wire region disposed on the insulating surface of the substrate and extending long in one direction; a first insulating film formed on the fine wire region at least at a partial area along the longitudinal direction of the fine wire region; and a first micro box region formed on the first insulating film over the fine wire region at a partial area along the longitudinal direction of the fine wire region a semiconductor device. The semiconductor device has a fine wire region and a micro box region to realize control of a single electron level. The manufacturing method for the semiconductor device is also disclosed.

Abstract: A die including a corrosion monitoring feature is described. The die includes: (i) a surface including an active die region and a scribeline region that is adjacent the active die region; (ii) an insulating layer disposed above the surface and includes a first corrosion sensitive metal plug and a second corrosion sensitive metal plug in the scribeline region; and (iii) a metallization layer positioned above the insulating layer, the first corrosion sensitive metal plug and the second corrosion sensitive metal plug in the scribeline region and the metallization layer disposed above second corrosion sensitive metal plug is patterned to provide the metallization layer with a first opening extending from a top surface of the metallization layer down to a top surface of the second corrosion sensitive metal plug such that a solvent introduced above the top surface of the metallization layer flows into the second corrosion sensitive metal plug disposed below through the first opening in the metallization layer.

Abstract: Thin-film switching elements (20,21) of a display device or the like include a first electrode (22,23) on a substrate (11) and a layer of switching material (24,25) on the first electrode. These switching elements may be semiconductor PIN or Schottky diodes, or MIMs, or TFTs. The switching material is typically .alpha.-Si:H in the case of the semiconductor diodes and TFTs, and tantalum oxide or silicon nitride in the case of the MIMs. An auxiliary layer (28,29) of insulating material is provided between the first electrode (22,23) and the layer of switching material (24,25), leaving an edge (30,31) of the first electrode uncovered, so that the layer of switching material is connected to this edge only. The switching elements with this construction can be patterned using an inexpensive proximity printer, and have a low capacitance value, so counter-acting kickback and crosstalk which can occur in a switching matrix, e.g in the display of television pictures.

Abstract: A method of forming the FEM cell semi-conductor structure includes forming a device area for the ferroelectric memory (FEM) gate unit on a silicon substrate. Appropriate impurities are implanted into the device area to form conductive channels, for use as a source junction region, a gate junction region and a drain junction region. A FEM cell includes a FEM gate unit formed on the substrate. A gate junction region is formed between the source junction region and the drain junction region for the FEM gate unit on the FEM gate unit device area, which FEM gate unit includes a lower metal layer, a ferroelectric (FE) layer, and an upper metal layer. A shallow junction layer is formed between the FEM gate unit and the gate junction region, as another conductive channel, which extends into the drain junction region. The FEM gate unit is spaced apart from the source region and the drain region, as is the conductive channel between the FEM gate unit and the gate junction region.

Abstract: A method of fabricating an interconnect structure having improved electromigration resistance. Two conductive lines are formed over a substrate and isolated by a dielectric layer. A contact/via array including a plurality of row contact/vias and column contact/vias are formed within the dielectric layer and electrically connect to the two conductive lines. The load resistors are respectively inserted into the two conductive lines close to the contact/via array. The load resistors are parallel to each other and disposed to its corresponding contact/via array. The load resistors having various resistances are formed by a plurality of slots with various lengths, which are filled with dielectrics. Accordingly, the current paths from one conductive line to the other conductive line through the contact/vias and the load resistors corresponding to the two conductive lines have identical equivalent resistance.

Abstract: A structure of a conductive line. The structure of a conductive line comprises a substrate with two conductive lines formed thereon. These two conductive lines are isolated by the formation of a dielectric layer. The conductive lines are electrically connected by a contact/via array. The contact/via array further comprises contact/via columns and contact/via rows made up of contacts/vias. Each contact/via column and contact/via row are added with a load resistor, so that the equivalent resistance of each contact/via is identical.

Abstract: A method of forming a FEM cell semi-conductor structure includes forming a device area for the ferroelectric memory (FEM) gate unit on a silicon substrate. Appropriate impurities are implanted into the device area to form conductive channels, for use as a source junction region, a gate junction region and a drain junction region. A FEM cell includes a FEM gate unit formed on the substrate. A gate junction region is formed between the source junction region and the drain junction region for the FEM gate unit on the FEM gate unit device area, which FEM gate unit includes a lower metal layer, a ferroelectric (FE) layer, and an upper metal layer. A shallow junction layer is formed between the FEM gate unit and the gate junction region, as another conductive channel. The FEM gate unit is spaced apart from the source region and the drain region, as is the conductive channel between the FEM gate unit and the gate junction region.

Abstract: A two-terminal nonlinear device according to the present invention includes a lower electrode of a thin Ta film doped with nitrogen which is formed on a substrate, an anodized oxide film formed by anodizing a surface of the lower electrode, and an upper electrode of a metal thin film which is formed on the anodized oxide film, wherein the thin Ta film includes a structure in which first portions and second portions are alternately deposited, the first portions containing a different amount of nitrogen from that contained in the second portions.