Abstract: An apparatus comprising a plurality of solar cells that each comprise a nanowire titanium oxide core having graphene disposed thereon. By one approach this plurality of solar cells can comprise, at least in part, a titanium foil having the plurality of solar cells disposed thereon wherein at least a majority of the solar cells are aligned substantially parallel to one another and substantially perpendicular to the titanium foil. Such a plurality of solar cells can be disposed between a source of light and another modality of solar energy conversion such that both the solar cells and the another modality of solar energy conversion generate electricity using a same source of light.

Abstract: An ion implantation system for improving performance and extending lifetime of an ion source is disclosed whereby the selection, delivery, optimization and control of the flow rate of a co-gas into an ion source chamber is automatically controlled.

Abstract: A charged particle source comprises at least one gas inlet configured to supply gas particles, at least one tip having a tip apex being biased to provide an electrical field for generating charged particles, and at least one ionization area to which gas particles are supplied. The gas particles are ionized in the ionization area due to the electrical field. Additionally, the charged particle source comprises at least one first electrode configured to accelerate charged particles and at least one light emitting device providing a light beam. The light beam is focused to a focus point in the ionization area, specifically, to a focus volume such that the ionization area is at least partly positioned in the focus volume. The ionization area is arranged between the tip apex and the first electrode. The distance between the ionization area and the tip apex may be from 0.1 nm to 1 nm.

Abstract: A method for amorphizing a layer on a substrate is described. In one embodiment, the method includes treating the substrate with a first gas cluster ion beam (GCIB) using a first beam energy selected to yield an amorphous sub-layer within the substrate of a desired thickness, which produces a first interfacial roughness of an amorphous-crystal interface between the amorphous sub-layer and a crystalline sub-layer of the substrate. The method further includes treating the substrate with a second GCIB using a second beam energy, less than the first beam energy, to reduce the first interfacial roughness of the amorphous-crystal interface to a second interfacial roughness.

Abstract: A non-uniform ion implantation apparatus comprises a wide ion beam generator configured to generate a plurality of wide ion beams to irradiate at least two regions on the entire area of a wafer, and a wafer rotating device configured to rotate the wafer in a predetermined direction while the wide ion beams generated by the wide ion beam generator are irradiated to the wafer. Among the wide ion beams, at least one wide ion beam has a different dose from that of at least one different wide ion beam. Since the wide ion beams are irradiated at different doses to the wafer, a smooth circular border is formed between the regions to which the impurity ions are implanted to different concentrations. Since the position of the wafer is suitably changed for the wide ion beams, it is possible to control disposition of the regions implanted with the impurity ions of different concentrations.

Abstract: An ion source includes an arc chamber having an extraction aperture, and a plasma sheath modulator positioned in the arc chamber. The plasma sheath modulator is configured to control a shape of a boundary between a plasma and a plasma sheath proximate the extraction aperture, wherein the plasma sheath modulator includes a semiconductor. A well focused ion beam having a high current density can be generated by the ion source. A high current density ion beam can improve the throughput of an associated process. The emittance of the ion beam can also be controlled.

Abstract: If the size of a single crystal silicon layer attached is not appropriate, even when a large glass substrate is used, the number of panels to be obtained cannot be maximized. Therefore, in the present invention, a substantially quadrangular single crystal semiconductor substrate is formed from a substantially circular single crystal semiconductor wafer, and a damaged layer is formed by irradiation with an ion beam into the single crystal semiconductor substrate. A plurality of the single crystal semiconductor substrates are arranged so as to be separated from each other over one surface of a supporting substrate. By thermal treatment, a crack is generated in the damaged layer and the single crystal semiconductor substrate is separated while a single semiconductor layer is left over the supporting substrate. After that, one or a plurality of display panels is manufactured from the single crystal semiconductor layer bonded to the supporting substrate.

Abstract: An organic electroluminescent display device and a method of preparing the same are provided. The organic electroluminescent display device may include a first electrode formed on a substrate. A second electrode may be formed so as to be insulated from the first electrode. One or more organic layers may be interposed between the first electrode and the second electrode and include at least an emission layer. A protective layer may be formed so as to cover the second electrode. The protective layer may have a surface roughness (rms) of about 5 ? to about 50 ?. The organic electroluminescent display device including a protective layer having a low surface roughness may benefit from superior lifespan characteristics.

Abstract: A system and method for providing a pulsed atmospheric source of ions for chemical analysis includes a chamber containing a pair of electrodes and a second chamber with the sample gas. A narrow pulse of high voltage is applied between the electrodes to form an arc which emits ultraviolet light directly into the sample gas chamber through an aperture connecting the chambers. The ultraviolet photons ionize the sample gas and the resultant sample gas ions are then swept into a chemical detector by an electric field.

Abstract: Single-walled carbon nanotube transistor devices, and associated methods of making such devices include a porous structure for the single-walled carbon nanotubes. The porous structure may be anodized aluminum oxide or another material. Electrodes for source and drain of a transistor are provided at opposite ends of the single-walled carbon nanotube devices. A concentric gate surrounds at least a portion of a nanotube in a pore. A transistor of the invention may be especially suited for power transistor or power amplifier applications.

Abstract: An ion source includes an arc chamber having an extraction aperture, and a plasma sheath modulator. The plasma sheath modulator is configured to control a shape of a boundary between plasma and a plasma sheath proximate the extraction aperture. The plasma sheath modulator may include a pair of insulators positioned in the arc chamber and spaced apart by a gap positioned proximate the extraction aperture. A well focused ion beam having a high current density can be generated by the ion source. A high current density ion beam can improve the throughput of an associated process. The emittance of the ion beam can also be controlled.

Abstract: An ion source and method for providing ionized particles to a molecular/atomic analyser, such as a mass spectrometer, are disclosed. The ion source includes a vessel defining a channel; a gas inlet extending from the gas source into the channel, for introducing a gas flow into the channel; a sample inlet extending into the channel for introducing sample within the channel; and an ionizer to ionize the sample in the channel. The vessel is sufficiently sealed to allow the channel to be pressurized, at a pressure in excess of 100 Torr. At least one gas source maintains the pressure of the channel at a pressure in excess of 100 Torr and the pressure exterior to the channel at a pressure in excess of 0.1 Torr and provides a gas flow that sweeps across the ionizer to guide and entrain ions from the ionizer to the outlet.

Abstract: An implanter provides two-dimensional scanning of a substrate relative to an implant beam so that the beam draws a raster of scan lines on the substrate. The beam current is measured at turnaround points off the substrate and the current value is used to control the subsequent fast scan speed so as to compensate for the effect of any variation in beam current on dose uniformity in the slow scan direction. The scanning may produce a raster of non-intersecting uniformly spaced parallel scan lines and the spacing between the lines is selected to ensure appropriate dose uniformity.

Abstract: A composite material that may be used for a thin membrane is disclosed. This composite material includes first material that has a quasi-periodic system of vertical trenches (nanotrenches) with wavelength period that may be in the range between 20 and 500 nm. These nanotrenches are formed as openings between bordering elongated elements. The nanotrenches are at least partially filled with a second material that has physical-chemical characteristics substantially different from the first material.

Abstract: A method is provided for modifying a circuit containing a plurality of electrodes, within a substrate, comprising the steps of: (a) selecting at least two electrodes for making a connection; (b) removing materials covering the electrodes with a focused ion beam (FIB) or a laser to form contact holes for respectively exposing the electrodes; (c) depositing in the contact holes a conductive material for forming electrically conductive piers, by applying the focused ion beam (FIB) or laser, with gas molecules ejected from a nozzle; (d) disposing an electrically conductive viscid material over each of the electrically conductive piers; and (e) disposing an electrically conductive bridge floor to connect with the electrically conductive viscid material to form an electrically conductive bridge.

Abstract: A damascene process incorporating a GCIB step is provided. The GCIB step can replace one or more CMP steps in the traditional damascene process. The GCIB step allows for selectable removal of unwanted material and thus, reduces unwanted erosion of certain nearby structures during damascene process. A GCIB step may also be incorporated in the damascene process as a final polish step to clean up surfaces that have been planarized using a CMP step.

Abstract: An ion implanter includes a source of a stationary, planar ion beam, a set of beamline components that steer the ion beam along a normal beam path as determined by first operating parameter values, an end station that mechanically scans the wafer across the normal beam path, and control circuitry that responds to a glitch in the ion beam during implantation pass to (1) immediately alter an operating parameter of at least one of the beamline components to a second value to direct the ion beam away from the normal beam path and thereby cease implantation at an implantation transition location on the wafer, (2) subsequently move the wafer to an implantation-resuming position in which the implantation transition location on the wafer lies directly on the normal path of the ion beam, and (3) return the operating parameter to its first value to direct the ion beam along the normal beam path and resume ion implantation at the implantation transition location on the wafer.

Abstract: A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as a mask, to form a doped depletion region beneath and separated from the source/drain regions. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. The doped depletion region and substrate form depletion regions between the source/drain regions and the doped depletion region. We perform a S/D implant by implanting ions having a second conductivity type into the substrate to form S/D regions. The doped depletion region and depletion regions reduce the capacitance between the source/drain regions and the substrate.

Abstract: A method for fabricating a semiconductor memory device in which a logic circuit and a nonvolatile memory are provided on a semiconductor substrate includes the steps of: forming an isolation region; forming a protective film made of an insulating material over the semiconductor substrate in a logic circuit region and a nonvolatile memory region; selectively introducing impurity ions in part of the semiconductor substrate in the logic circuit region; and removing the protective film formed over the logic circuit region. The step of introducing the impurity ions is performed before the step of removing the protective film is performed.

Abstract: Method and device for cutting a wire with a small number of processing operations. The method includes forming a cut portion by scanning the semiconductor substrate with a focused ion beam to cut the wire. The method further includes forming a clear region continuously from the cut portion by scanning the semiconductor substrate with the focused ion beam. The clear region is free of stray material of the wire.

Abstract: The present invention provides a method for forming a contact plug in a semiconductor device capable of preventing an increase of contact resistance caused by a decrease in dopant concentration and suppressing diffusions of dopants implanted into the contact. The dopants are doped in a manner to allow the conductive layer to have different doping distributions with respect to a thickness. Particularly, the dopants are doped until reaching a target deposition thickness by gradually increasing a concentration of the dopants from a first concentration to a second concentration for an interval from an initial deposition of the conductive layer to the target deposition thickness, and the second concentration is consistently maintained throughout for an interval from the target deposition thickness to a complete deposition thickness.

Abstract: Dose uniformity of a scanning ion implanter is determined. A base beam current is measured at the beginning and/or the end of a complete scan over the whole substrate area. This base beam current is measured at a time when the measurement should be unaffected by outgassing from a substrate being implanted and a base dose distribution map is then calculated for the scan in question. During the scan itself beam instability events are detected and the magnitude and position in the scan of the detected instability events is measured. Corresponding deviations in the calculated base dose map are determined and subtracted from the previously calculated base dose distribution map to provide a corrected distribution map. By determining overall dose uniformity substractively in this way, good overall accuracy can be obtained with lesser accuracy in the measurement of the beam instability events.

Abstract: Disclosed are an ion implantation method capable of dramatically increasing an implantation rate of hydrogen ions into a semiconductor substrate and a method for manufacturing an SOI wafer, in which manufacturing efficiency of the SOI wafer is sufficiently high. When the hydrogen ions are implanted to a predetermined depth of the semiconductor substrate, hydrogen gas is introduced into a chamber where an inner pressure is reduced and a predetermined magnetic field is formed, plasma is generated by introducing a microwave into the magnetic field, hydrogen ion beams containing hydrogen molecule ions is extracted from the plasma, and the hydrogen molecule ions are irradiated and implanted onto the semiconductor substrate. Thus, a throughput in the hydrogen ion implantation is improved, thus making it possible to enhance the manufacturing efficiency of the SOI wafer.

Abstract: A gate structure (4), an LDD region (6) and a sidewall (7) are provided in this order. Arsenic ions (8) are thereafter implanted into the upper surface of a silicon substrate (1) by tilted implantation. The next step is annealing for forming an MDD region (9) in the upper surface of the silicon substrate (1). The MDD region (9) and the gate structure (4) do not overlap one another in plan view. Further, the MDD region (9) formed into a depth shallower than that of the LDD region (6) is higher in concentration than the LDD region (6). Thereafter a source/drain region (11) higher in concentration than the MDD region (9) is provided by vertical implantation into a depth greater than that of the LDD region (6).

Abstract: A method for fabricating a semiconductor memory device is provided to increase the etch selectivity of photoresist by changing the matter properties thereof in forming a trench isolation region. The method includes the steps of: depositing first and second insulating layers on a semiconductor substrate where a shallow trench isolation (STI) region and a deep trench isolation (DTI) region are defined; forming the STI region by selectively etching the second and first insulating layers and the semiconductor substrate; forming a photoresist to cover the STI region and curing the surface of the photoresist; and forming the DTI region by using the cured photoresist and the second insulating layer as a mask.

Abstract: A semiconductor device including a substrate having a dopant of a first polarity, a first semiconducting structure including a dopant of a second polarity disposed over the substrate, and having substantially planar top and side surfaces. The semiconductor device includes a first junction, formed between the first semiconducting structure and the substrate, having an area wherein at least one lateral dimension is less than about 75 nanometers.

Abstract: A method is provided for making ultra-shallow diffused junctions using an elemental dopant. A semiconductor wafer is cleaned for providing a clean reaction surface. The cleaned wafer in loaded onto a stage located in a doping system. A quantity of elemental dopant atoms are placed in a partially enclosed elemental dopant source which is within a secondary vacuum enclosure. A quantity of the elemental dopant atoms having thermal velocities are deposited onto a surface of the wafer, and the wafer is heated for diffusing the elemental dopant into the wafer. In one embodiment, the heating is conducted by heating the wafer in ultra-high vacuum for diffusing the portion of the doping atoms into the wafer, and the deposition and heating occur simultaneously. In another embodiment, the surface of the wafer is hydrogen terminated, the wafer is removed from the UHV system, and the heating of the wafer is conducted outside of the UHV system by heating the wafer in a furnace.

Abstract: An integrated circuit fabrication process to pattern reduced feature size is disclosed herein. The process includes reducing the width of a patterned area of a patterned photoresist layer provided over a substrate before patterning the substrate. The patterned area is representative of a feature to be formed in the substrate. The width of the feature is reduced by an electron beam mediated heating and flowing of select areas of the patterned photoresist layer.

Abstract: Disclosed are a method and apparatus for forming an insulating film on the surface of a semiconductor substrate capable of improving the quality and electrical properties of the insulating film with no employment of high-temperature heating and with good controllability. After the surface of a silicon substrate is cleaned, a silicon dioxide film having a thickness of 1-20 nm is formed on the substrate surface. The silicon substrate is exposed to plasma generated by electron impact, while the silicon substrate is maintained at a temperature of 0° C. to 700° C. Thus, nitrogen atoms are incorporated into the silicon dioxide film, obtaining a modified insulating film having good electrical properties.

Abstract: Plasma enhanced chemical vapor deposition (PECVD) reactors and methods of effecting the same are described. In accordance with a preferred implementation, a reaction chamber includes first and second electrodes operably associated therewith. A single RF power generator is connected to an RF power splitter which splits the RF power and applies the split power to both the first and second electrodes. Preferably, power which is applied to both electrodes is in accordance with a power ratio as between electrodes which is other than a 1:1 ratio. In accordance with one preferred aspect, the reaction chamber comprises part of a parallel plate PECVD system. In accordance with another preferred aspect, the reaction chamber comprises part of an inductive coil PECVD system. The power ratio is preferably adjustable and can be varied. One manner of effecting a power ratio adjustment is to vary respective electrode surface areas.

Abstract: A method of forming a silicon nitride layer or film on a semiconductor wafer structure includes forming a silicon nitride layer on the surface of a wafer structure using a molecular beam of high purity elemental Si and an atomic beam of high purity nitrogen. In a preferred embodiment, a III-V compound semiconductor wafer structure is heated in an ultra high vacuum system to a temperature below the decomposition temperature of said compound semiconductor wafer structure and a silicon nitride layer is formed using a molecular beam of Si provided by either thermal evaporation or electron beam evaporation, and an atomic nitrogen beam provided by either RF or microwave plasma discharge.

Abstract: An IC wiring connecting method for interconnecting conductive lines of the same wiring plane of an IC chip for correcting the wiring, for interconnecting conductive lines of different wiring lanes of a multilayer IC chip at the same position, or for connecting a conductive line of a lower wiring plane of a multilayer IC chip to a conductive line formed at a separate position on the same multilayer IC chip. The insulating film or films covering conductive lines to be interconnected are processed by an energy beam such as a concentrated ion beam to form holes so as to expose the respective parts of the conductive lines where the conductive lines are to be interconnected, then a metal is deposited over the surfaces of the holes and an area interconnecting the holes by irradiating the surfaces of the holes and the area by an energy beam or a concentrated ion beam in an atmosphere of a gaseous organic metal compound to form a conductive metal film electrically interconnecting the conductive lines.