Abstract: A semiconductor device which includes a passivation structure formed with a conductive strip of resistive material that crosses itself once around the active region of the device to form a first closed loop, a continuous strip that loops around the first closed loop without crossing itself which crosses itself a second time to form a second closed loop.

Abstract: A method is provided for forming a semiconductor-detection device that provides internal gain. The method includes forming a plurality of bottom trenches in a bottom surface of an n-doped semiconductor wafer; and forming a second plurality of top trenches in a top surface of the semiconductor wafer. The bottom surface and the top surface are opposed surfaces. Each of the bottom trenches is substantially parallel to and substantially juxtaposed to an associated one of the top trenches. The method further includes doping the semiconductor wafer with at least one p-type dopant to form a p-region that defines at least one n-well within the p-region, wherein a p-n junction is formed substantially at an interface of the n-well and the p-region; and removing a portion of the bottom surface to form a remaining-bottom surface, wherein a portion of the n-well forms a portion of the remaining-bottom surface.

Abstract: A semiconductor system having a pn transition and a method for manufacturing a semiconductor system are disclosed. The semiconductor system is designed in the form of a chip having an edge region, the semiconductor system includes a first layer of a first conductivity type and a second layer of a second conductivity type, which is of opposite polarity to the first conductivity type. The first layer has an edge region and a center region, the pn transition being provided between the first layer and the second layer. The second layer is more weakly doped in its edge region than in its center region, and the boundary surface of the pn transition at the edge region is non-parallel to the main chip plane.

Abstract: A method of making a bi-directional transient voltage suppression device is provided, which comprises: (a) providing a p-type semiconductor substrate; (b) epitaxially depositing a lower semiconductor layer of p-type conductivity; (c) epitaxially depositing a middle semiconductor layer of n-type conductivity over the lower layer; (d) epitaxially depositing an upper semiconductor layer of p-type conductivity over the middle layer; (e) heating the substrate, the lower epitaxial layer, the middle epitaxial layer and the upper epitaxial layer; (f) etching a mesa trench that extends through the upper layer, through the middle layer and through at least a portion of the lower layer, such that the mesa trench defines an active area for the device; and (g) thermally growing an oxide layer on at least those portions of the walls of the mesa trench that correspond to the upper and lower junctions of the device.

Abstract: A semiconductor system (200), particularly a diode, having a p-n junction is proposed, that is formed as a chip having an edge area, which includes a first layer (2) of a first conductivity type and a second layer (1, 3) of a second conductivity type; the second layer (1, 3) including at least two sublayers (1, 3); both sublayers (1, 3) forming a p-n junction with the first layer (2); the p-n junction of the first layer (2) with the first sublayer (3) being provided exclusively in the interior of the chip, and the p-n junction between the first layer (2) and the second sublayer (1) being provided in the edge area of the chip; for each cross-section of the chip area parallel to the chip plane, the first sublayer (3) corresponding only to a part of such a cross-section.

Abstract: To provide a method for manufacturing a thermoelectric semiconductor material or a thermoelectric semiconductor element and method for manufacturing a thermoelectric module effective in improving thermoelectric performance. The thermoelectric semiconductor material is manufactured by producing a laminated body of thin powders manufactured by a quenching roller method, and compressing simultaneously the side surfaces of the laminated body using a secondary punch.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: Silicon carbide power devices are fabricated by masking the surface of a silicon carbide substrate to define an opening at the substrate, implanting p-type dopants into the silicon carbide substrate through the opening at implant energy and dosage that form a deep p-type implant, and implanting n-type dopants into the silicon carbide substrate through the opening at implant energy and dosage that form a shallow n-type implant relative to the deep p-type implant. The deep p-type implant and the shallow n-type implant are annealed at less than 1650° C., but preferably more than about 1500°. The annealing preferably takes place for between about five minutes and about thirty minutes. Ramp-up time from room temperature to the anneal temperature is also controlled to be less than about one hundred minutes but more than about thirty minutes. Ramp-down time after annealing is also controlled by decreasing the temperature from the annealing temperature to below about 1500° C.

Abstract: Silicon carbide power devices are fabricated by masking the surface of a silicon carbide substrate to define an opening at the substrate, implanting p-type dopants into the silicon carbide substrate through the opening at implant energy and dosage that form a deep p-type implant, and implanting n-type dopants into the silicon carbide substrate through the opening at implant energy and dosage that form a shallow n-type implant relative to the deep p-type implant. The deep p-type implant and the shallow n-type implant are annealed at less than 1650.degree. C., but preferably more than about 1500.degree.. The annealing preferably takes place for between about five minutes and about thirty minutes. Ramp-up time from room temperature to the anneal temperature is also controlled to be less than about one hundred minutes but more than about thirty minutes. Ramp-down time after annealing is also controlled by decreasing the temperature from the annealing temperature to below about 1500.degree. C.

Abstract: To ensure bulk breakdown when the mesa diode with a positive bevel angle is reverse biased, the diffused region is formed with thinner edge portions. This eliminates corner or edge effects which create conditions of high electric field, resulting in decreased breakdown voltage and clamping voltage levels. The edges of the surface of epitaxial region are covered with a narrow oxide layer prior to diffusion. The middle portion of the surface remains uncovered. Diffusing through the oxide results in a diffused region which is thinner along the edges of the device than in the interior region below the exposed surface portion. The oxide thickness controls the depth of the edge diffusion.

Abstract: An insulated gate field effect transistor is manufactured according to a process in which an insulated gate structure is formed along a semiconductor chip. Dopant is introduced into the chip to form a body region, semiconductor material outside the body region forming a drain region. Dopant is introduced into the chip at the location of part of the body region to form a source region spaced apart from the drain region by a channel region. Dopant of the same conductivity type as the body-region dopant is introduced through a dopant-introducing section of the chip's upper surface and into the chip at the location of part of the body region to form a sub-surface peaked portion of the body region, the dopant-introducing section being spaced laterally apart from the channel and source regions. The sub-surface peaked portion reaches a peak net dopant concentration below the chip's upper surface so as to improve the transistor's ruggedness under drain avalanche conditions.

Abstract: A semiconductor structure including: a substrate having a step portion; a first semiconductor layer formed on a region of the substrate which is selectively irradiated by light at an angle with respect to the projecting portion by using the step portion as a mask; and a second semiconductor layer formed on a region of the substrate shaded by the step portion.

Abstract: A method for forming a semiconductor device with a graded lightly-doped drain (LDD) structure is disclosed. The method includes providing a semiconductor substrate (10) having a gate region (14 and 16) thereon, followed by forming a pad layer (18) on the substrate and the gate region. Next, ions are implanted into the substrate, and a spacer (22) is formed on sidewalls of the gate region, wherein the first spacer has a concave surface inwards on a surface of the first spacer. Finally, ions are further implanted into the substrate using the gate region and the spacer as a mask, thereby forming a graded doping profile (20) in the substrate.

Abstract: A thin film transistor for an antistatic circuit includes: wells formed on a silicon substrate; insulating layers for electrical isolation between electrodes formed within the wells; low density impurity diffused regions respectively interposed between the insulating layers; a first high-density impurity diffused region formed within one low-density impurity diffused region; a second high-density impurity diffused region formed within the other low-density impurity diffused region; interlevel insulating layers formed on the insulating layers and the low-density impurity diffused layers; and metal gate electrodes formed on the low-density impurity diffused layers and the interlevel insulating layers; at least one of the first high-density impurity diffused region and the second high-density impurity diffused region being arranged to overlap an active region, inward from outside edges of the active region.

Abstract: A substantial portion of the material at the pn junction (27) of the photodiode (37, 41) having an implanted region extending to a surface thereof is selectively removed (39), leaving a very small junction region (35, 43) with the remainder of the p-type (23) and n-type (25) material of each photodiode being spaced apart or electrically isolated at what was originally the junction. In the ion implanted n-type on p-type approach, the majority of the signal is created in the implanted n-type region while the majority of the noise is generated in the p-type region. By selectively removing p-type material, n-type material or both from the pn junction of the diode or otherwise electrically isolating most of the p-type and n-type regions from each other at the pn junction and thereby minimizing the pn junction area, noise is greatly reduced without affecting the signal response of the photodiode.

Abstract: An MOS structure is disclosed which is provided with a trench in the substrate adjacent the channel region of the substrate, i.e., adjacent the area of the substrate over which the gate oxide and gate electrode are formed. The region of the substrate beneath the trench is lightly doped to provide a deeper LDD region in the substrate between the channel and the drain region so that electrons traveling through the channel to the drain region follow a path deeper in the substrate and farther spaced from the gate oxide in the region of the substrate between the source region and the drain region where high fields are encountered by electrons traveling through the channel from the source region to the drain region.