Semiconductor On Specified Insulator Patents (Class 438/967)
  • Patent number: 8999764
    Abstract: Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Ian D. Melville, Kevin S. Petrarca, Kenneth P. Rodbell
  • Patent number: 8932940
    Abstract: Embodiments of the invention provide a method for direct heteroepitaxial growth of vertical III-V semiconductor nanowires on a silicon substrate. The silicon substrate is etched to substantially completely remove native oxide. It is promptly placed in a reaction chamber. The substrate is heated and maintained at a growth temperature. Group III-V precursors are flowed for a growth time. Preferred embodiment vertical Group III-V nanowires on silicon have a core-shell structure, which provides a radial homojunction or heterojunction. A doped nanowire core is surrounded by a shell with complementary doping. Such can provide high optical absorption due to the long optical path in the axial direction of the vertical nanowires, while reducing considerably the distance over which carriers must diffuse before being collected in the radial direction. Alloy composition can also be varied. Radial and axial homojunctions and heterojunctions can be realized. Embodiments provide for flexible Group III-V nanowire structures.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: January 13, 2015
    Assignee: The Regents of the University of California
    Inventors: Deli Wang, Cesare Soci, Xinyu Bao, Wei Wei, Yi Jing, Ke Sun
  • Patent number: 8802534
    Abstract: A bond substrate is attached with an incline toward the setting surface of a base substrate. Accordingly, an attachment starting portion can be limited. Further, the bond substrate is provided so that part of the bond substrate extends beyond a support base and the part is closest to the base substrate. Because of this, part of the bond substrate is separated from the support base with the use of an end portion of the support base as a fulcrum point because the support base is not provided below the contact portion, and attachment sequentially proceeds from a portion which gets close to the base substrate; thus, stable attachment can be performed without an air layer remaining at the interface between the bond substrate and the base substrate.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: August 12, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshihiro Komatsu, Tomoaki Moriwaka, Kojiro Takahashi
  • Patent number: 8383491
    Abstract: A step of forming an insulating film over a semiconductor substrate and forming an embrittled region in the semiconductor substrate by irradiating the semiconductor substrate with accelerated ions through the insulating film; a step of disposing a surface of the semiconductor substrate and a surface of a base substrate opposite to each other and bonding the surface of the insulating film to the surface of the base substrate; a step of forming a semiconductor layer over the base substrate with the insulating film interposed therebetween by causing separation along the embrittled region by performing heat treatment after the surface of the insulating film and the surface of the base substrate are bonded to each other; a step of performing etching treatment on the semiconductor layer; a step of irradiating the semiconductor layer subjected to the etching treatment with a laser beam; and a step of irradiating the semiconductor layer irradiated with the laser beam with plasma.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: February 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Motomu Kurata, Shinya Sasagawa, Taiga Muraoka
  • Patent number: 8338270
    Abstract: First etching is performed on a surface of a single crystal semiconductor layer formed with no substrate bias applied. The single crystal semiconductor layer is formed by attaching a single crystal semiconductor substrate including an embrittled region to a supporting substrate so that an oxide layer is sandwiched between the single crystal semiconductor substrate and the supporting substrate and separating the single crystal semiconductor substrate into the single crystal semiconductor layer and part of the single crystal semiconductor substrate at the embrittled region. After the first etching, the single crystal semiconductor layer is irradiated with a laser beam and at least part of the surface of the single crystal semiconductor layer is melted and solidified. Then, second etching is performed on the surface of the single crystal semiconductor layer with no substrate bias applied.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: December 25, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kosei Noda
  • Patent number: 8293626
    Abstract: It is an object to provide a homogeneous semiconductor film in which variation in the size of crystal grains is reduced. Alternatively, it is an object to provide a homogeneous semiconductor film and to achieve cost reduction. By introducing a glass substrate over which an amorphous semiconductor film is formed into a treatment atmosphere set at more than or equal to a temperature that is needed for crystallization, rapid heating due to heat conduction from the treatment atmosphere is performed so that the amorphous semiconductor film is crystallized. More specifically, for example, after the temperature of the treatment atmosphere is increased in advance to a temperature that is needed for crystallization, the substrate over which the semiconductor film is formed is put into the treatment atmosphere.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: October 23, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Naoki Okuno
  • Patent number: 7888235
    Abstract: A method for fabricating a semiconductor substrate. In an embodiment, this method includes the steps of transferring a seed layer on to a support substrate; and depositing a working layer on the seed layer to form a composite substrate. The seed layer is made of a material that accommodates thermal expansion of the support substrate and of the working layer. The result is a semiconductor substrate that includes the at least one layer of semiconductor material on a support substrate.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: February 15, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac
  • Patent number: 7799589
    Abstract: An optical waveguide apparatus having a very simple structure that can modulate a signal light guided through an optical waveguide is provided. A photoresist 13 is applied to an upper side of an SOI film 12, a photoresist mask 14 is formed, and the SOI film in a region that is not covered with the photoresist mask 14 is removed by etching to obtain an optical waveguide 15 having a single-crystal silicon core. Further, a light emitting device capable of irradiating the single-crystal silicon core with a light having a wavelength of 1.1 ?m or below is provided on a back surface side of a quartz substrate 20 to provide an optical waveguide apparatus. When the light emitting device 30 does not apply a light, the light guided through the optical waveguide 15 is guided as it is.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: September 21, 2010
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shoji Akiyama, Yoshihiro Kuboto, Atsuo Ito, Koichi Tanaka, Yuuji Tobisaka, Makoto Kawai
  • Patent number: 7749870
    Abstract: Provided is a method for producing an SOI substrate comprising a transparent insulating substrate and a silicon film formed on a first major surface of the insulating substrate wherein a second major surface of the insulating substrate which is opposite to the major surface is roughened, the method suppressing the generation of metal impurities and particles in a simple and easy way.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: July 6, 2010
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Makoto Kawai, Yoshihiro Kubota, Atsuo Ito, Kouichi Tanaka, Yuji Tobisaka, Shoji Akiyama, Hiroshi Tamura
  • Patent number: 7732867
    Abstract: Hydrogen ions are implanted to a surface (main surface) of the single crystal Si substrate 10 to form the hydrogen ion implanted layer (ion-implanted damage layer) 11. As a result of the hydrogen ion implantation, the hydrogen ion implanted boundary 12 is formed. The single crystal Si substrate 10 is bonded to the quartz substrate 20 having a carbon concentration of 100 ppm or higher, and an external shock is applied near the ion-implanted damage layer 11 to delaminate the Si crystal film along the hydrogen ion implanted boundary 12 of the single crystal Si substrate 10 out of the bonded substrate. Then, the surface of the resultant silicon thin film 13 is polished to remove a damaged portion, so that an SOQ substrate can be fabricated. There can be provided an SOQ substrate highly adaptable to a semiconductor device manufacturing process.
    Type: Grant
    Filed: November 2, 2007
    Date of Patent: June 8, 2010
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Koichi Tanaka, Makoto Kawai, Yuuji Tobisaka
  • Patent number: 7348226
    Abstract: A method (and resultant structure) of forming a semiconductor structure, includes processing an oxide to have a crystalline arrangement, and depositing an amorphous semiconductor layer on the oxide by one of evaporation and chemical vapor deposition (CVD).
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: March 25, 2008
    Assignee: International Business Machines Corporation
    Inventors: Nestor Alexander Bojarczuk, Jr., Matthew Warren Copel, Supratik Guha, Vijay Narayanan
  • Patent number: 7294536
    Abstract: A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: November 13, 2007
    Assignee: STMicroelectronics S.R.L.
    Inventors: Flavio Villa, Gabriele Barlocchi, Pietro Corona
  • Patent number: 7265029
    Abstract: Methods for fabricating a semiconductor substrate. In an embodiment, the technique includes providing an intermediate support, providing a nucleation layer, and providing at least one bonding layer between the intermediate support and the nucleation layer to improve the bonding energy therebetween, and to form an intermediate assembly. The method also includes providing at least one layer of a semiconductor material upon the nucleation layer, bonding a target substrate to the deposited semiconductor material to form a final support assembly comprising the target substrate, the deposited semiconductor material, and the intermediate assembly, and processing the final support assembly to remove the intermediate assembly. The result is a semiconductor substrate that includes the at least one layer of semiconductor material on the target substrate.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: September 4, 2007
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac
  • Patent number: 7253081
    Abstract: A method for treating a film of material, which can be defined on a substrate, e.g., silicon. The method includes providing a substrate comprising a cleaved surface, which is characterized by a predetermined surface roughness value. The substrate also has a distribution of hydrogen bearing particles defined from the cleaved surface to a region underlying said cleaved surface. The method also includes increasing a temperature of the cleaved surface to greater than about 1,000 Degrees Celsius while maintaining the cleaved surface in an etchant bearing environment to reduce the predetermined surface roughness value by about fifty percent and greater. Preferably, the value can be reduced by about eighty or ninety percent and greater, depending upon the embodiment.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: August 7, 2007
    Assignee: Silicon Genesis Corporation
    Inventors: Sien G. Kang, Igor J. Malik
  • Patent number: 7185417
    Abstract: A method for shaping an ABS of a magnetic head slider including a step of holding at least one row bar with a plurality of aligned thin-film magnetic head elements by adhering a first surface of the at least one row bar to an adhesive or UV tape capable of passing a laser beam there through, the first surface being opposite an ABS of the at least one row bar, a step of shaping the ABS of the at least one row bar in a convex shape by radiating a laser beam to the first surface of the at least one row bar through the adhesive or UV tape, a step of cutting the at least one row bar into individual magnetic head sliders, and a step of then, removing the magnetic head sliders from the adhesive or UV tape after weakening adhesion properties of the adhesive or UV tape.
    Type: Grant
    Filed: January 4, 2005
    Date of Patent: March 6, 2007
    Assignee: Sae Magnetics (H.K.) Ltd.
    Inventor: Osamu Fukuroi
  • Patent number: 7172930
    Abstract: A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: February 6, 2007
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Stephen W. Bedell, Joel P. de Souza, Keith E. Fogel, Alexander Reznicek, Devendra K. Sadana, Ghavam Shahidi
  • Patent number: 7109130
    Abstract: A method is provided for making an integrated circuit dielectric. A structure-directing agent (SDA) is provided. Preferably this structure-directing agent is a salt of a polycyclic organic compound. By use of the structure-directing agent, a film of a zeolite having a framework density below 15 T atoms per 1000 cubic angstroms and comprising primarily silicon and/or germanium atoms in the T positions is provided on a semiconductor substrate. Preferably the zeolite has the LTA structure. The structure-directing agent is removed from the film. The removal may be effected, for example, by heating or by chemically and/or photochemically decomposing the structure-directing agent, preferably in a manner which allows it to be recovered. The film is then optionally modified to reduce its hydrophilicity.
    Type: Grant
    Filed: May 4, 2005
    Date of Patent: September 19, 2006
    Assignee: California Institute of Technology
    Inventor: Mark E. Davis
  • Patent number: 7067400
    Abstract: A method of forming a substantially relaxed SiGe-on-insulator substrate in which the consumption of the sidewalls of SiGe-containing island structures during a high temperature relaxation annealing is substantially prevented or eliminated is provided. The method serves to maintain the original lateral dimensions of the patterned SiGe-containing islands, while providing a uniform and homogeneous Ge fraction of the islands that is independent of each island size. The method includes forming an oxidation mask on at least sidewalls of a SiGe-containing island structure that is located on a barrier layer that is resistant to Ge diffusion. A heating step is then employed to cause at least relaxation within the SiGe-containing island structure. The presence of the oxidation mask substantially prevents consumption of at least the sidewalls of the SiGe-containing island structure during the heating step.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: June 27, 2006
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Anda C. Mocuta
  • Patent number: 7018912
    Abstract: Disclosed is a method of fabricating nitride semiconductors in a MOCVD reactor. GaN is first deposited on an inner wall of the MOCVD reactor, and a sapphire substrate is loaded into the MOCVD reactor. The sapphire substrate is heated and etching gas is injected into the MOCVD reactor. NH3 gas is injected into the MOCVD reactor to nitrify the surface of the sapphire substrate. A nitride semiconductor layer is grown on the nitrified sapphire substrate. By surface-reforming the sapphire substrate and then growing the nitride semiconductor layer on the surface-reformed sapphire substrate via MOCVD without formation of a low temperature buffer layer, an excellent nitride semiconductor structure can be realized. In this circumstance, the nitride semiconductor layer for example of GaN can be grown effectively on the surface-treated sapphire substrate because GaN deposition occurs on the sapphire substrate while it is etched.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: March 28, 2006
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sun Woon Kim, In Eung Kim, Hun Joo Hahm, Soo Min Lee, Dong Joon Kim, Je Won Kim
  • Patent number: 6946369
    Abstract: The invention concerns a method for forming nanostructures of semi-conductor material on a substrate of dielectric material by chemical vapour deposition (CVD). Said method comprises the following steps: a step of forming on the substrate (12) stable nuclei (14) of a first semi-conductor material in the form of islands, by CVD from a precursor (11) of the first semi-conductor material chosen so that the dielectric material (12) accepts the formation of said nuclei (14), a step of forming nanostructures (16A, 16B) of a second semi-conductor material from the stable nuclei (14) of the first semi-conductor material, by CVD from a precursor (21) chosen to generate a selective deposition of the second semi-conductor material only on said nuclei (14). The invention further concerns nanostructures formed according to one of said methods as well as devices comprising said nanostructures.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: September 20, 2005
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Frédéric Mazen, Thierry Baron, Jean-Michel Hartmann, Marie-Noelle Semeria
  • Patent number: 6911376
    Abstract: A process, which includes implanting hydrogen ions into a silicon substrate, overlaying the silicon substrate on to a support substrate, and applying a flash anneal heat treatment to the silicon and support substrates to cause the silicon substrates to separate at a region defined by the implanted hydrogen ions.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: June 28, 2005
    Assignee: WaferMasters
    Inventor: Woo Sik Yoo
  • Patent number: 6865798
    Abstract: A method for shaping an ABS of a magnetic head slider including a step of holding at least one row bar with a plurality of aligned thin-film magnetic head elements by adhering a first surface of the at least one row bar to an adhesive or UV tape capable of passing a laser beam there through, the first surface being opposite an ABS of the at least one row bar, a step of shaping the ABS of the at least one row bar in a convex shape by radiating a laser beam to the first surface of the at least one row bar through the adhesive or UV tape, a step of cutting the at least one row bar into individual magnetic head sliders, and a step of then, removing the magnetic head sliders from the adhesive or UV tape after weakening adhesion properties of the adhesive or UV tape.
    Type: Grant
    Filed: May 14, 2002
    Date of Patent: March 15, 2005
    Assignee: SAE Magnetics (H.K.) Ltd.
    Inventor: Osamu Fukuroi
  • Publication number: 20040115853
    Abstract: A method of forming a light emitting device includes providing a sapphire substrate, growing an Al1−xGaxN first layer by vapor deposition on the substrate at a temperature between about 1000° C. and about 1180° C., and growing a III-nitride second layer overlying the first layer. The first layer may have a thickness between about 500 angstroms and about 5000 angstroms. In some embodiments, reaction between the group V precursor and the substrate is reduced by starting with a low molar ratio of group V precursor to group III precursor, then increasing the ratio during growth of the first layer, or by using nitrogen as an ambient gas.
    Type: Application
    Filed: December 11, 2002
    Publication date: June 17, 2004
    Inventors: Junko Kobayashi, Werner K. Goetz
  • Patent number: 6743651
    Abstract: A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate is provided by implanting oxygen into a Si/SiGe multilayer heterostructure which comprises alternating Si and SiGe layers. Specifically, the high quality, relaxed SiGe-on-insulator is formed by implanting oxygen ions into a multilayer heterostructure which includes alternating layers of Si and SiGe. Following, the implanting step, the multilayer heterostructure containing implanted oxygen ions is annealed, i.e., heated, so as to form a buried oxide region predominately within one of the Si layers of the multilayer structure.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: June 1, 2004
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Feng-Yi Huang, Steven J. Koester, Devendra K. Sadana
  • Publication number: 20040072382
    Abstract: A method of separating two layers of material from one another in such a way that the two separated layers of material are essentially fully preserved. An interface between the two layers of material at which the layers of material are to be separated, or a region in the vicinity of the interface, is exposed to electromagnetic radiation through one of the two layers of material. The electromagnetic radiation is absorbed at the interface or in the region in the vicinity of the interface and the absorbed radiation energy induces a decomposition of material at the interface.
    Type: Application
    Filed: September 29, 2003
    Publication date: April 15, 2004
    Applicant: Siemens Aktiengesellschaft
    Inventors: Michael kelly, Oliver Ambacher, Martin Stutzmann, Martin Brandt, Roman Dimitrov, Robert Handschuh
  • Publication number: 20040053478
    Abstract: An epitaxial growth system comprises a housing around an epitaxial growth chamber. A substrate support is located within the growth chamber. A gallium source introduces gallium into the growth chamber and directs the gallium towards the substrate. An activated nitrogen source introduces activated nitrogen into the growth chamber and directs the activated nitrogen towards the substrate. The activated nitrogen comprises ionic nitrogen species and atomic nitrogen species. An external magnet and/or an exit aperture control the amount of atomic nitrogen species and ionic nitrogen species reaching the substrate.
    Type: Application
    Filed: June 30, 2003
    Publication date: March 18, 2004
    Inventor: Theodore D. Moustakas
  • Patent number: 6558994
    Abstract: A silicon-on-insulator semiconductor device and manufacturing method therefor is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.
    Type: Grant
    Filed: March 1, 2001
    Date of Patent: May 6, 2003
    Assignee: Chartered Semiconductors Maufacturing Ltd.
    Inventors: Randall Cher Liang Cha, Yeow Kheng Lim, Alex See, Tae Jong Lee, Wang Ling Goh
  • Patent number: 6498371
    Abstract: An SOI CMOS inverter circuit in which a silicide layer in combination with body tie regions tie a p-type body region and an n-type body region together. At the same time, however, the body regions remain floating electrically so that the benefits of SOI are maintained. The silicide layer permits excess carriers to be recombined via the respective body regions so that the body region potential does not get modulated by generation/recombination effects. Thus, a hysteresis effect in the inverter circuit will be reduced.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: December 24, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Srinath Krishnan, Jerry G. Fossum, Meng-Hsueh Chiang
  • Patent number: 6429099
    Abstract: A method and semiconductor structure are provided for implementing body contacts for semiconductor-on-insulator transistors. A bulk semiconductor substrate is provided. A mask is applied to the bulk semiconductor substrate to block an insulating implant layer in selected regions. The selected regions provide for body contact for transistors. Holes are formed extending into the bulk semiconductor substrate. The holes are filled with an electrically conductive material to create stud contacts to the bulk semiconductor substrate. In the preferred embodiment, the semiconductor-on-insulator is silicon on an oxide insulating layer and the invention provides a body contact for SOI transistors.
    Type: Grant
    Filed: January 5, 2000
    Date of Patent: August 6, 2002
    Assignee: International Business Machines Corporation
    Inventors: Todd Alan Christensen, John Edward Sheets, II
  • Patent number: 6417075
    Abstract: The present invention relates to a method of producing very thin substrate layers, particularly thin semiconductor areas, which may comprise integrated circuits. In the method two substrates (1, 2) are bonded by their faces via one or several intermediate connecting layers (3, 4). At least one of the bonding layers or the face of one of the substrates is structured before in such a way that channel-shaped recesses (5) are formed which permit a lateral penetration of an etching agent. The resulting wafer stack is thinned from one side down to the desired thickness of the layer. Finally, this thin layer is detached from the remaining substrate by introduction of the etching agent into the channel-shaped recesses. This detaching process is a low-price wet chemical process that does not expose the chip and the added value integrated thereon to any risk.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: July 9, 2002
    Assignee: Fraunhofer-Gesellschaft zur Forderung der Angewandten Forschung e.V.
    Inventors: Karl Haberger, Andreas Plettner
  • Patent number: 6403447
    Abstract: A method for forming a semiconductor substrate is provided including the general sequential steps of: providing a handle wafer and a device wafer; implanting at least a first impurity region in a first surface of the device wafer; bonding the first surface of the device wafer to a first surface of the handle wafer having a silicon dioxide layer; removing a portion of the device wafer at a second surface; and forming an epitaxial silicon layer on the second surface of the device wafer. The process enables the thickness of the device wafer to be minimal.
    Type: Grant
    Filed: July 7, 1999
    Date of Patent: June 11, 2002
    Assignee: Elantec Semiconductor, Inc.
    Inventor: Sameer Parab
  • Patent number: 6403388
    Abstract: A system and method provides for effective analysis of an integrated circuit having silicon on insulator (SOI) structure. According to one example embodiment of the present invention, the system includes a system (e.g., a nanomachining arrangement) adapted to remove a selected portion of the backside of a semiconductor device having SOI structure, and to electrically isolate a selected portion of circuitry on the SOI semiconductor device circuitry side. The isolated circuitry then is analyzed.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: June 11, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jeffrey D. Birdsley, Michael R. Bruce, Brennan V. Davis, Rosalinda M. Ring, Daniel L. Stone
  • Publication number: 20020068469
    Abstract: An improved semiconductor device and method for making it. That semiconductor device includes a first insulating layer, having a low-k dielectric constant that preferably comprises a carbon doped oxide, that is formed on a substrate. The device further includes a second layer, which is formed on the first layer, that has a relatively high dielectric constant and superior mechanical strength. The second layer is preferably under compressive stress. A third layer may be formed on the second layer, which has a relatively low dielectric constant and relatively poor mechanical strength, and a fourth layer may be formed on the third layer, which has a relatively high dielectric constant and superior mechanical strength.
    Type: Application
    Filed: January 2, 2002
    Publication date: June 6, 2002
    Inventors: Ebrahim Andideh, Qing Ma, Quan Tran, Steve Towle
  • Patent number: 6383924
    Abstract: A plurality of buried conductors and/or buried plate patterns formed within a monocrystalline substrate is disclosed. A plurality of empty-spaced buried patterns are formed by drilling holes in the monocrystalline substrate and annealing the monocrystalline substrate to form empty-spaced patterns of various geometries. The empty-spaced patterns are then connected through vias with surfaces of the monocrystalline substrate. The empty-spaced patterns and their respective vias are subsequently filled with conductive materials.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: May 7, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Paul A. Farrar, Joseph Geusic
  • Publication number: 20020016046
    Abstract: An ion implantation system for producing silicon wafers having relatively low defect densities, e.g., below about 1×106/cm2, includes a fluid port in the ion implantation chamber for introducing a background gas into the chamber during the ion implantation process. The introduced gas, such as water vapor, reduces the defect density of the top silicon layer that is separated from the buried silicon dioxide layer.
    Type: Application
    Filed: June 19, 2001
    Publication date: February 7, 2002
    Inventors: Robert Dolan, Bernhard Cordts, Marvin Farley, Geoffrey Ryding
  • Publication number: 20010026950
    Abstract: In a method of manufacturing a semiconductor device by using a sapphire substrate, a nitrogen-based semiconductor thick film is deposited on the sapphire substrate by VPE and is left without any cracks by etching the sapphire substrate by an etchant. The nitrogen-based semiconductor thick film serves as a substrate for manufacturing the semiconductor device.
    Type: Application
    Filed: March 29, 2001
    Publication date: October 4, 2001
    Applicant: NEC Corporation
    Inventors: Haruo Sunakawa, Akira Usui
  • Patent number: 6287941
    Abstract: A method for treating a film of material, which can be defined on a substrate, e.g., silicon. The method includes providing a substrate comprising a cleaved surface, which is characterized by a predetermined surface roughness value. The substrate also has a distribution of hydrogen bearing particles defined from the cleaved surface to a region underlying said cleaved surface. The method also includes increasing a temperature of the cleaved surface to greater than about 1,000 Degrees Celsius while maintaining the cleaved surface in an etchant bearing environment to reduce the predetermined surface roughness value by about fifty percent and greater. Preferably, the value can be reduced by about eighty or ninety percent and greater, depending upon the embodiment.
    Type: Grant
    Filed: September 20, 1999
    Date of Patent: September 11, 2001
    Assignee: Silicon Genesis Corporation
    Inventors: Sien G. Kang, Igor J. Malik
  • Patent number: 6235611
    Abstract: An improved method for making silicon-on-sapphire transducers including the steps of: forming a first silicon layer on a first side of a first sapphire wafer; bonding a second sapphire wafer to the first side of the first sapphire wafer such that the first silicon layer is interposed between the first and second sapphire wafers; reducing the thickness of the first sapphire wafer to a predetermined thickness; depositing a second silicon layer on a second surface of the first sapphire wafer, wherein the second surface of the first sapphire wafer is oppositely disposed from the first surface of the first sapphire wafer; bonding a silicon wafer to the second surface of the first sapphire wafer such that the second silicon layer is interposed between the first sapphire wafer and the silicon wafer, wherein the silicon wafer includes p+ regions indicative of a transducer structure and non-p+ regions; and, removing the non-p+ regions of the silicon wafer thus forming the transducer structure of p+
    Type: Grant
    Filed: January 12, 1999
    Date of Patent: May 22, 2001
    Assignee: Kulite Semiconductor Products Inc.
    Inventors: Anthony D. Kurtz, Alexander A. Ned
  • Patent number: 6136666
    Abstract: Disclosed is a method for fabricating a silicon-on-insulator wafer, particularly to a cost reductive method.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: October 24, 2000
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Sang Mun So
  • Patent number: 6127244
    Abstract: A method of fabricating a SOI wafer using an isolation film as a polishing stopper, comprising the steps of: preparing a first and a second silicon substrates; implanting impurities into selected active regions of the first silicon substrate to a desired depth; etching the portion of the silicon substrate between the active regions to forming trenches having a desired depth; forming a first insulating layer of an oxide film on the first silicon substrate to be filled in the trenches; etching-back the first insulating layer to form a trench type isolation film; forming a second insulating layer of an oxide film on the first silicon substrate including the isolation film; bonding the first and the second silicon substrates to contact the second insulating layer with the second silicon substrate; firstly polishing the first silicon substrate by the vicinity of the portion of the first silicon substrate where the impurities are implanted; etching the polished first silicon substrate by using an etchant until the
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: October 3, 2000
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Seong Eun Lee
  • Patent number: 6100106
    Abstract: A process for producing a semiconductor light-emitting device, which comprises forming, on a substrate by crystal growth, a gallium nitride type compound semiconductor layer having a crystal face (0,0,0,1) which can be utilized as the end surface of an optical waveguide or as a cavity mirror surface.
    Type: Grant
    Filed: November 17, 1998
    Date of Patent: August 8, 2000
    Assignee: NEC Corporation
    Inventors: Atsushi Yamaguchi, Akitaka Kimura, Chiaki Sasaoka
  • Patent number: 6033490
    Abstract: In a method of manufacturing a semiconductor device which includes a quartz substrate having a z-cut plane of (0001) plane on a surface, a GaN film is first deposited on the surface. Finally, the quartz substrate is removed from the GaN film. The removed GaN film is used as a real substrate for forming GaN based compound semiconductor layers thereon.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: March 7, 2000
    Assignee: NEC Corporation
    Inventors: Akitaka Kimura, Chiaki Sasaoka, Koichi Izumi
  • Patent number: 5985728
    Abstract: A silicon on insulator (SOI) process is disclosed which includes the steps of forming an etch stop layer in a starting wafer, forming an insulating layer on the etch stop layer, bonding this wafer to a handle wafer, thinning the start wafer down to the etch stop and then recovering a device layer from the etch stop layer by outgassing dopants from the etch stop layer.
    Type: Grant
    Filed: September 1, 1995
    Date of Patent: November 16, 1999
    Assignee: Elantec Semiconductor, Inc.
    Inventor: Dean Jennings
  • Patent number: 5985687
    Abstract: Optically flat cleaved facet mirrors are fabricated in GaN epitaxial films grown on sapphire by wafer fusing a GaN film with a sapphire substrate to a cubic substrate such as an InP or GaAs substrate. The sapphire substrate may then partially or entirely removed by lapping, dry etching, or wet etching away a sacrificial layer disposed in the interface between the sapphire substrate and the GaN layer. Thereafter, the cubic InP or GaN substrate is cleaved to produce the cubic crystal facet parallel to the GaN layer in which active devices are fabricated for use in lasers, photodetectors, light emitting diodes and other optoelectronic devices.
    Type: Grant
    Filed: April 12, 1996
    Date of Patent: November 16, 1999
    Assignee: The Regents of the University of California
    Inventors: John E. Bowers, R. Kehl Sink, Steven P. Denbaars
  • Patent number: 5932048
    Abstract: A method of direct-bonding semiconductor wafers limits the time interval between a bonding step and a bonding anneal step or performs a baking step between the bonding and bonding anneal steps at a predetermined temperature for a predetermined time interval to prevent the formulation of voids on the edge regions of the wafers. The method for fabricating laminated semiconductor wafers includes a bonding step to fit together two polished semiconductor wafers by bonding jigs, and a succeeding bonding anneal step to laminate the wafers. In the method the bonding anneal step is preferably carried out within an hour following the bonding step; or a baking step at a predetermined temperature for a predetermined time interval is carried out between the bonding step and the bonding anneal step. Further, the method can prevent heavy metal impurities attached to the surface of the wafer from diffusing into the wafer by baking the wafer for over 5 minutes at above 100.degree. C.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: August 3, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hiroshi Furukawa, Hirotaka Kato, Hiroaki Yamamoto, Kazuaki Fujimoto
  • Patent number: 5879970
    Abstract: Polycrystalline silicon-germanium alloy is grown on a glass substrate through a chemical vapor deposition under the conditions where the substrate temperature ranges from 350 degrees to 450 degrees in centigrade, the ratio between gas flow rate of Si.sub.2 H.sub.6 and the gas flow rate of GeF.sub.4 ranges from 20:0.9 to 40:0.9 and the dilution gas is selected from the group consisting of helium, argon, nitrogen and hydrogen, and the composition ratio of silicon of the polycrystalline silicon-germanium is equal to or greater than 80 percent so that the carrier mobility is drastically improved.
    Type: Grant
    Filed: September 3, 1997
    Date of Patent: March 9, 1999
    Assignee: NEC Corporation
    Inventors: Kunihiko Shiota, Jun-ichi Hanna
  • Patent number: 5879960
    Abstract: A thin film diode (8) between a data line (12) and a drive electrode (13), which is free from breakage in an upper layer film (4), is formed on one inner surface of a glass substrate (1) sealing a liquid crystal of a liquid crystal display device. To form such a thin film diode, a lower layer film (2) is formed on the glass substrate (1) such that the lower layer film (2) overlaps with the upper layer film (4) and the lower layer film (2) has a plurality of differences in level. An insulating film (3) is formed by oxidizing the surface of the lower layer film (2) with an anodic oxidation technique. The upper layer film (4) is formed, thereby completing the thin film diode. Alternately, an insulating film material (7, 7') may be formed either on the lower layer film (2) or on the peripheral region thereof in the form of a film, and the insulating film (3) may be formed by oxidizing the insulating film material (7, 7').
    Type: Grant
    Filed: August 13, 1997
    Date of Patent: March 9, 1999
    Assignee: Citizen Watch Co., Ltd.
    Inventor: Kozo Miyoshi
  • Patent number: 5840593
    Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
    Type: Grant
    Filed: March 10, 1997
    Date of Patent: November 24, 1998
    Assignee: Elm Technology Corporation
    Inventor: Glenn Joseph Leedy
  • Patent number: 5776803
    Abstract: A method of manufacturing a large-area electronic device such as a flat panel display, which method includes subjecting a semiconductor film on a polymer substrate to an energy beam treatment, e.g., for crystal growth or to anneal an ion implant, and masking the substrate prior to treatment to prevent exposure to the energy beam, wherein the adhesion of the film and other layers on the substrate is improved by first heating the substrate to pre-shrink it, and then depositing the layers on the pre-shrunk substrate at a lower temperature than the heating temperature.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: July 7, 1998
    Assignee: U.S. Philips Corporation
    Inventor: Nigel D. Young
  • Patent number: 5736439
    Abstract: A semiconductor device and a method for forming the same. The semiconductor device comprises an insulating or semiconductor substrate, a thermally-contractive insulating film which is formed on said substrate and provided with grooves, and a semiconductor film which is formed on the thermally-contractive insulating film and divided in an islandish form through the grooves. The thermally-contractive insulating film is contracted in a heat process after the semiconductor film is formed.
    Type: Grant
    Filed: June 20, 1996
    Date of Patent: April 7, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuhiko Takemura