Abstract: A semiconductor structure can be created by forming an insulator layer over a surface of a substrate. An intermediate layer can be formed on top of the insulator layer, wherein openings in the intermediate layer may expose regions of the insulator. Openings may be formed in the exposed regions of the insulator layer to create exposed areas of the substrate. A first element of a multi-element semiconductor can be deposited onto the exposed regions of the insulator layer, into the openings in the exposed regions of the insulator layer, and onto the exposed areas of the substrate. A capping layer can be formed over the first element of the multi-element semiconductor. The first element can be melted. A liquid solution can be created by dissolving a second element of the multi-element semiconductor into first element. A multi-element semiconductor, seeded off the substrate, can be formed from the liquid solution.

Abstract: A method for fabricating a MTJ cell of a magnetic random access memory (MRAM) using a semiconductor film as a tunnel barrier layer is disclosed. The method comprises the steps of: forming a pinned ferromagnetic layer on a connection layer; forming a tunnel barrier layer using a semiconductor film on the pinned ferromagnetic layer; and forming a free ferromagnetic layer on the tunnel barrier layer.

Abstract: An atomic layer deposition (ALD) method employing Si2Cl6 and NH3, or Si2Cl6 and activated NH3 as reactants. In one embodiment, the invention includes the steps of (a) placing a substrate into a chamber, (b) injecting a first reactant containing Si2Cl6 into the chamber, (c) chemisorbing a first portion of the first reactant onto the substrate and physisorbing a second portion of the first reactant onto the substrate, d) removing the non-chemically absorbed portion of the first reactant from the chamber, (e) injecting a second reactant including NH3 into the chamber, (f) chemically reacting a first portion of the second reactant with the chemisorbed first portion of the first reactant to form a silicon-containing solid on the substrate, and (g) removing the unreacted portion of the second reactant from the chamber. In other embodiments, the first reactant can contain two or more compounds containing Si and Cl, such as Si2Cl6 and SiCl4.

Abstract: An oxidation process for reducing the data retention loss (DRL) in a FAMOS device comprising the steps of (1) low temperature deposition of a silicon-enriched silicon oxide (130) over a FAMOS transistor gate stack (116) and (2) annealing said silicon-enriched oxide (130) at a high temperature in oxygen atmosphere to convert said silicon-enriched oxide (130) to a thermal oxide. The silicon enriched oxide (130) acts as both an oxygen getter and diffusion barrier during the annealing step.

Abstract: A method of growing a p-type doped Group II-VI semiconductor film includes the steps of forming a lattice comprising a Group II material and a Group VI material wherein a cation-rich condition is established at a surface of the lattice. The method further includes the steps of generating an elemental Group V flux by evaporating an elemental Group V material and providing the elemental Group V flux to a Group VI sublattice of the lattice.

Abstract: An object of the invention is to provide a method for the heat treatment of II-VI semiconductors such as ZnS, ZnS.sub.x Se.sub.1-x, Zn.sub.y Cd.sub.1-y Se, etc. to dope with Group III elements as a donor impurity to reduce its resistivity. This object can be attained by a method for the heat treatment of II-VI semiconductors in a closed vessel, which comprises forming a film of a Group III element as a donor impurity or a Group III element-containing compound on a surface of single crystal of II-VI semiconductors, then charging the single crystal and a Group II element for constituting the single crystal in the closed vessel and heating them in such a manner that the both are not contacted with each other.