Abstract: An anti-fuse having two electrical connections is constructed by adding at least one zener diode and resistor to a power MOSFET. When the voltage across the two electrical connections exceeds the zener diode voltage and the maximum gate voltage of the MOSFET, the MOSFET burns out. This shorts out the device which can be used to bypass an LED or other load when that load burns out and forms an open circuit.

Abstract: A transient voltage suppression device includes: a substrate; a first conductive type well region including a first well and a second well; a second conductive type well region including a third well and a fourth well, the third well being disposed between the first well and the second well so as to isolate the first well and the second well, and the second well being disposed between the third well and the fourth well; a zener diode active region; a first doped region, provided in the first well; a second doped region, provided in the first well; a third doped region, provided in the second well; a fourth doped region, provided in the second well; a fifth doped region, provided in the zener diode active region; and a sixth doped region, provided in the zener diode active region.

Abstract: A silicon-controlled rectifier includes a substrate of a first conductivity type; a deep well region of a second conductivity type; a well regions of the first conductivity type and the second conductivity type; a first, second and third heavily doped active regions of the first conductivity type; a first, second and third heavily doped active regions of the second conductivity type; and a first, second and third shallow trench isolation structures. A reverse diode formed in the third heavily doped active region of the second conductivity type and the well region of the first conductivity type is embedded, and a forward diode is formed in the heavily doped active region of the first conductivity type and the well region of the second conductivity type. By sharing the third heavily doped active region of the second conductivity type across the well regions of different conductivity types, two back-to-back diodes are formed.

Abstract: An asymmetrical bidirectional protection component formed in a semiconductor substrate of a first conductivity type, including: a first implanted area of the first conductivity type; a first epitaxial layer of the second conductivity type on the substrate and the first implanted area; a second epitaxial layer of the second conductivity type on the first epitaxial layer, the second layer having a doping level different from that of the first layer; a second area of the first conductivity type on the outer surface of the epitaxial layer, opposite to the first area; a first metallization covering the entire lower surface of the substrate; and a second metallization covering the second area.

Abstract: In one embodiment, electrostatic discharge (ESD) devices are disclosed.

Abstract: A semiconductor device including a semiconductor substrate having a first conductive type layer; a first diffusion region which has the first conductive type and is formed in the first conductive type layer; a second diffusion region which has a second conductive type and an area larger than an area of the first diffusion region and overlaps the first diffusion region; and a PN junction formed at an interface between the first and the second diffusion regions. The second diffusion region includes a ring shaped structure or a guard ring includes an inverted region which has the second conductive type. According to such a configuration, it is possible to provide a semiconductor device having the required Zener characteristics with good controllability.

Abstract: A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.

Abstract: Some embodiments include methods of forming diodes. The methods may include oxidation of an upper surface of a conductive electrode to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of an oxidizable material over a conductive electrode, and subsequent oxidation of the oxidizable material to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of a metal halide layer over a conductive electrode. Some embodiments include diodes that contain a metal halide layer between a pair of diode electrodes.

Abstract: Electrostatic discharge (ESD) protection clamps (61, 95) for I/O terminals (22, 23) of integrated circuit (IC) cores (24) comprise a bipolar transistor (25) with an integrated Zener diode (30) coupled between the base (28) and collector (27) of the transistor (25). Prior art variations (311, 312, 313, 314) in clamp voltage in different parts of the same IC chip or wafer caused by prior art deep implant geometric mask shadowing are avoided by using shallow implants (781, 782) and forming the base (28, 68) coupled anode (301, 75) and collector (27, 70, 64) coupled cathode (302, 72) of the Zener (30) using opposed edges (713, 714) of a single relatively thin mask (71, 71?). The anode (301, 75) and cathode (302, 72) are self-aligned and the width (691) of the Zener space charge region (69) therebetween is defined by the opposed edges (713, 714) substantially independent of location and orientation of the ESD clamps (61, 95) on the die or wafer.

Abstract: In one embodiment, a two terminal multi-channel ESD device is configured to include a zener diode and a plurality of P-N diodes. In another embodiment, the ESD devices has an asymmetrical, characteristic.

Abstract: In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.

Abstract: In one embodiment, a two terminal multi-channel ESD device is configured to include a zener diode and a plurality of P-N diodes.

Abstract: In one embodiment, a bi-directional diode structure is formed to have a substantially symmetrical current-voltage characteristic.

Abstract: A semiconductor laser apparatus has a Zener diode containing a first semiconductor region of a first conduction type and a second semiconductor region of a second conduction type joined with the first semiconductor region, and a vertical-cavity surface-emitting semiconductor laser diode stacked above the Zener diode and containing at least a first mirror layer of a first conduction type, a second mirror layer of a second conduction type and an active region sandwiched between the first and second mirror layers. The first semiconductor region and the second mirror layer are electrically connected and the second semiconductor region and the first mirror layer are electrically connected.

Abstract: Some embodiments include methods of forming diodes. The methods may include oxidation of an upper surface of a conductive electrode to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of an oxidizable material over a conductive electrode, and subsequent oxidation of the oxidizable material to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of a metal halide layer over a conductive electrode. Some embodiments include diodes that contain a metal halide layer between a pair of diode electrodes.

Abstract: A semiconductor device includes a semiconductor substrate, a cell region, an outer peripheral region, a field plate, an outermost peripheral ring, outer peripheral region layer, an insulator film, and a Zener diode. The semiconductor substrate has a superjunction structure. The outer peripheral region is disposed at an outer periphery of the cell region. The Zener diode is disposed on the insulator film for electrically connecting the field plate with the outermost peripheral ring. The Zener diode has a first conductivity type region and a second conductivity type region that are alternately arranged in a direction from the cell region to the outer peripheral region.

Abstract: Some embodiments include methods of forming diodes. The methods may include oxidation of an upper surface of a conductive electrode to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of an oxidizable material over a conductive electrode, and subsequent oxidation of the oxidizable material to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of a metal halide layer over a conductive electrode. Some embodiments include diodes that contain a metal halide layer between a pair of diode electrodes.

Abstract: Disclosed are a light emitting device having a zener diode therein and a method of fabricating the light emitting device. The light emitting device comprises a P-type silicon substrate having a zener diode region and a light emitting diode region. A first N-type compound semiconductor layer is contacted to the zener diode region of the P-type silicon substrate to exhibit characteristics of a zener diode together with the P-type silicon substrate. Further, a second N-type compound semiconductor layer is positioned on the light emitting diode region of the P-type silicon substrate. The second N-type compound semiconductor layer is spaced apart from the first N-type compound semiconductor layer. Meanwhile, a P-type compound semiconductor layer is positioned on the second N-type compound semiconductor layer, and an active layer is interposed between the second N-type compound semiconductor layer and the P-type compound semiconductor layer.

Abstract: A positive-intrinsic-negative (PIN)/negative-intrinsic-positive (NIP) diode includes a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate is of a first conductivity. The PIN/NIP diode includes at least one trench formed in the first main surface which defines at least one mesa. The trench extends to a first depth position in the semiconductor substrate. The PIN/NIP diode includes a first anode/cathode layer proximate the first main surface and the sidewalls and the bottom of the trench. The first anode/cathode layer is of a second conductivity opposite to the first conductivity. The PIN/NIP diode includes a second anode/cathode layer proximate the second main surface, a first passivation material lining the trench and a second passivation material lining the mesa. The second anode/cathode layer is the first conductivity.

Abstract: In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.

Abstract: In one embodiment, an ESD device is configured to include a zener diode and a P-N diode.

Abstract: In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.

Abstract: A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth semiconductor region (140, 340) above the third semiconductor region, a fifth semiconductor region (150, 350) above the second semiconductor region and at least partially contiguous with the fourth semiconductor region, a sixth semiconductor region (160, 360) above and electrically shorted to the fifth semiconductor region, and an electrically insulating layer (180, 380) above the fourth semiconductor region and the fifth semiconductor region. A junction (145, 345) between the fourth semiconductor region and the fifth semiconductor region forms a zener diode junction, which is located only underneath the electrically insulating layer. In one embodiment, a seventh semiconductor region (170) circumscribes the third, fourth, fifth, and sixth semiconductor regions.

Abstract: Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) antifuse transistor serves as an electrically-programmable antifuse. In its unprogrammed state, the antifuse transistor is off and has a relatively high resistance. During programming, the antifuse transistor is turned on which melts the underlying silicon and causes a permanent reduction in the transistor's resistance. A sensing circuit monitors the resistance of the antifuse transistor and supplies a high or low output signal accordingly. The antifuse transistor may be turned on during programming by raising the voltage at its substrate relative to its source. The substrate may be connected to ground through a resistor. The substrate may be biased by causing current to flow through the resistor. Current may be made to flow through the resistor by inducing avalanche breakdown of the drain-substrate junction or by producing Zener breakdown of external Zener diode circuitry connected to the resistor.

Abstract: A manufacturing technique for a zener diode which includes forming a first semiconductor region in a region such as a well region at a primary face of a semiconductor substrate and then forming a second semiconductor region of opposite conductivity type thereover. The second semiconductor region covers an area greater than the underlying first semiconductor region. The method further calls for forming an insulating film on the primary face of the substrate followed by the forming connection holes in the insulating film to expose an upper part of the second semiconductor region located outside the area covered by the junction affected between the first and second semiconductor regions. This is followed by the formation of a wire at the upper part of the insulating film in which an electrical connection is affected between the wire and the second semiconductor region through the plural connection holes which are distributively arranged.

Abstract: In an avalanche structure, different breakdown voltages are achieved by making use of a polygate and forming a highly doped p-n junction beneath the polygate, and adjusting the gate length and optionally the bias voltage of the gate.

Abstract: A process for fabricating Zener diodes that does not require the use of photomasks. An oxide layer is grown on a silicon substrate which is doped with an N-type dopant. The substrate is subsequently implanted with a P-type dopant, forming a PN junction. The substrate is then metallized for connecting the Zener diode to other circuit components. Advantageously, the substrate may be scribed after processing, before processing, or anytime during processing. Back-to-back Zener diodes formed in this manner are used as shunt circuits across individual lamp sockets in series-wired Christmas light strings to maintain current flow to each of the lamps of the light string when one or multiple lamps fail.

Abstract: Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) antifuse transistor serves as an electrically-programmable antifuse. In its unprogrammed state, the antifuse transistor is off and has a relatively high resistance. During programming, the antifuse transistor is turned on which melts the underlying silicon and causes a permanent reduction in the transistor's resistance. A sensing circuit monitors the resistance of the antifuse transistor and supplies a high or low output signal accordingly. The antifuse transistor may be turned on during programming by raising the voltage at its substrate relative to its source. The substrate may be connected to ground through a resistor. The substrate may be biased by causing current to flow through the resistor. Current may be made to flow through the resistor by inducing avalanche breakdown of the drain-substrate junction or by producing Zener breakdown of external Zener diode circuitry connected to the resistor.

Abstract: The present invention provides a diode 200 that includes a substrate 215 doped with a first type dopant and a double implanted guard ring 245 located within the substrate and doped with a second type dopant opposite the first type dopant and having a first doped profile region 245a and a second doped profile region 245b. The present invention also includes a method of manufacturing this diode and an integrated circuit that utilizes this diode 200 within a CMOS and bipolar transistor integrated circuit 600.

Abstract: A process for fabricating Zener diodes that does not require the use of photomasks. An oxide layer is grown on a silicon substrate which is doped with an N-type dopant. The substrate is subsequently implanted with a P-type dopant, forming a PN junction. The substrate is then metallized for connecting the Zener diode to other circuit components. Advantageously, the substrate may be scribed after processing, before processing, or anytime during processing. Back-to-back Zener diodes formed in this manner are used as shunt circuits across individual lamp sockets in series-wired Christmas light strings to maintain current flow to each of the lamps of the light string when one or multiple lamps fail.

Abstract: A single-electrode, push-pull semiconductor PIN Mach-Zehnder modulator (10) that includes first and second PIN devices (12, 14) on a substrate (16). Intrinsic layers (22, 28) of the devices (12, 14) are the active regions of two arms (50, 52) of a Mach-Zehnder interferometer. An outer electrode (38) is connected to the N layer (24) of the first PIN device (12) and a center electrode (40) is connected to the P layer (20) of the first PIN device (12). An outer electrode (42) is connected to the P layer (26) of the second PIN device (14) and the center electrode (40) is connected to the N layer (30) of the second PIN device (14). An RF modulation signal biases the PIN devices (12, 14) in opposite directions and causes the index refraction of the intrinsic layers (22, 28) to change in opposite directions to give a push-pull modulation effect.

Abstract: Interband tunnel diodes which are compatible with Si-based processes such as, but not limited to, CMOS and SiGe HBT fabrication. Interband tunnel diodes are disclosed (i) with spacer layers surrounding a tunnel barrier; (ii) with a quantum well adjacent to, but not necessarily in contact with, one of the injectors, and (iii) with a first quantum well adjacent to, but not necessarily in contact with, the bottom injector and a second quantum well adjacent to, but not necessarily in contact with, the top injector. Process parameters include temperature process for growth, deposition or conversion of the tunnel diode and subsequent thermal cycling which to improve device benchmarks such as peak current density and the peak-to-valley current ratio.

Abstract: An ESD protection circuit protects integrated circuits having multiple power supply voltage sources from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage sources. The ESD protection circuit has a string of serially connected lateral polycrystalline silicon diodes characterized by consistent turn-on threshold voltage level such that as the number of stage of the ESD protection circuit increase, the turn-on voltage threshold of the ESD protection circuit increase linearly.

Abstract: An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resistor can turn on the transistor. The zener diode is formed in series with the resistor and extends between the base and collector regions of the transistor. Thus configured, breakdown current through the zener diode, typically in response to an ESD event, turns on the transistor to provide a nondestructive discharge path for the ESD. The zener diode includes anode and cathode diffusions. The cathode diffusion extends down into the semiconductor substrate in a direction perpendicular to the substrate. The anode diffusion extends down through the cathode diffusion into the semiconductor substrate. The anode diffusion extends down further than the cathode diffusion so that the zener diode is arranged vertically with respect to the substrate.

Abstract: A zener diode is formed in a bipolar or BiCMOS fabrication process by modifying the existing masks that are used in the bipolar or BiCMOS fabrication process, thereby eliminating the need for a separate doping step. In addition, the reverse breakdown voltage of the zener diode is set to a desired value within a range of values by modifying the area of a new opening in one of existing masks.

Abstract: The specification describes a DMOS transistor that is fully integrated with an electrostatic protection diode (ESD). The ESD diode is isolated from the DMOS device by a trench. The trench is metallized to tie the guard ring of the ESD to the substrate thereby increasing the current handling capabilities of the ESD. The trench also provides a convenient buried contact to the RF ground.

Abstract: A method of fabricating a diode device, such as a PIN diode, includes forming top and bottom regions of opposite conductivity types and includes anisotropically etching into the top surface to form a pit having side walls that converge with approach to the bottom surface. However, the pit does not extend to the bottom surface. In the PIN diode embodiment, the pit terminates within an intrinsic region that separates a bottom surface diffusion region from a diffusion region along the walls of the anisotropically etched pit. The anisotropic etching approach provides a degree of self regulation with regard to the geometries of the pit. A process flow of steps is described, which allows thicker and larger diameter wafers to be used in the formation of an array of such diode device.

Abstract: A manufacturing process providing a zener diode formed in an N-type well housing a first N-type conductive region and having a doping level higher than the well, and a second P-type conductive region arranged contiguous to the first conductive region. The first conductive region is connected, through a third N-type conductive region having the same doping level as the first conductive region, to a conductive material layer overlying the gate oxide layer to be protected. The third conductive region, the well, and the substrate form an N+/N/P diode that protects the gate oxide layer during manufacture of the integrated device from the deposition of the polycrystalline silicon layer that forms the gate regions of the MOS elements.

Abstract: Implemented is a diode which controls an energy loss produced during a reverse recovery operation and generates an oscillation of an applied voltage with difficulty even if a reverse bias voltage has a great value. An N layer 101 and a P layer 102 are formed in a semiconductor substrate such as silicon. Furthermore, a cathode side P layer 103 is also formed facing a cathode electrode 105 in a position on the N layer 101 that a depletion layer extended during application of a reverse bias voltage does not reach. By providing the cathode side P layer 103, a current density of a reverse current obtained during a reverse recovery operation can be increased, the sudden change of a resistance component of a diode can be prevented and the generation of a voltage oscillation can be suppressed. The cathode side P layer 103 has a diameter W of approximately 400 &mgr;m or less and a rate of an area of the cathode side P layer 103 occupying a cathode surface is kept at approximately ⅖ or less.

Abstract: This invention relates to a technique of improving reverse recovery characteristic of a semiconductor device, and an object of the invention is to solve a technical problem of breakdown voltage reduction which has conventionally caused in enhancing soft recover.

Abstract: A structure of an ESD protection circuit device located under a pad, protecting an internal circuit and a method of manufacturing the same are disclosed. The ESD protection circuit device having a pad window, located under a pad, includes a semiconductor substrate having a P-well and an N well. The P-well and the N-well have an interface. A predetermined area, pad window is selected in the substrate. A first STI structure, a second STI structure and a third STI structure are formed in the substrate within the pad window. N-type doped regions are formed P-well and in the N-well. First p-type doped regions are formed in the P-well and in the N-well and second p-type doped regions are formed in the P-well and in the N-well. A first zener diode is formed in the N-well and a second zener diode is formed in the P-well.

Abstract: A diode for use in an under-the-hood automotive application has a TO 220 outline and consists of a diode die on a two piece lead frame which has a thick section to which the bottom of the die is soldered, and a thinner section which extends through a plastic housing as a connection tab and which has a forked end for easy connection to a node of a three phase bridge. The bottom of the thickened section is exposed through the insulation housing for easy connection to a d-c heat sink rail. The diode is particularly useful in applications greater than 2 KW.

Abstract: The present invention provides a semiconductor device embracing (a) a first semiconductor region defined by a first end surface, a second end surface opposing to the first end surface and a side boundary surface connecting the first and second end surfaces; (b) a second semiconductor region connected with the first semiconductor region at the second end surface; (c) a third semiconductor region connected with the first semiconductor region at the first end surface; and (d) a fourth semiconductor region having inner surface in contact with the side boundary surface and an impurity concentration lower than the first semiconductor region. The fourth semiconductor region surrounds the first semiconductor region, and is disposed between the second and third semiconductor regions. The first, second and fourth semiconductor regions are first conductivity-type, but the third semiconductor region is a second conductivity type.

Abstract: An improved semiconductor device and method which includes a zener diode and RC network combination that share common semiconductor mask steps during the fabrication process. A common N+ layer serves to provide both the separate N+ cathode regions of the zener diode and the separate bottom electrode N+ region of the capacitor. A common metal layer serves to provide separate electrical contacts to the N+ cathode regions of the zener diode and also provides a separate top metal electrode for the capacitor. The capacitor dielectric is comprised of silicon nitride. A silicon dioxide/silicon nitride insulation layer is formed between the top metal electrode of the capacitor and a resistive layer typically made from tantalum nitride.

Abstract: A cost-competitive, dense, CMOS compatible ZPROM memory array design and method of manufacture is disclosed. The method of manufacture includes a novel method for forming extremely thin diodes and thin strips of other materials such as conductors by using oxide spacers as an etching mask.

Abstract: A new method of fabricating a Flash EEPROM memory cell is achieved. Ions are optionally implanted into said semiconductor substrate to form threshold enhancement regions of the same type as the semiconductor substrate. A tunneling oxide is formed. A first conductive layer is deposited. An interpoly oxide layer is deposited. A second conductive layer is deposited. The second conductive layer, the interpoly oxide layer, the first conductive layer, and the tunneling oxide layer are patterned to form control gates and floating gates. Ions are implanted to form drain junctions. A mask protects the planned source junctions. The drain junctions are opposite type to the semiconductor substrate. Ions are implanted to form source junctions. A mask protects the drain junctions. The source junctions are opposite type to the semiconductor substrate. Ions are implanted to form channel stop junctions to complete the Flash EEPROM memory cells.

Abstract: In this invention a deep N-type wall is created surrounding an area that contains an ESD device, or circuit. The ESD device, or circuit, is connected to a chip pad and is first surrounded by a P+ guard ring. The P+ guard ring is then surrounded by the deep N-type wall to block excess current from an ESD event or voltage overshoot from reaching the internal circuitry. The deep N-type wall comprises an N+ diffusion within an N-well which is on top of a deep N-well. The height of the deep N-type wall is approximately 4 to 6 micrometers which provides a capability to absorb much of the current from an ESD event or voltage overshoot.

Abstract: A method for manufacturing a non-volatile EEPROM memory cell, and a memory cell structure provided by the method. The method comprises the steps of: forming a gate stack on the surface of a substrate; forming a first and a second active regions in the substrate so that the first and second active regions extend to a depth below the surface of the substrate and have a first impurity type and an impurity concentration; and implanting a pocket region of an opposite conductivity type to that of the first or second active region into the surface of the substrate adjacent to the first active region. The step of implanting a pocket region may performed by implanting substantially at an angle non-normal to the surface of the substrate.

Abstract: An integrated circuit with a passive component and an ESD device in accordance with the present invention has: a P substrate; an N+ buried layer implanted in the P substrate; a cathode coupled to the N+ buried layer with an N area formed between the cathode and the N+ buried layer; an anode coupled to the N+ buried layer with a P area formed between the anode and the N+ buried layer; and a first P+ buried layer implanted in the N+ buried layer and below the P area to form a Zener diode. In an alternative embodiment, the ESD device may be incorporated in an integrated circuit with an active component.

Abstract: The method in accordance with the present invention is compatible with conventional CMOS fabrication processes to form a zener diode and a lateral silicon controlled rectifier constituting an on-chip ESD protection circuit in a semiconductor substrate. The zener diode is composed of a p-type doped region and an n-type doped region, wherein one of the doped regions, formed by deep diffusing impurities from a doped polysilicon layer, is arranged between two adjacent well regions. During an ESD event, the zener diode incurs breakdown to lower the trigger voltage of the lateral SCR device to within a range of about 5-7 Volts to thereby discharge the ESD current prior to damage of an internal circuit being protected.