Abstract: A method for multi-mode autonomous selection demodulation is disclosed. The method includes the step of providing a receiver with demodulation circuitry (110-112) capable of demodulating a plurality of waveform modulation techniques. The method also includes the step of receiving a modulated information waveform and a preamble associated with the modulated information waveform. The method also includes the steps of matching the preamble against a predefined set of patterns corresponding to a plurality of modulation techniques at the receiver and identifying a corresponding demodulation technique. Additionally, the method configures the demodulation circuitry (110-112) to apply the corresponding demodulation technique to the modulated information waveform.

Abstract: A method for demodulating digital frequency modulation (FM) signals is disclosed. A group of complex-valued discrete-time FM signal samples is initially received. A corresponding first complex product for each of the complex-valued discrete-time FM signal samples is computed, and a corresponding second complex product for each of the first complex values of the complex-valued discrete-time FM signal samples is computed. Subsequently, an inverse tangent of the second complex products are computed to yield an angle for each of the second complex values, wherein each of the angles represents a second-order difference of a phase of the complex-valued discrete-time FM signal samples. Finally, a digital integration is performed to obtain a first-order difference of the phase of the complex-valued discrete-time FM signal samples.

Abstract: An FM demodulation circuit includes a phase conversion circuit which converts a frequency variation of an input signal into a phase variation and has a variable conversion characteristic, and a control current source circuit which outputs, when the level of the input signal drops lower than a predetermined level, control current to vary the conversion characteristic of the phase conversion circuit so that the demodulation sensitivity may be raised.

Abstract: For a possible simple structure, dispensing with ceramic filters, an FM demodulator for demodulating sound-FM signals comprises a controllable amplifier (1) which receives the sound signals converted to intermediate frequencies, said amplifier having a gain which is adjusted by means of an amplitude control circuit (4) and whose output signal is applied to the amplitude control circuit and to the phase-locked loop which supplies a demodulated sound signal in the locked-in state from its output, said phase-locked loop including a loop filter (7) which comprises a filter (8, 9, 10) of at least the second order with a pole at the frequency f=0, and a limit-detection circuit (13) which feeds back the operating frequency of the phase-locked loop to a predetermined frequency range when said phase-locked loop leaves this frequency range around a predeterminable nominal demodulation frequency, the amplitude control circuit (4) controlling the controllable amplifier (1) in dependence upon its output signal and a signa

Abstract: Apparatus and method for estimating the angle-modulation imposed on a transmitted Radio Frequency (RF) or Intermediate Frequency (IF) carrier. The method estimates angle-modulation when communications channels add distortions such as noise to transmitted signals. The system provides reconstituted frequency modulation from a feedforward demodulator. The goal is to reduce the modulation index of a desired signal and to employ a narrower band-pass filter that passes this signal while rejecting the distortion that accompanies it. A plurality of stages, 1 through M, exist within the system. Stages 2 through M contain the same components, although filter coefficients and alignment delays may differ from stage to stage. Stage 1 of the demodulator differs slightly from the remaining stages, since the only input required by Stage 1 is a complex envelope signal that contains both the desired signal and the distortion added by the channel.

Abstract: An integrated circuit includes a demodulator having delay circuitry and demodulation control circuitry that may be fully formed within a common integrated circuit. The delay circuitry receives an input signal and generates a delayed input signal. The demodulation control circuitry generates a demodulated output based upon the input signal and the delayed input signal that has a level that is proportional to, or a finction of, a period of a respective cycle of the input signal. The demodulation control circuitry includes pulse generation circuitry, pulse delay circuitry, pulse conversion circuitry and sampling circuitry. The pulse generation circuitry generates a signal pulse based upon the input signal and the delayed input signal with a duration that is proportional to at least one period of the input signal. The pulse delay circuitry generates a delayed signal pulse based upon the signal pulse.

Abstract: A wide bandwidth frequency discriminator circuit (200) employs a wide bandwidth limiting amplifier (202) to amplify the IF signal portion of a received RF signal. A frequency-to-voltage circuit 208 is provided having a bandwidth substantially greater than the bandwidth of the IF signal. This discriminator (200) operates to form a detection system capable of discriminating between desired and undesired components of the received RF signal even when said desired and undesired components are nearly identical in amplitude. This is due in part to the enhanced frequency response provided by the discriminator (200).

Abstract: An receiver receives, amplifies, filters, and downconverts an RF signal to obtain an FM signal. The FM signal is then limited by a limiter and sampled by an ADC. The FM samples from the ADC are provided to an edge detector which detects transitions in the FM samples. The transitions correspond to zero crossings in the FM signal. The time period between the zero crossings, or the cycle width, is measured with a counter to determine the instantaneous frequency f.sub.c of the FM signal. The demodulated output is proportional to the instantaneous frequency which can be determined from the measured cycle periods as f.sub.c =1/2T.sub.c, f.sub.c .apprxeq.-.alpha.T.sub.c, or f.sub.c .varies.T.sub.c, where T.sub.c is the measured cycle period, and .alpha. is a constant based on the slope of 1/2T.sub.c,avg, where T.sub.c,avg is the average cycle period. The sample rate of the demodulated output can be reduced, through resampling, to minimize power consumption in the subsequent signal processing blocks.

Abstract: Frequency modulated signals are demodulated through a limiter circuit that chops the signal to give pulses whose occurrence frequency is proportional to the instant frequency of the received signal. The invention is devoted to a new processing of those pulses. The leading edges of the pulses are time integrated. The obtained signal is then as usual, low pass filtered to give the demodulated signal. The main advantage of this new processing is that the circuit that makes this processing does not implement delay lines and can then be made as a single chips.

Abstract: The digital FM receiver back end receives an analog intermediate frequency signal from a radio frequency front end (310) having a heterodyne circuit (312) and an intermediate frequency filter (314). In the receiver back end (307), a digital demodulator (330) having a hard limiter (333), a direct phase digitizer (336), and a phase differential circuit (339) produces a digital phase differential signal from the analog intermediate frequency signal. Next, a digital processor (360) filters and reduces noise in the digital phase differential signal using a bandpass filter (362), a de-emphasis filter (364), and an expandor (366). Finally, a pulse-width-modulation audio amplifier (380) prepares the signal for reproduction on an audio speaker (390). The digital FM receiver back end avoids inherent DC offset problems common to analog FM receivers, and it also offers a reduced complexity, size, and power consumption alternative to conventional digital FM receivers.

Abstract: Enhanced detection of an FM signal is provided through the use of a coded pattern signal which is processed at a receiver (120) non-linearly to facilitate pattern detection. The received signal is conditioned to limit signal amplitudes according to a particular noise threshold (530, 540, 550). The conditioned signal is then processed to determine the presence of the coded pattern (560). In this manner, the probability of detecting signals in weak signal conditions can be enhanced, while maintaining a particular detection falsing rate.

Abstract: A transceiver system having a base unit and a handset for communicating over a number of communication channels that are automatically switched during talk-time. A received-signal-strength-indicator (RSSI) circuit connects to the receiver for measuring the average energy received by the receiver over a baseband frequency bandwidth. The average energy includes the information, interference and noise portions of the received energy. The RSSI circuit transmits an RSSI output when the average energy exceeds a predetermined RSSI threshold. A discriminator-interference-and-noise-energy (DINE) circuit connects to the receiver for measuring out-of-band energy received by the receiver which is above the baseband frequency bandwidth. The out-of-band energy primarily comprises interference and noise energy. The DINE threshold detector provides a DINE output when the out-of-band energy exceeds a predetermined DINE threshold.

Abstract: The invention provides a demodulation PLL wherein: the first position of a switch, which is controlled by a control circuit, respectively connects the outputs of a mixer and a LP filter to high gain and low gain inputs of an oscillator when frequency signals at the inputs of the mixer have not converged sufficiently, i.e. during the PLLs tuning mode; the second position of the switch respectively connects the outputs of the mixer and the LP filter to the low gain and high gain inputs of the oscillator when the frequency signals at the inputs of the mixer and the signal levels on the input and output of the filter have converged sufficiently, i.e. during the PLLs demodulation mode.

Abstract: A frequency modulation (FM) signal demodulating circuit having a simple structure using general digital devices is provided. The FM signal demodulating circuit according to the present invention includes a first pulse generator for generating a pulse signal having a predetermined pulse width at every rising edge of the input FM signal, a second pulse generator for generating a pulse signal having a predetermined pulse width at every falling edge of the input FM signal, a combining portion for combining the pulse signals generated in the first pulse generator and the second pulse generator, and a low-pass filter for performing a low-pass filtering operation by receiving a combined pulse signal generated in the combining portion and outputting a signal having a magnitude corresponding to the frequency of the input FM signal.The FM signal demodulating circuit according to the present invention has a simple structure.

Abstract: A radio frequency (rf) receiver adapted to receive a number of different digitally modulated rf input signals such as quadrature amplitude modulated (QAM) and vestigial side band (VSB) rf input signals includes circuitry for down converting the rf input signals to an intermediate frequency (IF) range having a center frequency fc2 and a bandwidth of Bhz and converter circuitry for sampling the IF signals and then producing corresponding baseband signals. In a preferred embodiment, the intermediate frequency signals are applied to a sample and hold circuit which is sampled at a frequency fs and whose output is coupled via a low pass filter to an analog-to-digital converter whose output is then applied to a Hilbert filter for demodulating the sampled signals and producing baseband signals. In-phase (I) and quadrature (Q) signals are produced whose phase and amplitude are not a function of different components and their tolerance of different conduction paths, as in the prior art.

Abstract: A receiver configured to measure phase change (.DELTA..phi.) in a signal transmitted from a microwave signal source, such as a cell site for cellular telephones, the transmitted signal including a carrier signal (F.sub.1) added to a modulation signal (F.sub.MOD), the receiver providing the phase change measurement (.DELTA..phi.) without further reference to the modulation signal (F.sub.MOD). Utilizing (.DELTA..phi.), distance from the transmitter can be calculated. The receiver includes one or more mixers for receiving the transmitted signal from the cell site and downconverting relative to an intermediate frequency signal (F.sub.IF) to produce an IF mixed signal including a sum IF mixed signal (F.sub.IF +F.sub.MOD) and a difference IF mixed signal (F.sub.IF -F.sub.MOD). The receiver then further includes components to demodulate the IF mixed signal to provide the modulated signal (F.sub.MOD) and the phase change measurement (.DELTA..phi.) with tracking of the intermediate frequency signal (F.sub.IF).

Abstract: Radio receivers for frequency-modulated signals and more particularly, in such receivers, to a device for the demodulation of a signal modulated at intermediate frequency f.sub.i. The signal F.sub.M that is frequency modulated around a frequency f.sub.i is applied, after conversion into a square-wave signal F.sub.MR, to a delay line with shift registers that is controlled by the signals provided by an oscillator. Each of the three cascade-connected sections of the delay line introduces a delay 1/4f.sub.i and the output signals of each section are applied to EXCLUSIVE OR circuits that respectively give a demodulated signal F.sub.R1, a signal F.sub.R2 for the suppression of a demodulated signal and a signal F.sub.R3 to control the frequency of the oscillator.

Abstract: A demodulator circuit includes a gyrator circuit forming a derived equivalent inductance which is used in a demodulating circuit. The gyrator circuit has a first operational transconductance amplifier and a second operational transconductance amplifier, wherein a second input terminal of the first operational transconductance amplifier is connected to a first output terminal of the second operational transconductance amplifier. A second output terminal of the first operational transconductance amplifier is connected to a second input terminal of the second operational transconductance amplifier. Both of the second input terminal of the first operational transconductance amplifier and the second input terminal of the second operational transconductance amplifier are grounded via a constant dc voltage. A first output terminal of the first operational transconductance amplifier is connected to a first input terminal of the second operational transconductance amplifier.

Abstract: Device of the phase-locked loop type for demodulating a frequency-modulated signal. Device for frequency demodulation, using a phase-locked loop. According to the invention, for linearizing the variation of the frequency of a local oscillator (11) as a function of its control signal (Vb), a variable capacitance (Cv) is formed by an electronic module (20) which supplies the equivalent of a capacitance whose variation as a function of the control voltage (Vb) has a linearity deviation which is established for compensating the linearity deviation of the frequency of the oscillator as a function of the value of the capacitance (Cv).

Abstract: A dual-mode digital communication system for communicating an information signal during operation in frequency-modulated (FM) and multiple-access modes is disclosed herein. The digital communication system includes a dual-mode transmitter for transmitting the information signal using an FM communication signal during FM mode operation, and for transmitting the information signal using a multiple-access communication signal during multiple-access mode operation. The communication system further includes a dual-mode receiver for receiving the FM communication signal during FM mode operation, and for receiving the multiple-access communication signal during multiple-access mode operation. Incorporated within the dual-mode receiver is a digital demodulator for recovering the information signal from the received FM signal during operation in the FM mode, and for recovering the information signal from the received multiple-access signal during multiple-access mode operation.

Abstract: In order to process an input signal exhibiting a frequency modulation about an intermediate frequency, the demodulator includes a first mixer for producing a first signal exhibiting the frequency modulation about a transposition frequency lower than the intermediate frequency; a switched-capacitor phase-shifter receiving the first signal so as to produce a second signal exhibiting, with respect to the first signal, a phase-shift varying substantially linearly with frequency about the transposition frequency; two substantially identical low-pass filters receiving the second signal and the first signal respectively; and a second mixer for mixing the signals produced by the first and second low-pass filters, in order to deliver a baseband output signal.

Abstract: The invention provides a quadrature demodulator which removes unnecessary higher harmonic signals included in a demodulation output without giving rise to increase in number of externally connected parts and increase in current consumption. The quadrature demodulator includes a first double differential circuit to which a modulated signal and a first local signal are inputted, a first emitter follower circuit for effecting impedance conversion, a second double differential circuit to which the modulated signal and a second local signal having a phase shifted by 90-degrees from the first local signal are inputted, and a second emitter follower circuit connected to a pair of outputs of the second double differential circuit for effecting impedance conversion.

Abstract: A digital mixer-filter-decimator (MFD) is disclosed which is reconfigurable so that it can be used in both modes of operation of a dual mode receiver such as an AM/FM receiver. In either mode of operation the MPD performs filtering and decimation operations on separate data streams containing alternate samples of a digital input data stream. In the FM mode a mixing operation is also enabled to produce a complex output comprising in-phase and quadrature components. The mixing operation is disabled in the AM mode and the filtered and decimated outputs are combined to provide a real output. The same decimator filter can be used in both modes.

Abstract: A frequency modulated signal demodulator circuit wherein an in-phase component (I) and an orthogonal component (Q) of a frequency modulated signal output from an orthogonal detector circuit are respectively delayed by one sampling time. The result (I.multidot.Qs) of multiplying the in-phase component (I) by a delayed orthogonal component (Qs) is subtracted from the result (Q.multidot.Is) of multiplying the orthogonal component (Q) by the delayed in-phase component (Is), and the subtraction result (d.theta.) is multiplied by an inverse (1/Ts) of the sampling time to derive an instantaneous angular frequency (d.theta./Ts), whereby the frequency modulated signal can be demodulated without any feedback loop which is required by conventional FM demodulator circuits, thus making it possible to avoid a deterioration demodulation characteristics due to the influence of phasing.

Abstract: In a preferred embodiment, an FM demodulator includes an I and Q sampler for generating data samples of I and Q signals of an FM signal. A signal processor derives samples of a modulating waveform of the FM signal from the I and Q data samples, using a Lagrangian interpolation function of the I and Q data samples. Variables include derivatives of the I and Q signals obtained by differentiation of the Lagrangian function. Preferably, the processor further utilizes a correction factor to correct the modulating waveform samples obtained from the Lagrangian-based interpolation, to thereby derive a modulating waveform exhibiting low signal distortion.

Abstract: A delay-type FM demodulation circuit of this invention has an object to satisfactorily remove a harmonic wave in an arithmetic calculation output signal even if an LPF having relatively moderate stopping characteristics is used. The delay-type FM demodulation circuit includes first to third delay circuits for obtaining first to third signals obtained by times (e.g., 1/8, 1/4, and 3/8) which sequentially increase within a time shorter than 1/2 which is a signal period obtained when an FM-modulated input signal is positively deviated by a maximum frequency, a first multiplication circuit for multiplying the input signal and the first signal, a second multiplication circuit for multiplying the second signal and the third signal, and an addition circuit for adding an output signal from the first multiplication circuit and an output signal from the second multiplication circuit.

Abstract: An FM demodulator formed on a semiconductor chip generates a demodulated audio-frequency signal from an audio intermediate frequency signal through a phase locked loop constituted by a multiplier, a low-pass filter and a voltage-controlled oscillator. A variation of amplitude of the demodulated audio-frequency signal due to a temperature variation is compensated by a temperature compensating amplifier and a de-emphasis filter through first and second reference currents flowing out therefrom through an internal resistor fabricated on the same semiconductor chip and an external resistor.

Abstract: A polarity detection circuit for an FPLL demodulated signal including a small DC pilot recovers the DC pilot by determining the DC levels of the demodulated output signals both with and without the DC pilot. A zero carrier condition is created for determining the DC level of the output signal without the DC pilot. The two DC levels are subtracted and limited and the polarity of the recovered DC pilot is used to control the operation of a polarity inverter to assure that the output signal has a desired polarity.

Abstract: In the digital FM demodulator (330), a hard limiter (333) receives a modulated analog IF signal and limits the voltage of the IF signal to two levels. Next, a direct phase digitizer (336) uses zero-crossings of the limited IF signal to generate N-bit digital words. A phase differential circuit (340) computes the phase shift of the signal from the direct phase digitizer over a predetermined time interval. The dynamic range of the phase differential signal can be increased by replacing the phase differential circuit (340) with a high-resolution phase differential circuit (700). After digital demodulation and filtering and gain control by audio processor (360), the recovered signal is forwarded to a speaker (390) to produce an audio output. Thus, the digital FM demodulator both avoids problems common to analog discriminator circuitry and offers a reduced complexity, size, and power consumption alternative to conventional digital FM demodulators.

Abstract: The invention provides a demodulation PLL wherein: the first position of a switch, which is controlled by a control circuit, respectively connects the outputs of a mixer and a LP filter to high gain and low gain inputs of an oscillator when frequency signals at the inputs of the mixer have not converged sufficiently, i.e. during the PLLs tuning mode; the second position of the switch respectively connects the outputs of the mixer and the LP filter to the low gain and high gain inputs of the oscillator when the frequency signals at the inputs of the mixer and the signal levels on the input and output of the filter have converged sufficiently, i.e. during the PLLs demodulation mode.

Abstract: A method of demodulating an FM carrier wave and an FM demodulation circuit are described which use a phase locked loop. An FM input signal including the carrier wave is supplied to a phase detector in the phase locked loop. The output of the phase detector is filtered and used to generate a signal for use in controlling a voltage controlled oscillator having an output also connected to the phase detector. The phase locked loop is tuned to a selected carrier wave frequency and a variable gain setting of a variable gain circuit in the phase locked loop is selected to select a desired loop gain. The signal for use in controlling the voltage controlled oscillator is varied by the variable gain circuit to alter the amount by which the frequency of the output of the voltage controlled oscillator changes in relation to a given output of the phase detector. The variable gain setting is selected to select a required bandwidth for demodulation.

Abstract: An FM demodulator demodulating an FM modulated input signal through a PLL circuit, which includes a phase comparator a loop filter, a DC amplifier, a BB amplifier, and a VCO, and outputting the demodulated signal further includes a feedback circuit connected in parallel to DC amplifier and having a resistance which is a function of an external control voltage. The feedback circuit may be connected in parallel to both DC amplifier and BB amplifier. A PIN diode is typically used as a resistance variable element in the feedback circuit.

Abstract: An FM detecting circuit using phase locked loop (PLL) is disclosed. A reference voltage unit generates a reference voltage. A phase detector detects a phase difference between an FM signal and another frequency signal. A low-pass filter receives the output signal from the phase detector, and outputs a detected signal by passing only low frequency signals. A DC component detector receives the output signal from the low-pass filter, and detects a DC component. A voltage controlled amplifier receives the reference voltage and the voltage output from the DC component detector, and outputs a constant level voltage by controlling a gain based upon the difference between the two received voltages.

Abstract: In a quadrature FM detector, demodulation is performed by a product detector which multiplies an amplitude limited FM modulated information signal by a version of the amplitude limited FM modulated information signal which has been phase shifted by a phase shifting network including a single tuned LC circuit. In order to assure that the LC circuit is tuned to the carrier frequency of the FM signal, the LC circuit is tuned by a variable impedance device in response to a control signal generated by a bus controlled DAC. The control signal is coupled to the variable impedance device at the same pin of an integrated circuit where the LC circuit is coupled to the demodulator.

Abstract: A heterodyne receiver including a frequency discriminator adapted such that a signal to be subjected to frequency discrimination is divided into two signals and mixed together after one of the divided signals has been given a delay time, and additionally provided with a filter, of which a cutoff frequency is determined according to the delay time, disposed in the front stage. This results in both improvement of accuracy in frequency identification and expansion of the capture range.

Abstract: A demodulator receives a radio signal and causes a carrier signal reproducing circuit to reproduce the carrier signal of the received signal. One amplifier amplifies the amplitude of the reproduced carrier signal by K, and another amplifies the amplitude of the reproduced carrier signal by (K+2). An adder adds the reproduced carrier signal, amplified by K, and the received signal. A subtracter subtracts the received signal from the reproduced carrier signal amplified by (K+2). The output signal of the adder is demodulated by a first FM demodulator and the output signal of the subtracter is demodulated by a second FM demodulator. Another subtracter outputs the difference between the demodulated signals from the first and second FM demodulators as a demodulated signal of the received signal.

Abstract: A frequency modulation signal demodulator receives an intermediate frequency signal to demodulate a FM signal. The frequency modulation signal demodulator includes a voltage-controlled oscillator having variable capacitance diodes. The voltage-controlled oscillator varies the oscillating frequency of a signal by controlling a voltage across the variable capacitance diodes using a DC voltage. Also included is a phase comparator which produces a phase difference by comparing the phase of the intermediate frequency signal to the phase of the signal from the voltage-controlled oscillator and provides a direct current voltage signal corresponding to the phase difference. Also included is a differential amplifier which has an adjustable reference voltage source. The differential amplifier amplifies the direct current voltage signal to produce a demodulated signal. The demodulated signal is negatively fed back to the voltage-controlled oscillator as the direct current signal.

Abstract: In a phase detector, an input signal (Si) is multiplied in a multiplier by two reference signals intersecting at right angles with each other. Signals obtained by multiplication are passed through filters and subjected to quadrature demodulation. An I signal and a Q signal obtained by quadrature demodulation are input to non-linear compression circuits and compressed by logarithmic conversion. Based on the compressed I and Q signals, a phase detection circuit detects the phase of the input signal (Si).

Abstract: A phase detection system in which an original modulation signal is detected from a first complex baseband signal obtained through orthogonal demodulation of an FM signal and output, a second complex baseband signal having cosine and sine components of a phase change .DELTA..phi. of the first complex baseband signal in a predetermined time interval .tau. is rotated until a rotation angle .theta. becomes .DELTA..phi., and rotation angle data indicative of the rotation angle .iota. is detected and output.

Abstract: This delay detection circuit receives a digital-phase-modulated signal including an already-known preset symbol string and an unknown data symbol string following the already-known string, and detects a phase difference between an instantaneous phase of a reception signal and an instantaneous phase after a preset symbol time from the time of the reception signal received using a phase difference detector. Then, the delay detection circuit calculates a compensation phase difference necessary to demodulate the reception signal from the phase difference, the phase difference of demodulation symbol estimated from the already-known symbol string and the phase difference of demodulation symbol estimated from the data symbol string, and demodulate the reception signal based on the compensation phase difference.

Abstract: Disclosed is a tuned channel detector which includes a cable path between a radio frequency source and a receiver such as a TV, wherein the radio frequency source passes first through an attenuator and second through a signal selection module comprising two opposing directional couplers and a single-pole/double-throw switch. The channel to which the TV is tuned is determined by measuring the TV's local oscillator signal from the cable which feeds the radio frequency signal to the TV and, additionally or alternatively, by comparing the signal strength of the input and reflected TV carrier signals at and around the channels under test. Signal detection is further enhanced by modulating the signal mixed with the local oscillator with a tone and/or testing only during certain intervals such as the vertical synchronization interval or the power line cycle. A tone detector having a synchronous rectifier is used to detect low level local oscillator signals.

Abstract: Digital FM demodulator and method in which zero-crossings of a frequency modulated input signal are detected, a binary pulse is provided for each of the zero-crossings, and the binary pulse stream is filtered digitally to provide enhanced resolution of the incremental phase (frequency) of the input signal over a period which is asynchronous with the input signal. In the disclosed embodiments, the digital filtering is done with comb decimation filters, with a higher order filter being employed where greater resolution is desired.

Abstract: A frequency demodulation circuit having an improved detection sensitivity is provided by forming an all-pass equalizer in a Quadrature-type demodulator capable of allowing a band covering at least a carrier frequency deviation to pass therethrough. The equalizer comprises a band-pass filter for detecting the frequency deviation of an inputted FM carrier signal, a gain-doubling amplifier and a substractor for performing subtraction between the signal inputted to the band-pass filter and the output of the amplifier. The operation of the circuit is such that a FM carrier signal is supplied to the band-pass filter through a phase shifter and to a phase comparator and the output of the substractor and the FM carrier signal are compared to each other by the phase comparator to thereby obtain a FM demodulated signal.

Abstract: Digital frequency demodulation is accomplished by monitoring similar transitions in an FM radio signal to determine frequency. Time intervals between similar transitions in the FM signal are established by selecting anticipated transition times and accumulating error values relative to actual transition times. Accumulated error values provide a basis for further selecting anticipated transition times in such manner that a reported sequence of anticipated transition times provides a basis for inferring signal frequency. In one illustrated embodiment, the chosen transition times are positive transitions in the FM signal and the anticipated times of transition are taken from a set of two time periods, an early transition and a late transition relative to a valid transition window. In one embodiment of the invention, accumulated error is stored in an integrator device while in another embodiment accumulated error is stored in the phase of a bi-frequency oscillator.

Abstract: The digital FM demodulation apparatus includes a sampling unit, a frequency specifying unit, and a demodulated value specifying unit. The sampling unit samples an FM modulated wave at predetermined intervals. The frequency specifying unit specifies a frequency of the FM modulated wave at the time of sampling based on a plurality of sampled values. The demodulated value specifying unit specifies a demodulated value corresponding to the frequency to provide the demodulated value.

Abstract: In a digital frequency demodulator, data representing the input signal to be demodulated is prestored in a look-up table and signal processing is digitally performed to generate a read address required for reading out the data stored in the look-up table using a phase shift method of operation. Phase-shifting is performed by determining the slope of a frequency-modulated signal containing a signal which does not cross the zero axis. Thus, the precision of the frequency demodulation is enhanced, and the frequency demodulation data stored in the look-up table is minimized to reduce the size of a ROM used for the look-up table.

Abstract: An apparatus and method is provided of recovering a frequency modulated signal having a first component of the frequency modulated signal at a zero-RF spectral location and a second component of the frequency modulated signal at a zero-RF spectral location in quadrature relationship to the first component. The method includes the steps of: upconverting and summing the first and second components to produce a reference signal (100), time delaying the first and second components, upconverting and summing the delayed, upconverted first and second components to produce a delayed reference signal (101) in quadrature relationship to the reference signal; limiting the reference and delayed signal (102); and exclusive or-ing (103) the limited reference and limited delayed signal.

Abstract: A dual mode quadrature detector (15) uses the same components for both narrow band and wide band operation and provides an output amplitude which is independent of the mode of operation selected. A multiplier (32) provides a demodulated output signal (16) which is responsive to the phase difference between a signal (14) at one input (32A) and a phase shifted version of the signal at the other input (32B). A capacitor (30) and a phase shifting circuit (31) provide the phase shifted version of the signal. The phase shifting circuit (31) is responsive to a mode control signal (24) for determining the phase shift which is provided. The phase shift at the maximum frequency deviation of the narrow band signal is the same as the phase shaft at the maximum deviation of the wide band signal so that the output amplitude from the detector (15) is the same for both narrow band and wide band operation. The phase shift provided is controlled by varying the quality factor (Q) of the phase shifting circuit (31).

Abstract: A demodulation circuit comprises: a phase detection circuit for determining an absolute value of a phase difference between an input signal to be demodulated and a reference signal; a binary phase detection circuit for converting a phase lead or lag between the input signal and the reference signal into a sign of phase difference; and a phase demodulation circuit for calculating, from the absolute value and the sign of phase difference, a phase difference quantity between the input signal and the reference signal and for performing a delay detection on the phase difference quantity; wherein the binary phase detection circuit includes a delay circuit which generates a delay time corresponding to the operation delay of the phase detection circuit; and wherein the phase detection circuit includes a level limiter circuit to limit an internal signal voltage and a reference voltage adjust circuit to correct deviations in the internal signal voltage.

Abstract: A receiver (20) digitally tunes a radio frequency (RF) signal at the same time that it mixes the RF signal to a frequency suitable for demodulation and channel separation. A clock frequency divider (35) receives a reference clock signal, and divides the reference clock signal to provide a divided signal at a predetermined frequency, such as 20 kHz for AM stereo. A clock frequency multiplier (36) receives the divided signal and a digital tuning input signal, and provides an analog tuning signal at a multiple of the divided signal as determined by the digital tuning input signal. An analog multiplier (31) then mixes the RF signal with the analog tuning signal. An analog-to-digital converter (ADC) (32) receives an output of the analog multiplier (31), and is clocked by the reference clock signal to eliminate any clock phase error. A digital demodulator (38) then demodulates and further processes an output of the ADC (32).