Abstract: A storage system includes a storage device having a nonvolatile memory with a first and a second physical address and a host configured to insert a first journal logical address and a first target logical address into a journal mapping table. The storage device includes a flash mapping table storing the first journal logical address mapped to the first physical address, and the first target logical address mapped to the second physical address; a circuit configured to write the first journal data to an area of the nonvolatile memory to the first physical address corresponding to the first journal logical address according to the first mapping state, based on the journaling command; and to change the first mapping state of the flash mapping table to a second mapping state in which the first target logical address is remapped to the first physical address, based on the checkpointing command.

Abstract: A system, method, and computer readable medium for hybrid kernel-mode and user-mode checkpointing of multi-process applications using a character device. The computer readable medium includes computer-executable instructions for execution by a processing system. A multi-process application runs on primary hosts and is checkpointed by a checkpointer comprised of a kernel-mode checkpointer module and one or more user-space interceptors providing barrier synchronization, checkpointing thread, resource flushing, and an application virtualization space. Checkpoints may be written to storage and the application restored from said stored checkpoint at a later time. Checkpointing is transparent to the application and requires no modification to the application, operating system, networking stack or libraries. In an alternate embodiment the kernel-mode checkpointer is built into the kernel.

Abstract: Data collection is provided, in which one or more affected transactions related to one or more transaction exceptions are determined. Based on one or more features of the one or more affected transactions, one or more trace features are determined. Based on the one or more trace features, a data collection rule is generated. Data of a subsequent transaction complying with the data collection rule is collected.

Abstract: A motion control program that causes a computer to function as: a reception unit on a non-real-time OS that receives a control command that controls a plurality of control target devices, and notifies a control unit of control command information indicating a content of the received control command; the control unit that generates an interpolation command for each of the control target devices repeatedly for each of motion control cycles based on the control command information notified from the reception unit, and stores the generated interpolation command; and a communication module unit that obtains an interpolation command, converts the obtained interpolation command from a predetermined signal format which can be recognized by the control unit into a signal format with a communication interface standard which can be recognized by each of the plurality of control target devices, and transmits the interpolation command.

Abstract: A system, method, and computer readable medium for hybrid kernel-mode and user-mode checkpointing of multi-process applications using a character device. The computer readable medium includes computer-executable instructions for execution by a processing system. A multi-process application runs on primary hosts and is checkpointed by a checkpointer comprised of a kernel-mode checkpointer module and one or more user-space interceptors providing barrier synchronization, checkpointing thread, resource flushing, and an application virtualization space. Checkpoints may be written to storage and the application restored from said stored checkpoint at a later time. Checkpointing is transparent to the application and requires no modification to the application, operating system, networking stack or libraries. In an alternate embodiment the kernel-mode checkpointer is built into the kernel.

Abstract: A system includes a memory and multiple processors. The memory further includes a shared section and a non-shared section. The processors further include at least a first processor and a second processor, both of which read-only access to the shared section of the memory. The first processor and the second processor are operable to execute shared code stored in the shared section of the memory, and execute non-shared code stored in a first sub-section and a second sub-section of the non-shared section, respectively. The first processor and the second processor execute the share code according to a first scheduler and a second scheduler, respectively. The first scheduler operates independently of the second scheduler.

Abstract: A request to perform a test with one or more memory components can be received. Available test resources of a test platform that is associated with memory components can be determined. The desired characteristics of the one or more memory components that are specified by the test can be determined. One or more of the available test resources of the test platform to the test can be assigned based on characteristics of respective memory components associated with the one or more of the available test resources and the desired characteristics of the one or more memory components of the test. Furthermore, the test can be performed with the assigned one or more of the available test resources of the test platform.

Abstract: Embodiments of the specification provide a method and an apparatus for updating shared data in a multi-core processor environment. The multi-processor environment comprises a multi-core processor. The multi-core processor comprises a plurality of separate processing units (referred to as cores, or core processing units (CPUs) in the specification); the multi-core processor is configured to process a multi-threaded task; the multi-threaded task has shared data to update. The method is executed by any CPU. The method may comprise: requesting, by a first CPU, for a lock to execute a critical section function on the shared data, wherein the lock provides permission to update the shared data, and the critical section function updates the shared data; and setting, by the first CPU if the lock is occupied by a second CPU, a memory index corresponding to the critical section function in a memory of the lock for the second CPU to execute the critical section function based on the memory index.

Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors, local memories, configurable communication elements, and direct memory access (DMA) engines, and a DMA controller. Each processor may be coupled to one of the local memories, and the plurality of processors, local memories, and configurable communication elements may be coupled together in an interspersed arrangement. The DMA controller may be configured to control the operation of the plurality of DMA engines.

Abstract: A multi-master hybrid bus apparatus is provided. The multi-master hybrid bus apparatus includes a hybrid bus bridge circuit configured to couple multiple master circuits with one or more slave circuits via heterogeneous communication buses. In examples discussed herein, the multiple master circuits can correspond to multiple physically separated master circuits or multiple bus ports provided in a single master circuit. In a non-limiting example, the hybrid bus bridge circuit is coupled to the multiple master circuits via multiple radio frequency front-end (RFFE) buses and to the slave circuits via at least one single-wire bus (SuBUS) consisting of a single wire. By bridging the multiple master circuits to the slave circuits based on a single hybrid bus bridge circuit, it may be possible to enable flexible heterogeneous bus deployment in an electronic device (e.g., a smartphone) with reduced cost and/or footprint.

Abstract: An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes directory control logic that configures at least a number of congruence classes utilized in the real address-based directory based on configuration parameters specified on behalf of or by the accelerator unit.

Abstract: A system and method for providing data redundancy. The method includes receiving a write instruction, the write instruction including data to be written to a primary remote direct access (RDMA) storage and a primary block address corresponding to a designated primary block of the primary RDMA storage, wherein the designated primary block is associated with a primary lock stored in the primary RDMA storage; determining whether the primary lock and at least one secondary lock are obtained, wherein each secondary lock is associated with a secondary block of a distinct secondary RDMA storage; and writing the data included in the write instruction to the designated primary data block and each secondary data block associated with the obtained at least one secondary lock, when it is determined that the primary lock and the at least one secondary lock have been obtained.

Abstract: Systems, methods, and media are presented that are used to recompute a service model to match data in a configuration management database. Recomputing includes detecting a change to a configuration item in a configuration management database and marking a recomputing environment indicating a recomputing environment to be recomputed based on the change. Using a recomputation job, a service environment database is queried and a response is received from the service environment indicating at least the recomputing environment. The recomputation job then recomputes the service environment to match a service model to the change in the configuration management database.

Abstract: A system and method is provided for smart grid dynamic regulation pools. The system may include at least one processor configured to initiate a plurality of pool regulation tasks that are respectively executed by different processing resources. The pool regulation tasks respectively manage respective subsets of electrical power assets assigned to respective different regulation pools to fulfill electrical power requirements for market orders received from at least one energy trading market system. Such management may include determining whether to reassign at least one asset to fulfill at least one market order. Also responsive to a determination to reassign the at least one asset, the management may include removing the at least one asset from one regulation pool managed with one pool regulation task for at least one market order and assigning the removed asset to another regulation pool managed with another pool regulation task for at least one market order.

Abstract: A control system for a machine comprising a plurality of independently replaceable machine modules comprises a controller operable to control operation of the machine. Memory stores machine data for use by the controller. Communication means are operable to provide communication for data transfer between the controller and the memory. The memory includes a plurality of memory modules associated with respective machine modules. Each of the memory modules is replaceable with the respective associated machine module and independently of other memory modules. The communication means is operable to provide communication for data transfer between the controller and a replacement memory module associated with a replacement machine module.

Abstract: A system includes a multi-process application that runs on primary hosts and is checkpointed by a checkpointer comprised of a kernel-mode checkpointer module and one or more user-space interceptors providing at least one of barrier synchronization, checkpointing thread, resource flushing, and an application virtualization space. Checkpoints may be written to storage and the application restored from said stored checkpoint at a later time. Checkpointing may be incremental using Page Table Entry (PTE) pages and Virtual Memory Areas (VMA) information. Checkpointing is transparent to the application and requires no modification to the application, operating system, networking stack or libraries. In an alternate embodiment the kernel-mode checkpointer is built into the kernel.

Abstract: A numerical controller is equipped with an access unit configured to access variables included within a machining program at a time of analyzing the machining program, a look-ahead determining unit configured to determine whether or not the variables accessed by the access unit were accessed during look-ahead of the machining program, a specific variable determining unit configured to determine whether or not the variables determined to have been accessed during look-ahead by the look-ahead determining unit are specific variables, and an output unit configured to output at least one of numbers of the specific variables accessed during look-ahead and a time of accessing the specific variables during look-ahead, in the event that the variables accessed during look-ahead are determined to be the specific variables by the specific variable determining unit.

Abstract: A method for recognizing traffic signs includes: receiving images of traffic signs from different locations at different times; and calculating a first probability value that indicates the probability with which an image received at a specific time maps a specific traffic sign from a set of traffic signs. The calculating is based on: at least one image of a traffic sign received before the specific time and characterizing an earlier state, and a previously known transition probability value that indicates the probability with which the specific traffic sign occurs following the earlier state.

Abstract: A computer-implemented method for computer-implemented method for communicating completion of synchronous input/output (I/O) commands between a processor executing an operating system and a recipient control unit is described. The method may include issuing, by a processor, a Synchronous I/O command to the recipient control unit; receiving, with the processor, a DMA read request from the recipient control unit; converting, with the processor, the DMA read response to write a data record into memory of the recipient control unit; issuing the DMA read request to the recipient control unit, wherein the DMA read request comprises an echo read portion comprising at least one byte of information at the end of the data record written; receiving, by the processor, a DMA write confirmation comprising the echo read portion of the record; and writing the echo read portion to a status area.

Abstract: The present disclosure relates to offloading computing tasks from a user device to a cloud service. In one embodiment, a method generally includes generating, based on user input, a command for processing by the cloud service. The user device ranks the user device and one or more peer devices in a network based on at least one of information about the user device and one or more peer devices and information about the generated command from the user device and the peer devices, and the user device selects one or more of the user device and the peer devices to transmit the command based on the ranking information. Upon determining that the user device is one of the selected devices, the user device transmits the command to the cloud service. If the user device is not one of the selected devices, the user device discards the generated command.

Abstract: A file with an exclusive serialization is allocated. The exclusive serialization associated with the newly allocated file is transformed into a shared serialization. The file with the shared serialization is allocated as shared resource for a multisystem environment.

Abstract: Methods, systems, and computer programs are presented for virtualizing Non-Volatile Random Access Memory (NVRAM). A first area in RAM is labeled as active area and a second area as non-active area, and an active journal and a non-active journal are created in permanent storage. A transaction is created for each write made to the virtual NVRAM, and the created transactions are written to the active journal and to the active area. When the active journal is greater than a predetermined size or a timeout occurs, a checkpoint is created by copying contents from the active area to the non-active area, switching status of the active area and the non-active areas (the active area becomes the non-active area and the non-active area becomes the active area), switching status of the active journal and the non-active journal, and copying the content of the current non-active area to permanent storage.

Abstract: A parallel computing apparatus includes a first processor that executes a first thread, a second processor that executes a second thread, and a memory. The memory includes a first private area that corresponds to the first thread, a second private area that corresponds to the second thread, and a shared area. The first processor stores first data in the first private area and stores address information that enables access to the first data in the shared area. The second processor stores second data in the second private area, accesses the first data based on the address information, and generates third data based on the first and second data.

Abstract: In a method for processing cache data of a computing device, a storage space of the storage device is divided into sections, and a section number of each data block in the storage device is determined according one of the sections in the storage device which each data block belongs to. A field is added for each data block in the storage device to record a section number of each data block in the storage device. When the cache data in the cache memory requires to be written back to the storage device, cache data with the section number is searched from all of the cache data in the cache memory to be written back to a corresponding section in the storage device.

Abstract: When computers and virtual machines operating in the computers both attempt to allocate a cache regarding the data in a secondary storage device to respective primary storage devices, identical data is prevented from being stored independently in multiple computers or virtual machines. An integrated cache management function in the computer arbitrates which computer or virtual machine should cache the data of the secondary storage device, and when the computer or the virtual machine executes input/output of data of the secondary storage device, the computer inquires the integrated cache management function, based on which the integrated cache management function retains the cache only in a single computer, and instructs the other computers to delete the cache. Thus, it is possible to prevent identical data from being cached in a duplicated manner in multiple locations of the primary storage device, and enables efficient capacity usage of the primary storage device.

Abstract: For easy centralized management of measurement data and installation environmental data and user's real-time recognition through a certain type of peripheral equipment of how the installation environment affects the measured values at the site of measurement, a data logger for a measurement device includes in its structure any of the sensors for temperature, humidity, air pressure, and acceleration as an environmental sensor that detects a physical quality of an environment where the measurement device is installed, a data recording unit that records installation environmental data detected by the environmental sensor and measurement data detected by the measurement device on the basis of time, and a data processing unit that displays the installation environmental data and measurement data in whole or selectively, as numerical values or graphs of changes over time, with the time axes aligned, and includes one or more external equipment terminal connectors that exchange signals with external equipment.

Abstract: A control apparatus sends a data access request to a first memory sharing device, wherein the data access request includes an address of target data. The first memory sharing device determines that the target data is stored in a second memory sharing device according to the address of the target data and an address list. The address list includes corresponding relationships between addresses and memory sharing devices, and first addresses corresponding to the first memory sharing device are different from second addresses corresponding to the second memory sharing device, and forward the data access request to the second memory sharing device. The second memory sharing device obtains the target data based on the address of the target data, and sends the target data to the first memory sharing device. Then the first memory sharing device forwards the target data to the control apparatus.

Abstract: A data manager may include a data opaque interface configured to provide, to an arbitrarily selected page-oriented access method, interface access to page data storage that includes latch-free access to the page data storage. In another aspect, a swap operation may be initiated, of a portion of a first page in cache layer storage to a location in secondary storage, based on initiating a prepending of a partial swap delta record to a page state associated with the first page, the partial swap delta record including a main memory address indicating a storage location of a flush delta record that indicates a location in secondary storage of a missing part of the first page. In another aspect, a page manager may initiate a flush operation of a first page in cache layer storage to a location in secondary storage, based on atomic operations with flush delta records.

Abstract: A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect that implements internal controls. The interconnect in an integrated circuit communicates transactions between initiator Intellectual Property (IP) cores and target IP cores coupled to the interconnect. The interconnect implements logic configured to support multiple transactions issued from a first initiator IP core to the multiple target IP cores while maintaining an expected execution order within the transactions. The logic supports a second transaction to be issued from the first initiator IP core to a second target IP core before a first transaction issued from the same first initiator IP core to a first target IP core has completed while ensuring that the first transaction completes before the second transaction and while ensuring an expected execution order within the first transaction and second transaction are maintained. The logic does not include any reorder buffering.

Abstract: A system, method, and computer-readable storage medium having a computer-readable instruction thereon to replicate transactions in a Zettabyte File System (ZFS). The method includes operations including determining, using a tracing module, a commitment of a current file transaction to a disk, obtaining when a probe function associated with the current file transaction is triggered, the current file transaction, recording a data change contained in the current file transaction, registering a callback function and a reference to the data change contained in the current file transaction after the commitment of the current file transaction, and sending the data change to a remote server.

Abstract: Embodiments relate to two general purpose computers connected in a peer-to-peer mode by connecting a cable (or wireless connection) between universal ports (e.g., PCIe ports) on each computer. A timing protocol utility runs on each computer to time schedule operations performed by its respective computer. Because the system clocks on each peer computer operate independently (asynchronously), they may vary somewhat from each other. To support time synchronized peer-to-peer operations, paired clock value (one for each peer computer) are generated continually and independently by each peer system. Each peer system periodically supplies the paired clock values to its associated timing protocol utility, which uses the paired clock values to time synchronize peer-to-peer computer operations. The timing protocol utilities may also exchange the paired clock values with each other for integrity checking and other operations.

Abstract: Disclosed are various embodiments for determining capacities for work buffers. Data is received that indicates past work cycles for a first stage and a second stage of a pipelined process. The pipelined process includes a work buffer between the first stage and the second stage. Staffing levels for the first stage and the second stage are received. An optimal buffer capacity for the work buffer is generated based at least in part on a predicted workflow variance for the pipelined process, the staffing levels, and the past work cycles.

Abstract: An environment is described in which a cloud-implemented service system controls a plurality of target devices via a plurality of respective device-agnostic pipe mechanisms. The target devices themselves may represent “dumb” devices, e.g., lacking local control logic, or providing reduced reliance on local control logic. Users may interact with the service system via applications running on any type of user devices.

Abstract: Disclosed are systems, methods, and software for performing version control. In a particular embodiment, a non-transitory computer readable medium is provided having stored therein program instructions that, when executed by a computer system, direct the computer system to perform a method of version control. The method includes executing a plurality of virtual machines from a plurality of derivative versions of an ancestor data volume, wherein the ancestor data volume and the plurality of derivative versions each comprise a plurality of files. The method further includes tracking modifications to the plurality of files in each of the plurality of derivative versions and merging the plurality of derivative versions with the ancestor data volume based on the modifications.

Abstract: An improved method for the prevention of deadlock in a massively parallel processor (MPP) system wherein, prior to a process sending messages to another process running on a remote processor, the process allocates space in a deadlock-avoidance FIFO. The allocated space provides a “landing zone” for requests that the software process (the application software) will subsequently issue using a remote-memory-access function. In some embodiments, the deadlock-avoidance (DLA) function provides two different deadlock-avoidance schemes: controlled discard and persistent reservation. In some embodiments, the software process determines which scheme will be used at the time the space is allocated.

Abstract: A method for enhancing an input image to produce an enhanced output image is provided. The method includes constructing a photographic-mask intermediate image without low-contrast details and a temporary-image intermediate image with enhanced mid-contrast details, retained high-contrast details, and reduced low-contrast details, and employing values for the photographic-mask intermediate image and temporary-image intermediate image to produce the enhanced output image that is globally and locally contrast-enhanced, sharpened, and denoised.

Abstract: There is described a method for determining a value of a zero point offset of a yaw rate sensor. The method comprises measuring over time the output of the yaw rate sensor, determining whether the measured output has remained within a set of limits for a pre-determined period and if it is determined that the measured output has remained within the limits for the pre-determined period, using at least one measured value of the output to determine the value of the zero point offset.

Abstract: A central control and instrumentation system with a plurality of functional modules interconnected by data transmission is provided. The functional modules are monitored by a central control module. Functional modules with a data output after completing a predefined number of action cycles, which are specific to each module, allow a provision of a fast motion functionality for simulation purposes and are subjected to a correction parameter of the number of action cycles for a user-controlled variation of the respective cycle to be completed.

Abstract: A system for storing data from an industrial control system having an industrial controller including a communication module and first memory containing data for controlling an industrial process is provided. The system comprises a computer separate from the industrial controller and having a second memory and an application for automatically accessing the data from the first memory of the industrial controller via the communication module and storing the data on the second memory.

Abstract: The present approach increases bandwidth by performing at least two functions at the pre-processing level. Specifically, under the present approach, program code is structured so that the segmentation and binarization functions/modules (and optionally a blob analysis function/module) are merged into a single module to reduce memory bandwidth. In addition, each image frame is segmented into a plurality of partitions (e.g., vertical strips) to enhance the reusability of the image data in LS already fetched from main memory. Each partition is then processed by a separate one of a plurality of processing engines, thereby increasing the utilization of all processing engines and allowing the processing engines to maintain good bandwidth.

Abstract: The present invention relates to a system and methodology facilitating network communications between an industrial control system and a client application that interacts with a plurality of data items on the control system. The client application initiates a request or query to the industrial control system for an identification of selected data items of interest. Based on information received in the request, an aggregation component can be constructed by the client, wherein names and buffer allocations relating to the data items of interest are provided. The aggregation component is then installed by the client and updated in the industrial control system, thus providing information access to the client application when fresh or updated information is desired. Information is accessed via a communications packet that is generated from the data items identified in the aggregation component.

Abstract: Disclosed are methods and systems for granting an application-specific integrated circuit (ASIC) in a multi-ASIC environment controlled access to a shared resource. A system includes a first ASIC, a second ASIC, and a shared memory that stores a shared resource and a data set partitioned into fields. The first ASIC writes data to a first subset of the fields and reads data from the fields. The first ASIC includes first logic that computes a first value based on the data read from the fields. The second ASIC writes data to a second subset of the fields and reads data from the fields. The second ASIC includes second logic that computes a second value based on the data read from the fields. Based on the first and second values respectively computed by the first and second logic, only one of the first and second ASICs gains access to the shared resource.

Abstract: A programmable logic processor (PLC) with multiple PLC functions is disclosed. The PLC includes at least one memory storing at least one of a plurality of programs or data, and one or more processor assigned to each of the PLC function and couple to the memory. The PLC functions are run in parallel. A method of operating the PLC and a PLC system with multiple processors are also disclosed.

Abstract: A PLC for distributed control includes a storage unit that stores common-data specifying information for specifying common data shared by a corresponding PLC and another PLC, a receiving unit that receives the common-data specifying information from another PLC, and a collating unit that collates the common-data specifying information stored in the storage unit with the common-data specifying information received by the receiving unit.

Abstract: For example, by providing MMF software 10, 11 transferring data using a memory-mapped file respectively in a semiconductor manufacturing apparatus 1 and in an input signal analyzing system 8, data transfer load placed on control software 4 and analyzing software 9 is reduced. Additionally, in the MMF software 10, by inserting counter information in the memory-mapped file and by observing the information by the MMF software 11, communication abnormality is detected.

Abstract: A computer-aided configuration for a technical installation includes a presentation layer with operator control interfaces, an application layer containing all applications, a realtime basic processing layer for providing all applications and operator control interfaces with information and a data manager for creating and maintaining data models for operating and system functions. One such configuration is constructed in such a way that the structure thereof is favorable to extension and offers high availability. The applications in the realtime basic processing layer are respectively combined to form bundles, wherein the same data model is respectively common to the applications of a bundle. The data of a respective application bundle is stored in an application bundle storage unit as shared memory mapped files. A method for operating such a configuration includes storing the data in the realtime basic processing layer in an application bundle storage unit as shared memory mapped files.

Abstract: A system for providing an application with a plurality of methods for accessing memory of a programmable logic controller includes an application, an interface for establishing communication between the application and a programmable logic controller, and a shared memory area initiated by the application or the programmable logic controller. The shared memory area includes an input memory and an output memory. The application is enabled by the interface to write to the input memory and to read from the output memory.

Abstract: Phase function blocks are associated with a process for producing at least one product or part thereof. For example, a phase function block could reside in a recipe control module defining the process. Each phase function block can be executed to implement the process. A phase function block may acquire and initiate execution of a module providing control over a process element. The phase function block may also provide one or more first parameters to the module. The first parameters define how the module implements a portion of the process using the process element. In addition, the phase function block may retrieve one or more second parameters from the module. The second parameters are associated with results of the execution of the module. Multiple phase function blocks could be contained in multiple recipe control modules, which are distributed in multiple controllers in a hard real-time process control system.

Abstract: A method of recovering the state of a system, which system comprises at least one counter, which counter represents an instantaneous state of an entity in a system. The counter will increase in value in response to an increment request and decrease in value in response to a decrement request, wherein each increment request is paired with a decrement request.

Abstract: An Intelligent Data Multiplexer (“IDM”) can be used to interface a plurality of host computers with a semiconductor manufacturing tool. In one embodiment, the IDM has a plurality of host-side ports configured to receive messages from each of the host computers interfaced with the semiconductor manufacturing tool. The IDM also includes a multiplexer configured to multiplex the messages received from the host-side ports. To process possible conflict messages from the host computers, the IDM has a conflict resolve module. The messages are then delivered from the IDM to the semiconductor manufacturing tool through a tool-side port used to connect the semiconductor manufacturing tool to the IDM.