Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

Abstract: A neural network not requiring massive changes in configuration when changing the number of stages (number of levels) of the neural network. This neural network is provided with at least one neuron core 10 performing an analog multiply-accumulate operation and a weight-value-supply control unit 30 supplying the weight value to the neuron core 10. This neural network is subjected to control processing by a control-processor unit 40 controlling the supply of the weight value from said weight-value-supply control unit 30 in synchronization with the timing of the analog multiply-accumulate operation of the neuron core 10, and processing the data output from the neuron core 10 at every analog multiply-accumulate operation performed by said neuron core as serial data and/or parallel data.

Abstract: Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, an analog neural memory system comprises an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to word line terminals of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to bit line terminals of a column of non-volatile memory cells; and a plurality of erase gate enable transistors, each erase gate enable transistor coupled to erase gate terminals of a word of non-volatile memory cells.

Abstract: The present disclosure relates to a neuron for an artificial neural network. The neuron includes: a first dot product engine operative to: receive a first set of weights; receive a set of inputs; and calculate the dot product of the set of inputs and the first set of weights to generate a first dot product engine output. The neuron further includes a second dot product engine operative to: receive a second set of weights; receive an input based on the first dot product engine output; and generate a second dot product engine output based on the product of the first dot product engine output and a weight of the second set of weights. The neuron further includes an activation function module arranged to generate a neuron output based on the second dot product engine output. The first dot product engine and the second dot product engine are structurally or functionally different.

Abstract: An all-analog natural language processing system is provided. Analog audio input is processed directly by an all-analog signal pathway wherein the audio activity detection, voice activity detection, feature extraction and neural network processing are all performed in the analog domain. Audio/voice detection and feature extraction is performed by a bandpass filter bank having a plurality of individual bandpass filters. Each bandpass filter includes an array of individual capacitively coupled current conveyor second order sections having a charge-trap transistor as a programmable element for tuning the passband of the filter. Compared to typical digital systems for natural language processing, the present all-analog system can perform natural language processing with comparable accuracy but greatly reduced energy consumption of up to two orders of magnitude less.

Abstract: There is provided with a data processing apparatus that carries out a computation corresponding to a neural network containing a plurality of layers. A processing unit includes a plurality of processors that, through pipeline processing, sequentially calculate data of each of blocks, each block corresponding to a part of a feature plane in one layer. A control unit determines a calculation order for the data of the blocks on the basis of structure information of the neural network, and sends a command that controls the calculation order to the plurality of processors.

Abstract: This application relates to computing circuitry (200), in particular for analogue computing circuitry suitable for neuromorphic computing. The circuitry (200) has a plurality of memory cells (201), each memory cell having an input electrode (201) for receiving a cell input signal and an output (203P, 203N) for outputting a cell output signal (IP, IN), with first and second paths connecting the input electrode to the output. The cell output signal thus depends on a differential current between the first and second paths due to the cell input signal. Each memory cell also comprises at least one programmable-resistance memory element (204) in each of the first and second paths and is controllable, by selective programming of the programmable-resistance memory elements, to store a data digit that can take any of at least three different values.

Abstract: There is provided with a data processing apparatus. An acquisition unit acquires feature plane data of a layer included in a neural network. A control unit outputs a first control signal corresponding to the layer for controlling first compression processing and a second control signal corresponding to the layer for controlling second compression processing. A first compression unit performs the first compression processing corresponding to the first control signal on the feature plane data. A second compression unit performs the second compression processing corresponding to the second control signal on the feature plane data after the first compression processing. A type of processing of the second compression processing is different from the first compression processing.

Abstract: The present disclosure relates to a neuron for an artificial neural network. The neuron includes: a first dot product engine operative to: receive a first set of weights; receive a set of inputs; and calculate the dot product of the set of inputs and the first set of weights to generate a first dot product engine output. The neuron further includes a second dot product engine operative to: receive a second set of weights; receive an input based on the first dot product engine output; and generate a second dot product engine output based on the product of the first dot product engine output and a weight of the second set of weights. The neuron further includes an activation function module arranged to generate a neuron output based on the second dot product engine output. The first dot product engine and the second dot product engine are structurally or functionally different.

Abstract: A product-sum operation device includes a product operator, a sum operator, and a malfunction determiner. The product operator includes a plurality of product operation elements (10AA) to (10AC), and each of the plurality of product operation elements (10AA) to (10AC) is a resistance change element. The sum operator includes an output detector that detects the sum of outputs from the plurality of product operation elements (10AA) to (10AC). The malfunction determiner determines that a malfunction has occurred when the sum detected by the output detector exceeds a specified value. The specified value is a value equal to or greater than a maximum value of the sum that can be detected by the output detector when the plurality of product operation elements (10AA) to (10AC) all operate normally.

Abstract: An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses. The synapses are configured to receive inputs and to generate therefrom outputs. Neurons are configured to receive the outputs. The synapses include a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the inputs by the stored weight values to generate the outputs.

Abstract: The present invention concerns a method of programming an analogue electronic neural network comprising a plurality of layers of somas. Any two consecutive layers of somas are connected by a matrix of synapses. The method comprises: applying test signals to inputs of the neural network; measuring at a plurality of measurement locations in the neural network responses of at least some somas and synapses to the test signals; extracting from the neural network, based on the responses, a first parameter set characterising the behaviour of the at least some somas; carrying out a training of the neural network by applying to a training algorithm the first parameter set and training data for obtaining a second parameter set; and programming the neural network by using the second parameter set. The invention also relates to the neural network and to a method of operating it.

Abstract: A system and method for controlling a non-tactile device including a receiving device configured to receive signals corresponding to a user's brain waves or movements, the brain waves or movements corresponding to a series of directional intentions, the intentions defining at least one line pattern, a processor configured to process the at least one line pattern, each of said at least one line patterns associated with an action of the device, and output a control signal to the non-tactile device related to the action.

Abstract: Facilitating energy-efficient wireless communications for advanced networks (e.g., 4G, 5G, and beyond) with low-resolution digital-to-analog converters is provided herein. Operations of a system can comprise determining first values. Respective values of the first values can be digital samples of transmission and reception chains determined based on symbols transformed from bits. The operations can also comprise facilitating a quantization of the first values resulting in second values. Facilitating the quantization can be based on a cost function associated with processing the first values. Further, the operations can comprise outputting the second values as a continuous time signal over antennas of a base station device. The second values can comprise fewer values than the first values.

Abstract: A method and apparatus for training a recognition model and a recognition method and apparatus using the model are disclosed. The apparatus for training the model obtains an estimation hidden vector output from a hidden layer of the model in response to an estimation output vector output from the model at a previous time being input into the model at a current time, and trains the model such that the estimation hidden vector of the current time matches an answer hidden vector output from the hidden layer in response to an answer output vector, corresponding to the estimation output vector of the previous time, being input into the model at the current time.

Abstract: Embodiments include methods and systems of neuron leaky integrate and fire circuit (NLIFC). Aspects include: receiving an input current having both AC component and DC component at an input terminal of the NLIFC, extracting AC component of input current, generating a number of swing voltages at a swing node using extracted AC component of the input current, transferring charge from a pull-up node to a neuron membrane potential (NP) node through an integration diode and a pull-up diode to raise a voltage at NP node over an integration capacitor gradually and the voltage at NP node shows integration value of AC component of input current, implementing leaky decay function of the neuron leaky integrate and fire circuit, detecting a timing of neuron fire using an analog comparator, resetting a neuron membrane potential level for a refractory period after neuron fire, and generating fire output signal of the NLIFC.

Abstract: CNN based digital IC for AI contains a number of CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem having first and second memories. The first memory includes an array of magnetic random access memory (RAM) cells for storing weights (e.g., filter coefficients) and the second memory contains SRAM for storing input signals (e.g., imagery data). The first memory may store one-time-programming weights. The memory subsystem may contain a third memory that contains magnetic RAM cells for storing one-time-programming data for security purpose. The magnetic RAM includes STT-RAM or OST-MRAM in SLC or MLC technology.

Abstract: CNN (Cellular Neural Networks or Cellular Nonlinear Networks) based digital Integrated Circuit for artificial intelligence contains multiple CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem having first and second memories. The first memory contains magnetic random access memory (MRAM) cells for storing weights (e.g., filter coefficients) while the second memory is for storing input signals (e.g., imagery data). The first memory may store one-time-programming weights. The memory subsystem may contain a third memory that contains MRAM cells for storing one-time-programming data for security purpose. The second memory contains MRAM cells or static random access memory cells. Each MRAM cell contains a Spin-Orbit-Torque (SOT) based magnetic tunnel junction (MTJ) element.

Abstract: CNN based digital IC for AI contains a number of CNN processing units. A first CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem, which includes a first one-time-programming (OTP) memory for filter coefficients and a second memory for imagery data. A second CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem that includes a first memory for filter coefficients, a second memory for imagery data and a third OTP memory for unique data pattern (e.g., security purpose). Either STT-RAM or OST-MRAM can be configured as different memories of the memory subsystem.

Abstract: Embedded memory subsystems in a digital integrated circuit for artificial intelligence are disclosed. A semi-conductor substrate contains CNN processing units. Each CNN processing unit includes CNN logic circuits and an embedded memory subsystem. The memory subsystem includes first embedded memory and second embedded memory. The first embedded memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area with a diameter in a range of 40-120 nm. The second embedded memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area having a diameter in a range of 30-75 nm.

Abstract: CNN (Cellular Neural Networks or Cellular Nonlinear Networks) based digital Integrated Circuit for artificial intelligence contains multiple CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem having first and second memories. The first memory contains magnetic random access memory (MRAM) cells for storing weights (e.g., filter coefficients) while the second memory is for storing input signals (e.g., imagery data). The first memory may store one-time-programming weights or filter coefficients. The memory subsystem may contain a third memory that contains MRAM cells for storing one-time-programming data for security purpose. The second memory contains MRAM cells or static random access memory cells. Each MRAM cell contains a voltage-controlled magnetic anisotropy (VCMA) based magnetic tunnel junction (MTJ) element. Magnetization direction in VCMA based MTJ element can be in-plane or out-of-plane.

Abstract: CNN based digital IC for AI contains a number of CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem. A first subsystem includes an array of first magnetic random access memory (RAM) cells for storing weights and an array of second magnetic RAM cells for storing input signals. A second subsystem includes an array of first magnetic RAM cells for storing one-time-programming weights and an array of second magnetic RAM cells for storing input signals. A third subsystem includes an array of first magnetic RAM cells for storing weights, an array of second magnetic RAM cells for storing input signals and an array of third magnetic RAM cells for storing one-time-programming unique data pattern for security identification. Either MLC STT-RAM or MLC OST-MRAM containing at least two MTJ elements can be configured as different memories for forming memory subsystem.

Abstract: CNN based digital IC for AI contains a number of CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem having first and second memories. The first memory includes an array of magnetic random access memory (RAM) cells for storing weights (e.g., filter coefficients) and the second memory contains SRAM for storing input signals (e.g., imagery data). The first memory may store one-time-programming weights. The memory subsystem may contain a third memory that contains magnetic RAM cells for storing one-time-programming data for security purpose. The magnetic RAM includes STT-RAM or OST-MRAM in SLC or MLC technology.

Abstract: A control circuit including a first switch to a third switch, an inverter, a first capacitor and a second capacitor. The first switch includes a first terminal receiving a weighting signal, and a second terminal. The second switch includes a first terminal, a control terminal coupled to the second terminal of the first switch, and a second terminal coupled to a reference voltage terminal. The third switch includes a first terminal coupled to the reference voltage terminal, a control terminal, and a second terminal. The inverter includes an input terminal coupled to a data input terminal, and an output terminal. The first capacitor is coupled between the data input terminal and the control terminal of the second switch. The second capacitor is coupled between the output terminal of the inverter and the control terminal of the third switch.

Abstract: A neuristor-based reservoir computing device includes support circuitry formed in a complimentary metal oxide semiconductor (CMOS) layer, input nodes connected to the support circuitry and output nodes connected to the support circuitry. Thin film neuristor nodes are disposed over the CMOS layer with a first portion of the neuristor nodes connected to the input nodes and a second portion of the neuristor nodes connected to the output nodes. Interconnections between the neuristor nodes form a reservoir accepting input signals from the input nodes and outputting signals on the output nodes. A method for forming a neuristor-based reservoir computing device is also provided.

Abstract: A synapse for a spike timing dependent (STDP) function cell includes a memory device having a variable resistance, such as a memristor, and a transistor connected to the memory device. A channel of the memory device is connected in series with a channel of the transistor.

Abstract: Embodiments of the invention relate to mapping neural dynamics of a neural model on to a lookup table. One embodiment comprises defining a phase plane for a neural model. The phase plane represents neural dynamics of the neural model. The phase plane is coarsely sampled to obtain state transition information for multiple neuronal states. The state transition information is mapped on to a lookup table.

Abstract: A neuromorphic data processing device comprising a plurality of spiking neurons, with each of these neurons comprising: an integrator designed to receive successive analog pulses each having a certain value, and accumulate the values of the pulses received in a recorded value, referred to as accumulation value, and a discharger designed to emit a pulse, referred to as discharge pulse, according to the accumulation value, and a silicon support having two surfaces, the neurons being carried out on at least one of the two surfaces, the integrator of each neuron comprising a metal via of the TSV type between the two surfaces of the silicon support, the metal via of the TSV type forming a capacitor with the silicon support and having an electric potential forming the accumulation value wherein the values of the pulses received are accumulated and according to which the discharge pulse is emitted.

Abstract: According to a technique, an electronic device is configured to correspond to characteristic features of a biological synapse. The electronic device includes multiple bipolar resistors arranged in parallel to form an electronic synapse, an axonal connection connected to one end of the electronic synapse and to a first electronic neuron, and a dendritic connection connected to another end of the electronic synapse and to a second electronic neuron. An increase and decrease of synaptic conduction in the electronic synapse is based on a probability of switching the plurality of bipolar resistors between a low resistance state and a high resistance state.

Abstract: According to a technique, an electronic device is configured to correspond to characteristic features of a biological synapse. The electronic device includes multiple bipolar resistors arranged in parallel to form an electronic synapse, an axonal connection connected to one end of the electronic synapse and to a first electronic neuron, and a dendritic connection connected to another end of the electronic synapse and to a second electronic neuron. An increase and decrease of synaptic conduction in the electronic synapse is based on a probability of switching the plurality of bipolar resistors between a low resistance state and a high resistance state.

Abstract: Disclosed is a method and system for analyzing a social network, the method comprising: segregating, by a processor, the social network into a plurality of groups of users, wherein each group of users has a unique identity in the social network; mining, by the processor, data from a group of users of the plurality of groups of users; identifying a plurality of social variables from the data, wherein the plurality of social variables comprises at least one of a number of users, connections of the users, interactions of the users, affinity of the users, or posts by the users; equating a social variable of the plurality of social variables with a thermodynamic variable of a plurality of thermodynamic variables; determining quantitative values of the plurality of thermodynamic variables based upon the plurality of social variables; generating a virtual thermodynamics system based upon the quantitative values for analyzing the social network.

Abstract: Disclosed is a system and method for Facilitating Credit Transactions, which may allow for the division of a given purchase or cash-withdrawal transaction amount, into periodical installments by enabling the financing of said transaction.

Abstract: Certain embodiments of the present disclosure support techniques for power efficient implementation of neuron synapses with positive and/or negative synaptic weights.

Abstract: A radiation-emitting device includes a first active semiconductor layer embodied for the emission of electromagnetic radiation and for direct contact with connection electrodes, and a second active semiconductor layer embodied for the emission of electromagnetic radiation and for direct contact with connection electrodes. The first active semiconductor layer and the second active semiconductor layer are arranged in a manner stacked one above another.

Abstract: Embodiments of the present invention include hybrid microscale-nanoscale neuromorphic integrated circuits that include an array of analog computational cells fabricated on an integrated-circuit-substrate. The analog electronic circuitry within each computational cell connected to one or more pins of a first type and to one or more pins of a second type that extend approximately vertically from the computational cells. The computational cells are additionally interconnected by one or more nanowire-interconnect layers, each nanowire-interconnect layer including two nanowire sublayers on either side of a memristive sublayer, with each nanowire in each nanowire sublayer of an interconnect layer connected to a single computational-cell pin and to a number of nanowires in the other nanowire sublayer of the interconnect layer.

Abstract: A method of modelling fabric properties and behavior first involves generating (16) a yarn model from fiber parameters, which may be empirically determined. The yarn model is homogenised (18, 20) to produce a homogenous representation of the yarn (YMM), suitable for use in finite element analysis. The method may then, secondly, involve generating (24) a fabric weave model by finite element analysis of the yarn representation (YMM). The fabric model is then also homogenised (26, 28) to produce a homogeneous representation of the fabric (FMM), suitable for use in finite element analysis. Finite element analysis of the fabric representation (FMM) can then be used to assess the suitability of various fabric materials for technical applications.

Abstract: A packet-network analyzer system for characterizing network conditions of a packet-network-under-test is provided. In this regard, one such system can be broadly summarized by a representative analyzer system that incorporates a data collection element to receive the raw digital data from a host analyzer, a data selection element to receive the raw digital data, a data processing element to process the selected data set to generate a normalized data set, a neural processing module to process the normalized data set to generate a set of rules and relationships, and a data mining module that uses the rules and relationships to generate a mined data set from the selected data set, the mined data set being used to characterize a packet-network-under test.

Abstract: A neuron element is provided having an input part that receives a plurality of input signals and, in response to the respective input signals, creates weighted signals as the products of the input signals and connection weights corresponding to the input signals, an addition part that obtains the total sum of the plurality of weighted signals, and an output part that outputs an output signal as a function of the total sum, a functional molecular element having a current-voltage characteristic in which the current flowing through the element is represented as a function having an inflection point with respect to the applied voltage is used as an element that defines the output signal, and the output signal is defined as a function of the total sum based on the current-voltage characteristic of this element in the region including the inflection point.

Abstract: We develop a system consisting of a neural architecture resulting in classifying regions corresponding to users' keystroke patterns. We extend the adaptation properties to classification phase resulting in learning of changes over time. Classification results on login attempts of 43 users (216 valid, 657 impersonation samples) show considerable improvements over existing methods.

Abstract: A graphical and interactive interface system manages risk management information. A secure database stores risk management information that is accessible by authorized access through a network. A graphics interface generates graphic data of the risk management information in response to the authorized access. One or more workflow process terminals connect in network with the database to provide updates to the risk management information. Summary reporting and statistical processing functionalities facilitate predictive accuracy of the system by permitting a user to compare relevant system inputs when selecting data to provide recommendations to customers for adjustment of insurance policies in accordance with risk management practices.

Abstract: A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0-11-(n?1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.

Abstract: A learning method of a semiconductor device of the present invention comprises a neuro device having a multiplier as a synapse in which a weight varies according to an input weight voltage, and functioning as a neural network system that processes analog data, comprising a step A of inputting predetermined input data to the neuro device and calculating an error between a target value of an output of the neuro device with respect to the input data and an actual output, a step B of calculating variation amount in the error by varying a weight of the multiplier thereafter, and a step C of varying the weight of the multiplier based on the variation amount in the error, wherein in the steps B and C, after inputting a reset voltage for setting the weight to a substantially constant value to the multiplier as the weight voltage, the weight is varied by inputting the weight voltage corresponding to the weight to be varied.

Abstract: A voltage-mode pulse width modulation (PWM) VLSI implementation of neural networks, comprising: a voltage-pulse converter for converting an input voltage into a neuron-state pulse; a synapse multiplier, including a multiplier cell for multiplying the neuron-state pulse by an input weight voltage and an integral and summation cell for integrating and summing up the multiplied output and producing a first output voltage; and a sigmoid circuit for converting the first output voltage into a second output voltage with the non-linear activation function of neuron.

Abstract: An analog neural computing medium, neuron and neural networks comprising same are disclosed. The neural computing medium includes a phase change material that has the ability to cumulatively respond to multiple synchronous or asynchronous input signals. The introduction of input signals induces transformations among a plurality of accumulation states of the disclosed neural computing medium. The accumulation states are characterized by a high electrical resistance that is substantially identical for all accumulation states. The high electrical resistance prevents the neural computing medium from transmitting signals. Upon cumulative receipt of energy from one or more input signals that equals or exceeds a threshold value, the neural computing medium fires by transforming to a low resistance state that is capable of transmitting signals. The neural computing medium thus closely mimics the neurosynaptic function of a biological neuron.

Abstract: A neural network includes a neuron, an error determination unit, and a weight update unit. The weight update unit includes an analog accumulator. The analog accumulator requires a minimal number of multipliers.

Abstract: An associative artificial neuron and method of forming output signals of an associative artificial neuron includes receiving a number of auxiliary input signals; forming from the auxiliary input signals a sum weighted by coefficients and applying a non-linear function to the weighted sum to generate a non-linear signal. The neuron and method further include receiving a main input signal and forming, based on the main signal and the non-linear signal, the function S OR V, which is used to generate a main output signal, and at lest one of three logical functions S AND V, NOT S AND V, and S AND NOT V. The at least one logical function is used to generate an additional output signal for the associative artificial neuron.

Abstract: A method and apparatus for using a neural network to process information includes multiple nodes arrayed in multiple layers for transforming input arrays from prior layers or the environment into output arrays for subsequent layers or output devices. Learning rules based on reinforcement are applied. Interconnections between nodes are provided in a manner whereby the number and structure of the interconnections are self-adjusted by the learning rules during learning. At least one of the layers is used as a processing layer, and multiple lateral inputs to each node of each processing layer are used to retrieve information. The invention provides rapid, unsupervised processing of complex data sets, such as imagery or continuous human speech, and captures successful processing or pattern classification constellations for implementation in other networks.

Abstract: A method for generating fault classification signals which identify faulty loops which develop in a multiphase energy supply network observed in the event of a fault from a protective device with a starting arrangement. To be able to generate such fault classification signals in a relatively simple manner, a neural network is used which is trained using input variables simulating faulty loops in the form of normalized resistance and reactance variables formed taking into consideration the starting characteristic of the starting arrangement. In the case of a fault, normalized resistance and reactance measured variables network for generating fault classification signals.

Abstract: A Hamming neural network circuit which can be programmed and expanded is disclosed. The Hamming neural network includes an I/O circuit for inputting and outputting a plurality of standard patterns. A bi-directional transmission gate array is connected to the I/O circuit and controlled by a programming signal for transmitting the standard patterns. A plurality of standard pattern memory units is connected to the bi-directional transmission gate array for storing the plurality of standard patterns respectively. An address decoder is connected to the plurality of standard pattern memory units for addressing one of the plurality of standard pattern memory units. A plurality of pattern matching calculation circuit units are respectively connected to the plurality of standard pattern memory units for generating a plurality of matching rates between a to-be-recognized pattern and the plurality of standard patterns.

Abstract: The invention comprises e-circuits built from basic modules of e-cells which are capable of: recognizing a previously memorized percept anywhere within an arbitrarily large input field without incurring delay related to size of the search space; isolating a previously memorized percept within the input field when in the adjacent presence of other percepts and closely related distractors; locating and recognizing all occurrences of a repeated subfield within the input field, even in the presence of closely related distractors; and performing sequential shift attention between a number of different percepts in the input field. The invention is applicable to various recognition tasks including those in sensory domains such as speech and music recognition, vision, olefaction, and touch.