Abstract: In one embodiment, a matrix operation may be performed using a plurality of input matrices, wherein the matrix operation is associated with one or more convolution operations. The plurality of input matrices may be partitioned into a plurality of input partitions, wherein the plurality of input matrices is partitioned based on a number of available processing elements. The plurality of input partitions may be distributed among a plurality of processing elements, wherein each input partition is distributed to a particular processing element of the plurality of processing elements. A plurality of partial matrix operations may be performed using the plurality of processing elements, and partial matrix data may be transmitted between the plurality of processing elements while performing the plurality of partial matrix operations. A result of the matrix operation may be determined based on the plurality of partial matrix operations.

Abstract: An apparatus and configuring scheme where a ferroelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the ferroelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and pull-down devices are turned on in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.

Abstract: Various embodiments comprise systems, methods, architectures, mechanisms or apparatus for providing programmable or pre-programmed in-memory computing operations.

Abstract: A product-sum operation device includes a product operator and a sum operator. The product operator includes a plurality of variable-input product operation elements and a plurality of fixed-input product operation elements. Each of the plurality of variable-input product operation elements and the plurality of fixed-input product operation elements and is a resistance change element. The product-sum operation device includes variable input units and that input a variable signal to a plurality of variable-input product operation elements and fixed input units and that input a determined signal to the plurality of fixed-input product operation elements and in synchronization with the variable signal. The sum operator includes an output detector that determines the sum of outputs from the plurality of variable-input product operation elements and outputs from the plurality of fixed-input product operation elements.

Abstract: The present disclosure describes a mixed signal arithmetic logic unit configured to use a combination of analog processing elements and digital processing elements in a cohesive manner. Depending on the signals and the data received for processing, the analog processing elements and digital processing elements may be used separately, independently or in combination to optimize computational results and the performance of the mixed signal arithmetic logic unit.

Abstract: A multiplying digital-to-analog converter (MDAC) includes an operational amplifier, a sampling capacitor circuit, a pre-sampling capacitor circuit, and a switch circuit. During a sampling cycle, the switch circuit connects a pre-defined voltage and reference voltages to the pre-sampling capacitor circuit, disconnects the pre-sampling capacitor circuit from an input port of the operational amplifier and the sampling capacitor circuit, disconnects an output port of the operational amplifier from the sampling capacitor circuit, and connects a voltage input to the sampling capacitor circuit.

Abstract: A method (10) is described for operating a system (12), for example a hydraulic or pneumatic system (12), in which a manipulated variable of an actuator element (16) can be controlled, and in which at least one variable (26) which is dependent on the manipulated variable of the actuator element (16) can be determined, wherein the manipulated variable of the actuator element (16) is modulated with a first periodic signal (22), and wherein a measurement signal (30) which characterizes the at least one variable (26) is evaluated using at least one second periodic signal (47).

Abstract: The goal of detecting modifications, such as unauthorized modifications for example, of the code and/or behavior of an embedded device (e.g., unexpected/unauthorized remote reprogramming, re-flashing), changes to code at run-time (e.g.

Abstract: This application relates to apparatus and methods for the multiplication of signals. A multiplication circuit (100) has first and second time-encoding modulators (103a, 103b) configured to receive first and second combined signals (SC1, SC2) respectively, and generate respective first and second PWM signals (SPWM1, SPWM2), each with a cycle frequency that depends substantially on the square of the value of the input combined signal. The first combined signal (SC1) corresponds to a sum of a first and second input signals (S1, S2) and the second combined signal (SC2) corresponds to the difference between the first and second input signals (S1, S2). First and second time-decoding converters (104a, 104b) receive the first and second PWM signals and provide respective first and count values (D1, D2) based on a parameter related to the frequency of the respective first or second PWM signal.

Abstract: In some aspects, a method for performing analog matrix inversion on a matrix with a network of resistive device arrays B, W, Q, and C is described. The method may include initializing arrays W, Q, B and C, updating the connections of array W in parallel and array Q in parallel until a predetermined condition is satisfied, and responsive to determining that the predetermined condition is satisfied, outputting an inverted matrix based on outputs from the connections of arrays B, W, Q, and C.

Abstract: Provided are apparatuses and methods, in which a disturbed measurement variable is converted to a digital signal. The digital signal is then averaged over a number of sampling values which corresponds to a period of the disturbances.

Abstract: A power fingerprinting system is adopted for assessing integrity of a target computer-based system. In one implementation, the power fingerprinting system may receive, at a first module, side-channel information of a first target component of a system, the first module being collocated with the first target component; obtain a power fingerprint for the first target component based on the side-channel information for the first target component, the power fingerprint for the first target component representing a plurality of execution statuses of the first target component; receive, at a second module, side-channel information of a second target component of the system, the second module being collocated with the second target component, the power fingerprint for the second target component representing a plurality of execution statuses of the second target component; and obtain a power fingerprint for the second target component based on the side-channel information for the second target component.

Abstract: An improved current limiting circuit including a switch having a first terminal and a second terminal, the first and second terminal configured to connect a power supply to a load. A first resistor connected in series between the first terminal and a first constant current source. A second resistor connected in series between the second terminal and a second constant current source. A control circuit configured to measure a voltage drop across the first resistor and compare the voltage drop to a voltage drop across the switch.

Abstract: The technology is a division circuit with decreased circuit area. An embodiment includes an integrated circuit implementing multiplicative division of a dividend input and a divisor input. The integrated circuit includes a lookup table circuit and multiplier circuits. The lookup table circuit providing an approximation of a reciprocal of a divisor input. The multiplier circuits receive the approximation and refine a quotient output of the dividend input and a divisor input. At least one of the multiplier circuits is a squaring circuit implementing multiplication with a reduced number of intermediate partial products. The reduced number of intermediate partial products prevent the squaring circuit from multiplication of any two unequal numbers and limiting the squaring circuit to multiplication of a same number by the same number.

Abstract: An efficient method and apparatus to compute a product of polynomials of degree n?1 where n is an arbitrary prime is provided. The total number of multiply operations and Arithmetic Logical Unit (ALU) operations to compute the product is minimized through the judicious use of polynomial evaluations at few points to decrease the number of multiplications while using only simple ALU operations.

Abstract: The present invention is a cryptoengine configured for providing countermeasures against attacks, including: an input/output (I/O) control unit, a memory, a controller, and an Arithmetic Logic Unit (ALU). The memory is communicatively coupled with the I/O control unit, receives inputs from the I/O control unit, and provides outputs to the I/O control unit based upon the received inputs. The controller is communicatively coupled with the I/O control unit for transmitting and receiving control signals. The ALU includes a plurality of storage components and computational components. The ALU is communicatively coupled with the controller and receives commands from/transmits status bits and flags to the controller. The ALU is further communicatively coupled with the memory and is configured for providing output signals to/receiving input signals from the memory. Further, the cryptoengine is configured for being communicatively coupled with a host computing device.

Abstract: Disclosed is a filter circuit, comprising a signal to be filtered, a difference circuit coupled to the signal to be filtered, a filter having an input coupled to the difference circuit, an integrator (or accumulator) having a first input coupled to an output of the filter circuit, and having a second input, and an accumulator coupled to an output of the integrator. A method of filtering is described also.

Abstract: An arithmetic apparatus for performing a long product-sum operation includes an integer unit arithmetic circuit, a finite field GF(2^m) based unit arithmetic circuit logically adjacent to the integer unit arithmetic circuit, a selector for selecting the integer unit arithmetic circuit or the finite field GF(2^m) based unit arithmetic circuit, and an adder circuit which has a buffer for storing interim result data, adds the interim result data to the result data obtained by one of the integer unit arithmetic circuit and the finite field GF(2^m) based unit arithmetic circuit which is selected by the selector, propagates a carry in an integer unit arithmetic operation, and propagates no carry in a finite field GF(2^m) based unit arithmetic operation.

Abstract: Methods and apparatus for converting a radix 2 multiplier to respective groups of radix 4 encoded bits representing numbers of the group consisting of ?2, ?1, 0, 1, 2, wherein the set of encoded bits includes: a first bit that is true when the associated number is 2, a second bit that is true when the associated number is ?2, a third bit that is true when the associated number is either negative or zero, and a fourth bit that is true when the associated number has an absolute value of 1.

Abstract: Scalable and unified multipliers for multiplication of cryptographic parameters represented as elements of either of the prime field (GF(p)) and the binary extension field (GF(2m)) include processing elements arranged to execute in pipeline stages. The processing elements are configurable to perform operations corresponding to either the prime field or the binary extension field. In an example, the processing elements include a dual-field adder having a field-select input that permits selection of a field arithmetic. In a representative example, multipliers are implemented as integrated circuits having processing units that each receive a single bit of one operand and partial words of the remaining operand.

Abstract: The coefficient matrix, corresponding to the simultaneous linear equations to be solved, is divided into a plurality of row sets. The row sets as divided are processed in a parallel fashion, and entries specifying the nonzero elements contained in the first to nth row sets are added to the entry sets E1 to En. Moreover, in regard to each row set, fill-ins which take place at the time of eliminating the ith variable are obtained in a parallel fashion, and entries specifying the fill-ins are added to the entry sets E1 to En. The coefficient matrix is compressed using those entry sets E1 to En.

Abstract: A tone detector includes at least one circuit (hereinafter “single phase reference matcher”) that not only performs a convolution of an input signal with a reference signal, but also compares the result of convolution with a threshold to determine if there is a match, and if so drives a signal active indicating that tone is present. If there is no match, another circuit (hereinafter “phase shifter”) delays the reference signal by a fraction (e.g. ⅛) of the measuring period, thereby to introduce a phase shift (e.g. &pgr;/8) between the input signal and the reference signal. The “single phase reference matcher” again performs the just-described operation, this time with a delayed reference signal, and repeats the operation as often as necessary (e.g. eight times) to cycle through the entire measuring period, thereby to ensure that tone (if present in the input signal) is detected irrespective of phase, during one of the operations.

Abstract: An apparatus for performing signed and unsigned multiplication is presented comprising a computation cell to generate a plurality of product terms, a compressor, coupled to the computation cell, and a selector coupled to each of the computation cell and the compressor. As disclosed, the selector selects and passes either a standard partial product term or an inverse thereof to the compressor, based on whether signed or unsigned multiplication is being performed, respectively, while the compressor compresses the received partial product terms into a pair of partial product terms.

Abstract: An inverse discrete-cosine transform apparatus that is simple in structure and can yet output pixel data items different in resolution. The apparatus comprises eight inverse discrete-cosine transform multipliers 23, ten field, compression, inverse discrete-cosine transform multipliers 22, eight selectors 24, eight selectors 25, eight buffers 26, eight sign multipliers 27, a control section, eight adders 28, and eight buffers 29. The control section controls the selectors 24, selectors 25, buffers 26 and sign multipliers 27 in accordance with whether the input discrete-cosine block has been subjected to field division and where the discrete-cosine coefficients are located in the block. One of the values input to the selectors 24, selectors 25, buffers 26 and sign multipliers 27 is thereby selected. The value selected is output after added with the plus sign or the minus sign. The adders 28 add the values output from the selectors 24, selectors 25, buffers 26 and sign multipliers 27.

Abstract: A signal reception apparatus in the spread spectrum communication system requires only a small amount of circuitry and consumes a small amount of electric power. A quadrature detector decomposes received signals into in-phase components and quadrature components, and supplies them to a complex-type matched filter. The complex-type matched filter de-spreads the in-phase components and the quadrature components and sends them to a multi-path selector. The multi-path selector selects, from among the received de-spread signals, multiple paths having high levels of signal electric powers and sends the received signals of the selected paths to multiple phase correction blocks. Analog operation circuits calculate phase errors of the received signals of two successive pilot symbol blocks for each path. An analog operation circuit corrects the phases of the received signals of the information symbol block that has been received between the two successive pilot symbol blocks.

Abstract: Circuitry which performs modular mathematics to solve the equation C=M.sup.k mod n and n is performed in a manner to mask the exponent k's signature from timing or power monitoring attacks. The modular exponentation function is performed in a normalized manner such that binary ones and zeros in the exponent are calculated by being modulo-squared and modulo-multiplied.