Slave Computer Locking Patents (Class 709/210)
  • Publication number: 20020004868
    Abstract: A parallel processing system includes a network and a plurality of nodes which communicates asynchronously between the plurality of nodes through the network. Each of the plurality of nodes may include a plurality of CPUs and a communication control unit. Each of the plurality of CPUs as an issuing CPU generates and transmits an asynchronous communication request, retransmits the asynchronous communication request in response to a non-acceptance reply, and executes a subsequent process in response to an acceptance replay. The communication control unit determines whether the asynchronous communication request is acceptable, returns the acceptance reply to the issuing CPU when the asynchronous communication request is acceptable, and the non-acceptance reply to the issuing CPU when the asynchronous communication request is not acceptable, and executes the asynchronous communication request.
    Type: Application
    Filed: July 5, 2001
    Publication date: January 10, 2002
    Applicant: NEC Corporation
    Inventor: Takashi Hagiwara
  • Patent number: 6292860
    Abstract: A deadlock-avoidance system for a computer. In a multi-bus, multi-processor computer, one processor may request a lock on a bus, to execute a locked cycle, thereby blocking all other processors, and other agents, from access to the bus. In addition, a conflicting agent may, in effect, lock a resource which is needed by the processor to complete the cycle for which the lock was requested. These two locks can create a deadlock situation which stalls the computer: the processor and the conflicting agent have each locked a resource needed by the other. Under the invention, when a locked cycle is requested by a processor, all other operations are suspended in the computer. Then queues standing in memory controllers are emptied. If a process requested by an agent occupies a resource, such as a bridge, required by the requested locked cycle, that resource is freed. Then the locked cycle is executed.
    Type: Grant
    Filed: December 16, 1997
    Date of Patent: September 18, 2001
    Assignee: NCR Corporation
    Inventors: Arthur F. Cochcroft, Jr., Edward A. McDonald, Byron L. Reams, Harry W. Scrivener, Bobby W. Batchler
  • Patent number: 6237028
    Abstract: A pair of data processing systems, each of the data processing system having a host central processor and an associated controller including memory, both of the data processing systems to be cooperatively associated with a number of disk drive memory units, each of the disk drive memory unit coupled to both said controllers. Either one of the host central processors can appropriate any one of the disk drive memory units as a selected disk drive memory unit by propagating path-control-data to the memory in both of the controllers and in the selected disk drive memory unit.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: May 22, 2001
    Assignee: Unisys Corporation
    Inventor: Gary Edward Jackson
  • Patent number: 6233704
    Abstract: A multiple counter-rotating ring computer network system having a permission control scheme for client isolation. The peripheral channel allows two rings to be folded into one longer ring so that faulty nodes can be effectively removed from the network. Or, any of the rings can be masked so that they are unoperational. The network system also allows several client isolation states ranging from complete isolation to master access. These types of isolation allow faulty client devices to be tested while maintaining a high-level of network security by configuring the client to an appropriate isolation state.
    Type: Grant
    Filed: March 13, 1996
    Date of Patent: May 15, 2001
    Assignee: Silicon Graphics, Inc.
    Inventors: Steven L. Scott, Steven M. Oberlin, Daniel L. Kunkel, Gerald A. Schwoerer
  • Patent number: 6209022
    Abstract: The communications system operates at two distinct operating modes. Each of the slave stations, which are controlled by a master station, has a first output circuit and a second output circuit. The two output circuits are connected to one another on the output side. In a first operating mode, the slave stations are identified by the master station, all the first output circuits can be activated and the system operates at a low clock rate. In a second operating mode, a transfer of data takes place, one of the second output circuits can be activated, and the system operates at a higher clock rate.
    Type: Grant
    Filed: December 10, 1997
    Date of Patent: March 27, 2001
    Assignee: Infineon Technologies AG
    Inventors: Karel Sotek, Söhnke Mehrgardt, Christine Born, Heinz Endriss, Timo Gossmann
  • Patent number: 6185563
    Abstract: In an client-server electronic filing system, the server performs check-in check-out management on documents that two or more clients share and restrains the check-out of the same document by two or more clients. Through the use of a check-in check-out table for check-in check-out management of documents that the clients share, the server prohibits the check-out of a document requested by a client until the document is checked in or until the check-out of the document is canceled, thereby preventing concurrent multiple updating of the same document by two or more clients.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: February 6, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yosuke Hino
  • Patent number: 6178439
    Abstract: A means of providing session control over the Internet is disclosed. Traditionally, the Internet protocols define a session between a client and a server as one page request and one page response. This does not permit the servers to ascertain how long a client is accessing a page or whether a page containing database information is being viewed by two clients simultaneously. In accordance with the present invention, a Web page contains a script that causes the page to send beat signals from the client to the server at particular times to indicate to the server that the client is continuing to view the page. When the client releases the page, the beat will stop and the server will know that the client has released the page.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: January 23, 2001
    Assignee: British Telecommunications Public Limited Company
    Inventor: Fil Feit
  • Patent number: 6133938
    Abstract: A system for implementing indivisible command execution in an AV/C home audio video network of connected network devices. A network bus operable for conveying commands among a plurality of coupled devices is coupled to each of the devices. A controller device is coupled to the network bus operable for generating a command sequence, the command sequence including a plurality of AV/C commands. A target device is coupled to the network bus, the target device operable for implementing AV/C operations by receiving and executing the command sequence. The target device is configured to identify the command sequence received from the controller via the network bus by reading a group tag field and a command status included in each AV/C command.
    Type: Grant
    Filed: March 11, 1999
    Date of Patent: October 17, 2000
    Assignees: Sony Corporation of Japan, Sony Electronics, Inc.
    Inventor: David V. James
  • Patent number: 6098134
    Abstract: A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E)ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. According to a feature of the invention, provision is made for split transactions, i.e., a read request which is not satisfied while the processor requesting it is still on the bus, but instead the bus is relinquished and other transactions intervene before the read result is available.
    Type: Grant
    Filed: December 31, 1996
    Date of Patent: August 1, 2000
    Assignee: Compaq Computer Corp.
    Inventors: Peter Michels, Christopher J. Pettey, Thomas R. Seeman, Brian S. Hausauer
  • Patent number: 6098095
    Abstract: A method by which a microprocessor based handheld multi-meter, or other handheld electronic instrument, can communicate with a computer or other microprocessor based device through the measurement input jacks of the handheld multi-meter. A handheld meter, thus equipped, can receive control or calibration data from, and provide test or calibration data to, a host computer or microprocessor based accessory or other instrument. To enable this capability, the handheld meter employs dual-signal, single-axis jacks, for example split banana jacks, for one or more of its signal and ground receptacles. The handheld meter and the computer, or another microprocessor based instrument or accessory device that the meter is to communicate with, are equipped with mutually compatible software and appropriate hardware to support single signal path communication.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: August 1, 2000
    Assignee: Tektronix, Inc.
    Inventors: Theodore G. Nelson, James R. Brooks, Warren Woo
  • Patent number: 6076126
    Abstract: A shared resource lock mechanism is provided which enables processors in a mullet-processor environment which each share common resources to obtain locks on those resources using a read modify write type transaction which does not at any point in time require the locking of a bus or a memory which contains the lock records used to lock the particular resources.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: June 13, 2000
    Assignee: EMC Corporation
    Inventor: Eli Shagam
  • Patent number: 6047222
    Abstract: Functional elements within a two-wire, loop-powered, two-way digital communications environment are interconnected using selective redundant connections and selective redundant functional elements. The redundant functional elements and redundant connections provide a smooth transition from operation of a primary process loop element to a secondary process loop element in the event of a failure of the primary process loop element. Redundancy is selectively implemented using a redundant pair of field devices or a redundant bus pair having a primary bus and a redundant bus. In a first case, redundancy is selectively implemented using a single set of communication media, such as a single communication loop, but implementing redundant functional elements, such as field devices, so that recovery is achieved upon failure of a functional element but not upon failure of the communication media.
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: April 4, 2000
    Assignee: Fisher Controls International, Inc.
    Inventors: Harry A. Burns, Brent H. Larson, Larry K. Brown
  • Patent number: 6006282
    Abstract: Host input to a shared application is blocked while a guest has input control. Patch instructions are written over keyboard and mouse event procedures, which are operating system subroutines defining the normal entry points to the system queue for host mouse and keyboard events generated by host-mouse and keyboard drivers. The patch instructions call a patch subroutine which were written into the host-executed application-sharing program. The patch subroutine is operable to determine whether the host has control to enter the mouse and keyboard events into the system queue. If the host is without input control, the patch subroutine drops the events and replaces the patch instructions to their prior position on the keyboard or mouse event procedures. If the host has input rights, the original keyboard or mouse event code is written over the patch instruction and returned for execution.
    Type: Grant
    Filed: December 1, 1995
    Date of Patent: December 21, 1999
    Assignee: Intel Corporation
    Inventors: William C. DeLeeuw, David L. Anderson