Peripheral Monitoring Patents (Class 710/15)
  • Patent number: 11188279
    Abstract: In an information processing apparatus and a method of controlling the same, settings for prohibiting an access to a removable medium is performed, and even if the setting is set, the access to the removable medium is permitted in a case where the information processing apparatus is activated in the maintenance mode.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: November 30, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yasuharu Sugano
  • Patent number: 11144358
    Abstract: An exemplary system includes first and second controllers each configured to selectively operate in a master state and a standby state, a first watchdog timer associated with the first controller, and a second watchdog timer associated with the second controller. Each watchdog timer is configured to be either unexpired or expired. Selectively, the first controller operates in the master state and the second controller operates in the standby state when the first watchdog timer is unexpired and the second watchdog timer is expired, the first controller operates in the standby state and the second controller operates in the master state when the first watchdog timer is expired and the second watchdog timer is unexpired, and the first and second controllers both operate in the standby state when both the first and the second watchdog timer are expired or when both the first and the second watchdog timer are unexpired.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: October 12, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Alexander Noble, Alex Gregory, Eric Kelly Blanchard
  • Patent number: 11138683
    Abstract: Provided are a consultation service apparatus of an automatic civic service system and an information processing method. A user holds an application document and identity credentials and operates a consultation service apparatus at a public area. The consultation service apparatus is connected to at least one business/institutional organization at a remote end through a network. The consultation service apparatus acquires image information of the application document and the identity credentials through an image scanner, confirms validity of the image information and performs service classification thereon, transmits the image information to a corresponding organization according to a classification result, and generates a certificate of completion for proof of completion of all procedures. By virtue of the automatic application submission mechanism, social cost can be reduced and working efficiency can be enhanced.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: October 5, 2021
    Assignee: AVISION INC.
    Inventors: Chieh-Yi Sung, Vamsi Krishna Neelam
  • Patent number: 11137733
    Abstract: A power system capable of detecting a foreign object, includes a power supplier side, a power receiver side, and a cable. The power supplier side includes a power converter, a foreign object detection and control circuit, and a pull-up circuit. The power converter supplies a supply voltage to the power receiver side according to a power supply control signal. The foreign object detection and control circuit generates the power supply control signal for controlling the power converter, and generates a foreign object detection and control signal according to a voltage at a supplier transmission node of the power supplier side, for determining whether a foreign object exists in the power receiver side. The pull-up circuit adjusts a level of a supply current which is supplied from the supplier transmission node to the power receiver side.
    Type: Grant
    Filed: May 24, 2020
    Date of Patent: October 5, 2021
    Inventors: Wei-Hsu Chang, Jung-Won Kim
  • Patent number: 11138141
    Abstract: A method may include executing basic input/output system (BIOS) instructions to initialize an information handling system. The initialization may include generating a hot-plug detect (HPD) override request. The method may further include receiving the HPD override request at a general purpose input/output (GPIO) device. In response to receiving the HPD override request, the GPIO may assert an active-low signal at an interconnect electrically connected to a HPD terminal of a graphics display receptacle, the receptacle for coupling a graphics processing unit to a graphics display device.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: October 5, 2021
    Assignee: Dell Products L.P.
    Inventor: Eric Sendelbach
  • Patent number: 11126287
    Abstract: A display device includes a substrate, first electrodes, pixel electrodes, a display functional layer, common electrodes, second electrodes stacked in this order. The display device further includes lines that are provided between the substrate and the display functional layer and intersect with the first electrodes in the plan view. In response to a control signal from a controller, the pixel electrodes are supplied with a pixel signal through the lines, and the common electrodes are supplied with a common signal in the display periods; either of the lines and the first electrodes are supplied with a first drive signal to generate a magnetic field, and the other thereof generate an electromotive force caused by the magnetic field in the first sensing period; the common electrodes are supplied with a second drive signal to generate electrostatic capacitance between the common electrodes and the second electrodes in the second sensing period.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: September 21, 2021
    Assignee: Japan Display Inc.
    Inventors: Hayato Kurasawa, Hiroshi Mizuhashi, Tadayoshi Katsuta
  • Patent number: 11126524
    Abstract: A machine learning system for configuring input devices connected to a computer cluster is provided. A computing device analyzes one or more input devices connected to one or more computer device executing within a workstation. A computer device receives one or more signals from the one or more input devices connected to the one or more computer devices executing within the workstation. A computing device converts the one or more signals from the one or more input devices connected to the one or more computer devices executing within the workstation into one or more device data. A computing device analyzes the one or more device data from the one or more input devices connected to the one or more computer devices executing within the workstation. A computer device determines a detected pattern of device data, wherein a computer device generates a key-mapping command.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: September 21, 2021
    Assignee: International Business Machines Corporation
    Inventors: Marco Aurelio Stelmar Netto, Thiago Rodrigues de Souza Costa, Diego P. R. Franco
  • Patent number: 11113070
    Abstract: Technologies are provided for automated identification of system devices to be disabled in a computing system and the disablement of the system devices during bootup of the computing system. In some embodiments, the computing system can execute a firmware configured to perform a bootup process of the computing system. The computing system includes multiple system devices. The firmware can generate program code for identifying a system device for disablement. The firmware can send the program code to a controller device curing the bootup process, where execution of the program code by the controller device generates data identifying one or several specific system devices to be disabled in the computing system. The firmware can then access such data from the controller device. Using the data, the firmware can determine that a specific system device to be disabled. The firmware can then disable that particular system device on a next bootup process.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: September 7, 2021
    Assignee: AMERICAN MEGATRENDS INTERNATIONAL, LLC
    Inventors: Igor Kulchytskyy, Manickavasakam Karpagavinayagam, Viswanathan Swaminathan, Chandrasekar Rathineswaran
  • Patent number: 11105856
    Abstract: Methods and systems of detecting chip degradation are described. A processor may execute a test on a device at a first time, where the test includes executable instructions for the device to execute a task under specific conditions relating to a performance attribute. The processor may receive performance data indicating a set of outcomes from the task executed by the device during the test. The processor may determine a first value of a parameter of the performance attribute based on the identified subset. The processor may compare the first value with a second value of the parameter of the performance attribute. The second value is based on an execution of the test on the device at a second time. The processor may determine a degradation status of the device based on the comparison of the first value with the second value.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: August 31, 2021
    Assignee: International Business Machines Corporation
    Inventors: Emily A. Ray, Emmanuel Yashchin, Peilin Song, Kevin G. Stawiasz, Barry Linder, Alan Weger, Keith A. Jenkins, Raphael P. Robertazzi, Franco Stellari, James Stathis
  • Patent number: 11108893
    Abstract: A field device includes components to communicate with a control and/or asset management system of a process control system or with other field devices using any of several different communication protocols such as several different internet protocol (IP) protocols. This architecture allows for a single version of a field device to be provided in automation or plant control systems that use any of these communication protocols, thus saving on inventory and product development costs. Moreover, the multi-protocol field device or a system using the multi-protocol field device can manage the asset (read and write parameterized data from and to the asset) using one protocol while at the same time communicating real-time process/factory automation information using a second and different protocol. Moreover, the field device may be able to communicate to other devices including other field devices and host devices using both of these protocols or other protocols for different purposes.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: August 31, 2021
    Assignee: FISHER-ROSEMOUNT SYSTEMS, INC.
    Inventors: Martin Zielinski, Donald R. Lattimer
  • Patent number: 11099822
    Abstract: A system and method for deploying a distributed component-based application is disclosed. The system may include a plurality of uniform base components. Each base component of the plurality of uniform base components may host a respective service component, and may include an input port, an output port, a service port, an error, log, and exception port, a monitoring port, and a control port. A first base component may process event messages asynchronously with a second base component and a third base component. The system and method may also support auto-scalability of each base component.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: August 24, 2021
    Assignee: Accenture Global Solutions Limited
    Inventor: Shivakumar Rudrappa Goniwada
  • Patent number: 11099754
    Abstract: An apparatus comprises at least one processing device comprising a processor coupled to a memory. The at least one processing device is configured to receive, via a multi-path layer of at least one host device, at least one indication of a predicted distribution of input-output operations directed from the at least one host device to a storage system for a given time interval. The at least one processing device is also configured to determine a cache memory configuration for a cache memory associated with the storage system based at least in part on the at least one indication of the predicted distribution of input-output operations for the given time interval. The at least one processing device is further configured to provision the cache memory with the determined cache memory configuration for the given time interval.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: August 24, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Sanjib Mallick, John Krasner, Arieh Don, Ramesh Doddaiah
  • Patent number: 11099760
    Abstract: Techniques for performing background refresh for storage devices using a timestamp from the host are described. In one example, a method involves receiving a timestamp from a host, storing the timestamp in a storage device, and determining a retention time for data stored in one or more blocks of the storage device based on the timestamp relative to a second timestamp indicating when the data was written to the one or more blocks. In response to determining the retention time exceeds a threshold, the storage device moves the data to one or more other blocks of the storage device, which can include interleaving the refresh writes with activity from the host.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: August 24, 2021
    Assignee: Intel Corporation
    Inventors: Shankar Natarajan, Ning Wu
  • Patent number: 11080283
    Abstract: Systems and methods for intelligently pre-fetching data for input controls are disclosed. In particular, the disclosed systems and methods predict whether an input control is likely to be edited and only pre-fetches data for the input controls that have a high likelihood of being edited. This way, the presently disclosed systems and methods not only reduce latency in displaying recommended data results for input controls that are likely to be edited but also reduces the number of calls made to the backend server to retrieve the data as the data is not retrieved for all rendered input controls, but only the ones that are likely to be edited.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: August 3, 2021
    Assignees: ATLASSIAN PTY LTD., ATLASSIAN INC.
    Inventors: Addo Wondo, Ahmed Saad, Geoff Sims, Penyo Atanasov, Shihab Hassan Hamid, Gaurav Awadhwal, Edison Rho, Gilmar Jose Alves de Souza, Jr.
  • Patent number: 11042304
    Abstract: A memory system includes first and second non-volatile memories and a memory controller respectively connected to the first and second non-volatile memories via first and second channels. The memory controller executes a first read operation of reading first data from the first non-volatile memory and a second read operation of reading second data from the second non-volatile memory in parallel in response to a first read request received from the outside, and sets a first transfer rate of the first channel to be lower than a second transfer rate of the second channel when a first time at which the first read operation is scheduled to be completed is earlier than a second time at which the second read operation is scheduled to be completed.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: June 22, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Mitsuru Anazawa
  • Patent number: 11016522
    Abstract: A digital microprocessor device (2) has: a central processing unit; a memory (8); and an output signal module (4). The output signal module comprises: a counter (6) arranged to count to a predetermined count value; and at least one comparator (10a, 10b, 10c) arranged to change an output signal (14a, 14b, 14c) from a first output state to a second output state when the counter reaches a predetermined comparator value. The output signal module is arranged to load automatically from the memory at least one parameter selected from the group comprising: the predetermined count value, the predetermined comparator value and the first output state or the second output state, without receipt of an instruction from the central processing unit.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: May 25, 2021
    Assignee: Nordic Semiconductor ASA
    Inventors: Rolf Ambühl, Vemund Kval Bakken, Fredrik Jakobsen Fagerheim
  • Patent number: 11016927
    Abstract: A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: May 25, 2021
    Assignee: INTERNATIONAL MICROSYSTEMS, INC.
    Inventor: Peter A. Schade
  • Patent number: 11009841
    Abstract: A method for initialising control data for a device comprises determining whether an identification value stored in a control storage location of the device has a first value or second value. When the identification value has the first value, space is allocated in the memory for storing the control data and an address of the allocated space in memory is written to a control data pointer storage location of the device. When the identification value has the second value, the allocation of space in memory is omitted and the control data pointer storage location comprises a preset address indicative of a location for storing the control data in local storage provided within the device.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: May 18, 2021
    Assignee: ARM Limited
    Inventors: Håkan Persson, Matthew Lucien Evans
  • Patent number: 11003445
    Abstract: A microprocessor for neural network computing having a mapping table, a microcode memory, and a microcode decoding finite-state machine (FSM) is disclosed. According to the mapping table, a macroinstruction is mapped to an address on the microcode memory. The microcode decoding FSM decodes contents which are retrieved from the microcode memory according to the address, to get microinstructions involving at least one microinstruction loop that is repeated to operate a datapath to complete the macroinstruction.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: May 11, 2021
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Jing Chen, Xiaoyang Li, Juanli Song, Zhenhua Huang, Weilin Wang, Jiin Lai
  • Patent number: 10986246
    Abstract: A remote management system includes: a user operation server; a remote maintenance server; and a connection server, the user operation server, the remote maintenance server, and the connection server being connected to each other via a network, the remote maintenance server including a processor that operates as a setting change receiving unit that receives a setting value change instruction for an image forming apparatus from a user via the user operation server, a first setting change detection unit that detects a changed setting value based on the setting value change instruction, a setting change informing unit that informs an administrator and a user-in-charge of the image forming apparatus of the changed setting value, and a setting change command sending unit that sends a command to change setting of the image forming apparatus to the image forming apparatus via the connection server.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: April 20, 2021
    Assignee: KYOCERA DOCUMENT SOLUTIONS INC.
    Inventors: Kazuki Nishikai, Takeshi Nakamura, Satoshi Goshima, Dukil Park, Yuichi Obayashi, Takumi Nakamura, Koki Nakajima, Yasuo Nakashima
  • Patent number: 10985940
    Abstract: An on-vehicle device for a driver monitoring system can be configured to be isolated from the vehicle bus while connected to the vehicle's OBD port. In a fully-isolated mode, the device only receives power and ground from the vehicle's OBD port and there is no other communication sent or received from the vehicle bus. In a passive mode, the device can obtain some information from the vehicle bus but does not request any information on the vehicle bus. The device may be undetectable on the vehicle bus. Optionally, the device receives commands via a communication interface to be switched among the three modes: fully active mode, fully isolated mode and passive mode. The commands may come from a server and may be communicated over the internet or over a cell network to a communication module on the device.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: April 20, 2021
    Assignee: Appy Risk Technologies Limited
    Inventors: William Ben Miners, Otman A. Basir, Jason Toonstra
  • Patent number: 10977763
    Abstract: An information processing device includes: a first processing unit that processes plural color signals at a time and outputs a processed plural color signals in parallel; a memory that temporarily stores the processed plural color signals outputted in parallel from the first processing unit; and a second processing unit that reads the processed plural color signals from the memory in order by a processable number at a time, the second processing unit being able to process a smaller number of color signals than the first processing unit at a time, wherein a reading speed from the memory is faster than a writing speed to the memory.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: April 13, 2021
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Masaki Nudejima, Tomoyuki Ono, Takayuki Hashimoto, Suguru Oue, Daiki Takazawa
  • Patent number: 10970238
    Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Rajesh M. Sankaran, David J. Harriman, Sean O. Stalley, Rupin H. Vakharwala, Ishwar Agarwal, Pratik M. Marolia, Stephen R. Van Doren
  • Patent number: 10956260
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a data region and a parity region. The I/O gating circuit is connected to the ECC engine and the memory cell array. The control logic circuit generates control signals by decoding a command received from a memory controller. The ECC engine is configured to a first parity data based on a first write data associated with a first command. The control logic circuit is further configured to adjust a first write timing to write the first parity data in the parity region based on a receiving timing of a second command successive to the first command and a reference time interval.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: March 23, 2021
    Inventors: Jaekoo Park, Younghun Seo
  • Patent number: 10915321
    Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Graziano Mirichigni, Corrado Villa, Luca Porzio, Chee Weng Tan, Sebastien Lemarie, Andre Klindworth
  • Patent number: 10904286
    Abstract: A computerized system and method to detect phishing cyber-attacks is described. The approach entails analyzing at least one displayable image of a webpage referenced by a URL associated with an email to ascertain whether the image, and thus the webpage and the email are part of a phishing cyber-attack.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: January 26, 2021
    Assignee: FireEye, Inc.
    Inventor: Rundong Liu
  • Patent number: 10896145
    Abstract: A communications control system is disclosed that includes a serial communications interface and a parallel communications interface for coupling a plurality of input/output modules with a control module. The serial communications interface is configured for connecting the plurality of input/output modules to the control module in parallel to transmit information between the plurality of input/output modules and the control module, and the parallel communications interface is configured for separately connecting the plurality of input/output modules to the control module to transmit information between the plurality of input/output modules and the control module, and to transmit information between individual ones of the plurality of input/output modules. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: January 19, 2021
    Assignee: BEDROCK AUTOMATION PLATFORMS INC.
    Inventors: James G. Calvin, Albert Rooyakkers, Pirooz Parvarandeh
  • Patent number: 10863256
    Abstract: One embodiment provides a pluggable optical line terminal (OLT) in a passive optical network (PON). The OLT can include an optical transceiver, a non-volatile storage device storing configurations of the pluggable OLT, and an autonomous boot module configured to access the configurations stored in the storage device when booting the pluggable OLT, thereby enabling plug-and-play operations of the pluggable OLT.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: December 8, 2020
    Assignee: Tibit Communications, Inc.
    Inventors: Edward W. Boyd, Jean-Christophe B. A. Marion
  • Patent number: 10824566
    Abstract: In a storage device according to the present invention, controllers each having a cache memory manage duplication of cache data. A storage device SD includes multiple controllers 1 each including a cache memory, and multiple storing units 21 used by the controllers and configured with logical volume 24 for being provided to a higher-level device 3. Each of the controllers, in a case where a paired destination controller forming a duplication pair is blocked, selects a new paired destination controller for each logical volume, forwards the cache data stored in the cache memory included in the own controller to the new paired destination controller, and stores the cache data in a cache memory included in the new paired destination controller to duplicate the cache data.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: November 3, 2020
    Assignee: HITACHI, LTD.
    Inventors: Takashi Kaga, Tomohiro Nishimoto
  • Patent number: 10802082
    Abstract: The methods and apparatus allow one user to test cable continuity using a wire-configurable directional connector. The methods and apparatus may transmit a first and second voltage pulse through a first and second wire of a cable under test, respectively, having a wire-configurable directional connector attached. Both voltage pulses travel through the wire-configurable directional connector. The first voltage pulse selectively leaves at least one of the second wire and a third wire of the cable under test and the second voltage pulse selectively leaves the third wire. The methods and apparatus may store a pre-determined pattern of a returning voltage pulse specific to the cable under test, and determine a state of the first, second, and third wires in response to receiving the first and second voltage pulses.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: October 13, 2020
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventor: Brent E. Davis
  • Patent number: 10789196
    Abstract: Efficient communication between storage controllers can be performed. A storage system includes one or more backend switches that connect a first processor, a second processor, and one or more storage devices to each other. Each backend switch identifies a destination of a frame by referring to the frame received from the first processor. In a case where the destination of the frame is the second processor, each backend switch translates a first address, included in the frame, for specifying a location on the second memory in an address space of the first processor, into a second address for specifying the location on the second memory in an address space of the second processor, and transfers the frame including the second address to the second storage controller.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: September 29, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Katsuya Tanaka, Kentaro Shimada, Akira Yamamoto, Sadahiro Sugimoto
  • Patent number: 10768841
    Abstract: Technologies for managing network statistic counters include a network interface controller (NIC) of a computing device configured to identify a statistic counter of and a software consumer associated with a received network packet and identify an active counter page as a function of the identified software consumer. The NIC is further configured to read a value of the statistic counter stored at a counter memory address of a corresponding counter identifier entry of the identified active counter page, increment a read value of the statistic counter, and write the incremented value of the statistic counter back to the counter memory address. Additionally, in response to detecting a notification triggering event, generating a notification message that includes a present value of the statistic counter and a present value of each of the other statistic counters of the active counter page, and transmit the generated notification message to the software consumer. Other embodiments are described herein.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: Linden Cornett, Chih-Jen Chang, Manasi Deval, Parthasarathy Sarangam, Naru D. Sundar, Padma Akkiraju, Alexander Nguyen
  • Patent number: 10747285
    Abstract: Examples disclosed herein relate to a device to provide a bounded voltage range. Examples include a device to acquire a request for a voltage from a sink. In examples, the device determines whether the voltage is to be supplied from a battery of a source. The device is to further determine a bounded voltage range to supply to the sink according to the request for voltage and a state of the battery.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: August 18, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Lee Atkinson, Chin-Ho Li
  • Patent number: 10733165
    Abstract: A method for traversing a node tree, having a root node and a hierarchy of child nodes, to a selected child node is described. A node identifier of the root node is determined by performing a hash function with at least a seed value for the node tree. Each child node of the hierarchy has a respective node identifier determined by performing the hash function with i) the seed value, ii) a node identifier of a parent node of the child node, and iii) a child index of the parent node. The selected child node's node identifier is determined by performing the hash function with i) the seed value, ii) the node identifier of the selected child node's parent node, and iii) the child index of the parent node for the selected child node. A retrieval of data stored at a location indicated by the node identifier of the selected child node is caused.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: August 4, 2020
    Assignee: WORKIVA INC.
    Inventors: MacLeod Broad, Joseph Strach, Mark Shaule
  • Patent number: 10728605
    Abstract: There are disclosed devices, system and methods for a control device that controls a media player of a computer. The control device includes a circuit and various actuators that can be used to control the player. The actuators may be located in a pattern to be and may be configured to be activated by being stepped on. The control device sends loop in, loop out and a loop clear commands to the player upon receiving signals from a loop actuator. It also sends first speed, a second speed, a third speed, and a speed clear commands to the player upon receiving signals from a speed actuator. It sends pause, play and a global reset commands to the player upon receiving signals from a play/pause actuator. It may send skip backward and skip forward commands to the media player upon receiving signals from skip backward or skip forward actuators.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: July 28, 2020
    Assignee: Utility Design, Inc.
    Inventors: Michael Wayne Jones, Quinn Kazuo Jones
  • Patent number: 10721145
    Abstract: The detection of network communication problems in networks that have multiple end nodes, and multiple transit nodes in between. One or more of the end nodes monitors one or more flows, creates associated flow information including performance information for each flow, and then reports the flow information. A system then estimates, for each of multiple flows within the network, a likely path that network traffic takes through that network. The system might then use performance information for each of the reported flows to identify at least one candidate problem network entity that is common amongst the estimated paths of the at least the subset of the plurality of flows.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: July 21, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Adrian Power, Peter John Hill
  • Patent number: 10705497
    Abstract: A power system capable of detecting a foreign object, includes a power supplier side, a power receiver side, and a cable. The power supplier side includes a power converter, a foreign object detection and control circuit, and a pull-up circuit. The power converter supplies a supply voltage to the power receiver side according to a power supply control signal. The foreign object detection and control circuit generates the power supply control signal for controlling the power converter, and generates a foreign object detection and control signal according to a voltage at a supplier transmission node of the power supplier side, for determining whether a foreign object exists in the power receiver side. The pull-up circuit adjusts a level of a supply current which is supplied from the supplier transmission node to the power receiver side.
    Type: Grant
    Filed: June 3, 2018
    Date of Patent: July 7, 2020
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Wei-Hsu Chang, Jung-Won Kim
  • Patent number: 10706178
    Abstract: According to one embodiment, a data processing apparatus includes an access controller configured to control access by a CPU to a processor. The access controller selects permission configuration information and an identifier table to be used for the access control using processor selection information output from the CPU, determines as intermediate identifier MID that corresponds to an access request identifier SPID output from the CPU using the selected identifier table, and determines accessibility of the CPU to the processor using the selected permission configuration information and the determined intermediate identifier MID.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasuhiro Sugita, Koji Adachi, Yoichi Yuyama
  • Patent number: 10701145
    Abstract: Technology is described for generating data output using message requests to a message queue. A plurality of message requests that are sent to the message queue may be detected. The message queue may be operated by a messaging service executing in a service provider environment. Message attribute information for the plurality of message requests may be identified. The plurality of message requests and corresponding message attribute information may be published as a data output. The data output may be processed by the service provider environment. Access to the data output may be provided for consumption of the message attribute information in the data output.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: June 30, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Zakiul Islam, Jesse Marcus Dougherty
  • Patent number: 10698817
    Abstract: A method includes measuring an initial voltage a bulk capacitor at a power supply, controlling a power factor correction circuit to disable charging of the bulk capacitor for a predetermined period of time, and measuring a final voltage at the bulk capacitor at completion of the period of time. The method further includes measuring a first average power provided to a load receiving power from the voltage converter, the load external to the power supply, and determining a capacitance of the bulk capacitor based on the initial voltage, the final voltage, and the first average power.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: June 30, 2020
    Assignee: Dell Products, L.P.
    Inventors: Padmanabh R. Gharpure, Mark A. Muccini, Lei Wang
  • Patent number: 10680846
    Abstract: Methods, systems and apparatuses are described to detect and resolve device configuration and/or communication incompatibilities (e.g. incompatible messages, improper addressing, malfunctions) for a communication protocol such as HDMI-CEC.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: June 9, 2020
    Assignee: Caavo Inc
    Inventors: Nino V. Marino, Pankaj Kashyap, Shankara R. Sundararajan, Vinod K. Gopinath, Sharath H. Satheesh, Ashish D. Aggarwal, Bitto Niclavose, Conrad Savio Jude Gomes
  • Patent number: 10673362
    Abstract: A P terminal that is connected to an armature coil, an LIN terminal for LIN communications, and an interface circuit are provided, and the interface circuit converts serial signals which are input from the P terminal and the LIN terminal into parallel signals and transmits scan test signals input from the P terminal and the LIN terminal to a digital circuit and transmits a scan test signal output from the digital circuit to the LIN terminal.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: June 2, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Akio Kamimurai, Katsuyuki Sumimoto
  • Patent number: 10671199
    Abstract: Provided is an input detection device capable of suppressing a change in detection sensitivity depending on a position. The input detection device includes: signal wirings having end portions, and arranged so as to extend in a first direction; drive electrodes each extending in a second direction crossing the first direction, and arranged in parallel to the first direction; a plurality of first switches arranged between the end portions of the drive electrodes and the signal wirings; a drive signal circuit supplying a drive signal to the end portions; and a selection circuit controlling the first switches in detecting proximity of an external object.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: June 2, 2020
    Assignee: Japan Display Inc.
    Inventor: Tadayoshi Katsuta
  • Patent number: 10666801
    Abstract: The present invention relates to a telephone call processing system and a method of processing telephone calls, and in particular to systems and methods that facilitate secure transmission and accurate identification of sensitive information spoken during a call between a caller and an agent such that the agent does not have access to the sensitive information. The methods of the present invention involve outputting scrambled, out-of-sequence and/or partitioned sub-sets of a spoken voice stream to one or more recognition agents, which identify elements of the sensitive information and return the identified elements to a call processor for un-scrambling, re-ordering and/or re-assembly by the call processor to produce the identified sensitive information.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: May 26, 2020
    Assignee: Syntec Holdings Limited
    Inventor: Colin Philip Westlake
  • Patent number: 10657022
    Abstract: The disclosure provides an input and output recording device and method, CPU and data read and write operation method thereof. The input and output recording device is provided between a central processor CPU and a peripheral, and is configured to record data read and write operations between the CPU and the peripheral, wherein the data read and write operations comprise a data read and write operation initiated by the peripheral and a data read and write operation initiated by the CPU; the input and output recording device is further configured to request the CPU to process the data read and write operation initiated by the peripheral, and upon receiving an instruction sent by the CPU, send a data packet of the data read and write operation initiated by the peripheral to the CPU.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: May 19, 2020
    Assignee: TSINGHUA UNIVERSITY
    Inventors: Leibo Liu, Ao Luo, Shaojun Wei
  • Patent number: 10649909
    Abstract: A device having a controller configured to execute a range crawler algorithm residing in firmware or hardware and a data table containing one or more range entries (RE's), where each of the RE's is part of a logical block address (LBA) span associated with a command instruction, and where each LBA span has one or more LBA ranges, and where each LBA range is made of one or more sequential LBA's. The device also includes a collision bitmap configured to store data associated with RE collisions between one or more LBA's and a command dispatcher configured to release selected LBA ranges that are not associated with a RE collision. The range crawler algorithm is configured to search the data table to detect collisions between the RE's.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: May 12, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Cory Lappi, Darin Edward Gerhart, Nicholas Edward Ortmeier, William Jared Walker
  • Patent number: 10642707
    Abstract: A method for indicating a status of a storage device to be implemented by a complex programmable logic device (CPLD) is provided. The CPLD is coupled to a connector for connection with the storage device, and to an LED. The method includes: in response to receipt of a signal set from a connector, determining whether the connector is connected with a storage device based on the signal set; when affirmative, identifying the storage device based on the signal set; operating in a mode corresponding to a result of identification; generating a determination result representing an operating status of the storage device based on the signal set; and outputting a control signal corresponding to the determination result to the LED.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: May 5, 2020
    Assignee: Mitac Computing Technology Corporation
    Inventor: Wei-Yi Lo
  • Patent number: 10635503
    Abstract: A system for controlling shared computing resources is provided including a semaphore for controlling concurrent access to one or more computing resources by one or more worker processing threads, the semaphore including a semaphore counter corresponding to vacancies of one or more computing resources and a semaphore queue for resource requests of the one or more worker processing threads waiting for the one or more computing resources. The semaphore is programmed and configured to decrement the semaphore counter when allocating one of the computing resources to one of the worker threads and configured to increment the semaphore counter when releasing one of the computing resources from one of the worker threads. The semaphore increments the queue of requests from the one or more worker threads if a request for resource access occurs when the counter of the semaphore counter is zero or less than zero.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 28, 2020
    Assignee: EMC IP Holding Company LLC
    Inventor: Vladimir Shveidel
  • Patent number: 10635511
    Abstract: A kernel update method, a computer program product and a computer device, where the computer device sets a first interface mapping table to be invalid such that an interface block stops sending a service request of a service application to a driver logic of a first driver logic block such that the first driver logic block temporarily stops providing a driver service for the service application, replaces the first driver logic block in the loadable kernel with a second driver logic block, and records, in a second interface mapping table, a correspondence of each interface in the interface block to a driver logic in the second driver logic block. Therefore, the second driver logic block executes a driver logic on a new service request from the interface block according to the second interface mapping table.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: April 28, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Ruilin Peng
  • Patent number: RE48835
    Abstract: Embodiments are directed towards a controller that provides individual network accessibility to a storage drive. The controller may include a first connector operative to couple with a storage-drive connector, a second connector operative to couple with a backplane connector of a multi-storage-drive chassis, memory, and processor. The controller may convert communication received through the first connector into an Ethernet protocol for output through the second connector, and convert communication received through the second connector into a storage-drive protocol for output through the first connector. A physical shape of the controller may fit adjacent to the storage-drive connector and occupy less space than is bounded by peripheral edges of an end of a separate housing of a storage drive coupled to the storage-drive connector. The controller may manage power provided to the storage drive and may coordinate with other controllers to manage power-up sequences of multiple storage drives.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: November 30, 2021
    Assignee: Rubrik, Inc.
    Inventors: Timothy Rex Martin, Jeffrey Douglas Hughes, Triantaphyllos Byron Rakitzis, Kiran V. Bhageshpur