Abstract: An aspect of the disclosure provides a method and an apparatus for a control interface in a virtual environment. For example, the method includes providing a graphical user interface (GUI) with a virtual environment picture of the virtual environment. The GUI includes a first graphical element and a second graphical element. The first graphical element is associated with a first control for a first virtual object and the second graphical element is associated with a second control for the first virtual object. The method further includes receiving a merge setting operation for the first graphical element and the second graphical element, and merging the first control and the second control into a third graphical element in response to the merge setting operation.

Abstract: A network interface device comprises a streaming data processing path comprising a first data processing engine and hubs. A first scheduler associated with a first hub controls an output of data by the first hub to the first data processing engine and a second scheduler associated with a second hub controls an output of data by the second hub. The first hub is arranged upstream of the first data processing engine on the data processing path and is configured to receive data from a first upstream data path entity and from a first data processing entity implemented in programmable circuitry via a data ingress interface of the first hub. The first data processing engine is configured to receive data from the first hub, process the received data and output the processed data to the second hub arranged downstream of first data processing engine.

Abstract: An overlap detection unit for a user station of a serial bus system. The overlap detection unit includes a collision detection block for detecting bus states on a bus of the bus system, in which, in order to transmit a message, bus states of user stations of the bus system are generated on the bus with a first physical layer in a first communication phase, and are generated with a second physical layer in a second communication phase, the second physical layer being different from the first physical layer. The collision detection block generates a signal whose value indicates whether or not the bus states in the second communication phase have a level that corresponds to an overlap of the first and second physical layers or an overlap of two second physical layers, and the collision detection block is designed to output the signal for the user station.

Abstract: Systems, methods, and apparatuses relating to performing logical operations on packed data elements and testing the results of that logical operation to generate a packed data resultant are described.

Abstract: The disclosure relates to a controller area network, CAN, unit and associated method and computer program. The CAN unit is configured to detect a transmit signal edge on a transmit signal for a CAN transceiver; detect a corresponding receive signal edge on a receive signal for a CAN controller of the CAN transceiver; and detect a collision on the CAN bus based on a propagation delay between the transmit signal edge and the corresponding receive signal edge.

Abstract: The disclosed technology is generally directed to firewalls. In one example of the technology, a first firewall is used such that communication is blocked from a first subsystem of a device upon boot of the device. The first firewall is enabled to be configured by secure code subsequent to boot such that code that is not secure code is prevented from configuring the first firewall. After configuration of the first firewall, based on the configuration, the first firewall is used to selectively allow the first subsystem access to the first memory based on ranges of addresses of the first memory configured as accessible to the first subsystem.

Abstract: Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats. A first one of these formats spreads the data in the block across a larger number of memory subarrays (a.k.a., memory array tiles—MATs) than a second format. In this manner, the data blocks stored in the first format can be accessed with lower latency than the blocks stored in the second format because more data can be read from the array simultaneously. In addition, since the data stored in the second format is stored in fewer subarrays, it takes less energy to read a block stored in the second format. Thus, a system may elect, on a data block by data block basis, whether to conserve power or improve speed.

Abstract: A serial data processing device includes an offset detector circuit and an offset calibration circuit. The offset detector circuit is configured to store a plurality of tokens, and to receive a first data signal from a host device, and to detect an offset in the received first data signal according to the plurality of tokens, in order to generate a calibration signal, in which each of the tokens includes at least one predetermined logic value, and numbers of the at least one predetermined logic value in each of the plurality of tokens are different. The offset calibration circuit is configured to calibrate the received first data signal according to the calibration signal, in order to generate a second data signal.

Abstract: A method for controlling color component processing for a decoder includes: obtaining a coded video bitstream, the video bitstream being coded from a source having a RGB color format; decoding, signaling information of a current coding unit (CU) in a segment of a current picture from the coded video bitstream, the signaling information includes prediction information of the current CU and a control signal for processing chroma components of the current CU in a prediction residual domain; determining, according to the control signal, residual information of the current CU, comprising: determining, according to the control signal, adaptive color transform (ACT) enablement information; and when the ACT enablement information indicates that ACT is used for the current CU, obtaining the residual information by converting residuals at YCgCo domain obtained from inverse transform to residuals at RGB domain; and reconstructing the current CU based on the residual information and the prediction information.

Abstract: An apparatus is described that includes an execution unit to execute a first instruction and a second instruction. The execution unit includes input register space to store a first data structure to be replicated when executing the first instruction and to store a second data structure to be replicated when executing the second instruction. The first and second data structures are both packed data structures. Data values of the first packed data structure are twice as large as data values of the second packed data structure. The execution unit also includes replication logic circuitry to replicate the first data structure when executing the first instruction to create a first replication data structure, and, to replicate the second data structure when executing the second data instruction to create a second replication data structure.

Abstract: An apparatus is described that includes an execution unit to execute a first instruction and a second instruction. The execution unit includes input register space to store a first data structure to be replicated when executing the first instruction and to store a second data structure to be replicated when executing the second instruction. The first and second data structures are both packed data structures. Data values of the first packed data structure are twice as large as data values of the second packed data structure. The execution unit also includes replication logic circuitry to replicate the first data structure when executing the first instruction to create a first replication data structure, and, to replicate the second data structure when executing the second data instruction to create a second replication data structure.

Abstract: An apparatus is described that includes an execution unit to execute a first instruction and a second instruction. The execution unit includes input register space to store a first data structure to be replicated when executing the first instruction and to store a second data structure to be replicated when executing the second instruction. The first and second data structures are both packed data structures. Data values of the first packed data structure are twice as large as data values of the second packed data structure. The execution unit also includes replication logic circuitry to replicate the first data structure when executing the first instruction to create a first replication data structure, and, to replicate the second data structure when executing the second data instruction to create a second replication data structure.

Abstract: Computing apparatus includes a host processor, which runs a virtual machine monitor (VMM), which supports a plurality of virtual machines and includes a cryptographic security software module. A network interface controller (NIC) links the host processor to a network so as to transmit and receive data packets from and to the virtual machines and includes a cryptographic security hardware logic module, which when invoked by the VMM, applies the cryptographic security protocol to the data packets while maintaining a state context of the protocol with respect to each of the virtual machines. Upon encountering an exception in applying the cryptographic security protocol, the NIC transfers the data packet, together with the state context of the cryptographic security protocol with respect to the given virtual machine, to the cryptographic security software module for processing.

Abstract: Dedicating hardware devices to virtual machines includes dedicating, by a hypervisor executing on a computer system, a set of hardware devices of the computer system to a first virtual machine of the hypervisor, the first virtual machine executing a guest operating system, and the set of hardware devices for use by the guest operating system in execution of the guest operating system, and dedicating network device hardware of the computer system to a second virtual machine of the hypervisor, the second virtual machine being a different virtual machine than the first virtual machine, wherein network communication between the guest operating system and a network to which the computer system is connected via the network device hardware occurs via the second virtual machine.

Abstract: Computing apparatus includes a host processor, which runs a virtual machine monitor (VMM), which supports a plurality of virtual machines and includes a cryptographic security software module. A network interface controller (NIC) links the host processor to a network so as to transmit and receive data packets from and to the virtual machines and includes a cryptographic security hardware logic module, which when invoked by the VMM, applies the cryptographic security protocol to the data packets while maintaining a state context of the protocol with respect to each of the virtual machines. Upon encountering an exception in applying the cryptographic security protocol, the NIC transfers the data packet, together with the state context of the cryptographic security protocol with respect to the given virtual machine, to the cryptographic security software module for processing.

Abstract: To provide enhanced operation of data storage devices and systems, various systems, apparatuses, methods, and software are provided herein. In a first example, a data storage device accumulates write data into a cache storage region prior to committing into an archive storage region and maintains a data structure that tracks the write data in the cache storage region. Responsive to receiving first write data into the cache storage region, the data storage device establishes first tracking elements in the data structure for the first write data in the cache storage region. Responsive to receiving second write data directed to storage locations overlapping the first write data, the data storage device accepts the second write data into the cache storage region and establishes second tracking elements in the data structure for the second write data in the cache storage region without modifying the first tracking elements.

Abstract: A claw-back request, received from an accelerator, is issued for an address line. While waiting for a response to the claw-back request, a cast-out push request with a matching address line is received. The cast-out push request is associated with a cache having a modified copy of the address line. A combined-response, associated with the cast-out push request, is received from a bus. Data associated with the modified copy of the address line is received from the cache. A claw-back response, with the data associated with the modified version of the address line, is issued to an accelerator.

Abstract: A data storage system may have a number of data storage devices that each have a non-volatile memory connected to a memory buffer. The memory buffer can consist of a map unit having a predetermined size. In receipt of a data sector into the map unit of the memory buffer, the data sector may be identified as a runt with a runt module connected to the memory buffer and the non-volatile memory. The runt module can generate and subsequently execute a runt handling plan to fill the size of the map unit before storing the filled map unit in the non-volatile memory.

Abstract: A computing device including: more than two Universal Serial Bus (USB) ports configured to be connected respectively to more than two mobile devices simultaneously; at least one processor coupled to the USB ports; and a memory storing instructions configured to instruct the at least one processor to reprogram, through the more than two USB ports, the more than two mobile devices simultaneously.

Abstract: Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats. A first one of these formats spreads the data in the block across a larger number of memory subarrays (a.k.a., memory array tiles—MATs) than a second format. In this manner, the data blocks stored in the first format can be accessed with lower latency than the blocks stored in the second format because more data can be read from the array simultaneously. In addition, since the data stored in the second format is stored in fewer subarrays, it takes less energy to read a block stored in the second format. Thus, a system may elect, on a data block by data block basis, whether to conserve power or improve speed.

Abstract: The disclosed computer-implemented method for improving quality of service within hybrid storage systems may include (1) monitoring a performance measurement of a hybrid storage system that includes first and second types of storage devices that handle I/O throughput in connection with an application, (2) determining, based at least in part on the monitored performance measurement, an approximate amount of the I/O throughput handled by the first type of storage device over a period of time, (3) determining, based at least in part on the approximate amount of I/O throughput, a rate at which the application is allowed to deliver subsequent I/O throughput to the hybrid storage system over a subsequent period of time, and then (4) regulating, based at least in part on the rate, the subsequent I/O throughput in connection with the application over the subsequent period of time. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A transfer apparatus includes first and second communication paths, an accepting unit, a registration unit, an acquisition unit, and a transfer unit. The accepting unit accepts a request for data. The registration unit detects and registers a range that has been specified for writing. The acquisition unit acquires the data from a memory controller via the first communication path in a case where the request is issued for a registered range, and acquires the data from the arbitration device via the second communication path in a case where the request is issued for an unregistered range. The transfer unit transfers the acquired data. In a case where a first range detected from the arbitration device overlaps at least a portion of or is adjacent to a second range, which has been registered, the registration unit combines the first and second ranges into a continuous range and registers the continuous range.

Abstract: Exemplary method, system, and computer program product embodiments for scalable data deduplication working with small data chunk in a computing environment are provided. In one embodiment, by way of example only, for each small data chunk, a signature is generated based on a combination of a representation of characters used in selecting data to be deduplicated. A c-spectrum of the small data chunk being a sequence of representations of different characters ordered by a frequency of occurrence in the small data chunk, and an f-spectrum of the small data chunk being a corresponding sequence of frequencies of the different characters in the small data chunk.

Abstract: Provided is a support device that supports easier data exchange between PLCs without relying on a type of a PLC of the other communication party. The support device includes: a first input unit for receiving information defining, on a data-by-data basis, variables for data handled by the first programmable logic controller; a second input unit for receiving a source program expressing processing executed on the first programmable logic controller using the defined variables; a third input unit for receiving information that identifies a type of a second programmable logic controller in association with a first variable; and a generation unit that generates the executable program using the information defining the variables and the source program. The generation unit adapts a data structure of first data secured in the memory in correspondence with the first variable in accordance with the type of the second programmable logic controller.

Abstract: PCIe devices and corresponding methods are provided wherein a length of data to be transferred is aligned to a multiple of a double word length.

Abstract: Subject matter disclosed herein relates to arrangements and techniques for sending messages directly among processing cores and directly among co-processors over a network-on-chip (NoC). More particularly, the present disclosure provides an Application Specific Integrated Circuit (ASIC) that includes processing cores coupled together with a NoC. Each processing core and co-processor includes two corresponding buffers. A first buffer is for sending messages and a second buffer is for receiving messages. Messages are sent from a processing core directly to another processing core through the NoC. Messages are also sent from a co-processor directly to another co-processor through the NoC.

Abstract: A finite state machine is provided that both serializes virtual GPIO signals and messaging signals and that deserializer virtual GPIO signals and the messaging signals. The finite state machine frames the serialized virtual GPIO signals and messaging signals into frames each demarcated by a start bit and an end bit.

Abstract: Implementations relate to a hybrid finite state machine that is based on a micro-coded processor and the use of look-up tables to implement combinational logic. Micro-coding is used to describe the state transitions of the FSM and look-up tables are used to determine the conditions for state transitions and to generate the outputs as a function of the state.

Abstract: In a switch node connected with an external control server, a high functional service protocol processing can be realized by utilizing a multi-route compatible switch and a network interface (NW I/F), which are prescribed by the PCI express. Specifically, in a system which is provided with a switch node and a control server, a plurality of CPUs having a great deal of memories and a plurality of extended NW I/Fs are connected by a multi-route compatible PCI express switch, to configure a switch port of the plurality of extended NW I/Fs. Load distribution transfer processing to the plurality of CPUs from the network interfaces is made possible. High-speed packet processing is realized through the multiple processing by using the plurality of CPUs. A high-speed switch node is provided in which a large-capacity flow table is configured with the software-based switch node by using a large-capacity memory space of the CPU.

Abstract: An apparatus is described that includes an execution unit to execute a first instruction and a second instruction. The execution unit includes input register space to store a first data structure to be replicated when executing the first instruction and to store a second data structure to be replicated when executing the second instruction. The first and second data structures are both packed data structures. Data values of the first packed data structure are twice as large as data values of the second packed data structure. The first data structure is four times as large as the second data structure. The execution unit also includes replication logic circuitry to replicate the first data structure when executing the first instruction to create a first replication data structure, and, to replicate the second data structure when executing the second instruction to create a second replication data structure.

Abstract: The present invention discloses a method for locating the reference frames of the reference lane on the transmitting data bus. The present invention addresses this object by disclosing a method whereby the relationship between the size of the reference frame transmitted over the reference lane and the width of the data bus is such that the reference frame is bit-shifted automatically until it is aligned with the data bus.

Abstract: Various aspects of a method and system for low-latency networking are provided. Latency requirements of traffic to be communicated along a network path comprising one or more Ethernet links may be determined. A maximum size of Ethernet frames utilized for communicating the traffic may be determined based on the latency requirements. The maximum size of the Ethernet frames may be determined based on a data rate of one or more Ethernet links along the network path. A single device may utilize different maximum packet sizes for different ports/links on which it communicates. One or more messages indicating the determined maximum size may be communicated among devices along the network path to coordinate maximum packet sizes.

Abstract: A method, non-transitory computer readable medium, and device that sends an outgoing storage device frame to a storage device, the outgoing storage device frame converted from an incoming storage device frame received from a host device based on a protocol supported by the storage device. An incoming host device frame is received from the storage device in response to the outgoing storage device frame. Whether an outgoing host device frame has been sent to the host device is determined, the outgoing host device frame converted from the incoming host device frame based on a protocol supported by the host device, wherein the protocol supported by the host device requires a different frame sequencing than the protocol supported by the storage device. A next incoming storage device frame received from the host device is retrieved when the outgoing host device frame is determined to have been sent to the host device.

Abstract: A computer-implemented data processing method comprises receiving information from a user computer concerning a desired output to be generated, adding the information concerning the desired output to be generated to a data structure, and adding additional information to the data structure concerning intermediate outputs to be generated. The information concerning the desired output to be generated is received at a host computer. The host computer is one of a plurality of host computers configured to collect and analyze data received from a plurality of source computers. The data structure represents a list of outputs to be generated by the plurality of host computers. The intermediate outputs are precursor inputs needed to generate the desired output. The additional information is added to the data structure based on the information received from the user computer and based on stored information.

Abstract: Embodiments relate to tagging in a MCU. An aspect includes assigning a command tag to a command by a tag allocation logic of the MCU. Another aspect includes sending the command and the command tag on a plurality of channels that are in communication with the MCU. Another aspect includes receiving a response tag comprising one of a data tag and a done tag corresponding to the command tag from each of the plurality of channels. Another aspect includes, based on receiving a data tag from each of the plurality of channels, determining that read data corresponding to the command is available.

Abstract: A method for receiving a single message includes a receiving communication adapter receiving a first sub-unit in a single message. A transmitting communication adapter partitions the single message into sub-units. The method further includes storing the first payload in the memory of a receiving device, appending a first completion code into the first sub-unit, and sending a first notification to a receiving entity of the first completion code. The receiving entity processes the first payload based on the first determination. The receiving communication adapter receives a second sub-unit of the multiple sub-units after the first payload is processed by the receiving entity. The method further includes storing the second payload in the memory of the receiving device. The receiving entity determines that the first sub-unit is completely stored based on the first completion code, and that the second sub-unit is completely stored based on a second completion code.

Abstract: Techniques are described to transmit commands to a display device. The commands can be transmitted in header byte fields of secondary data packets. The commands can be used to cause a target device to capture a frame, enter or exit self refresh mode, or reduce power use of a connection. In addition, a request to exit main link standby mode can cause the target enter training mode without explicit command to exit main link standby mode.

Abstract: A fieldbus gateway using a virtual serial fieldbus port and a data transmission method thereof are provided. By receiving a fieldbus frame containing target data through a virtual serial fieldbus port connected to a source device or a target device via a fieldbus gateway and sending another fieldbus frame containing the target data via other fieldbus port to target devices or source devices, the system and the method can provide two or more remote devices to control one controlled device at the same time. The invention also achieves the effect of using one virtual serial fieldbus port to transmit data between multiple source devices and target devices concurrently.

Abstract: A controller to which a second controller is connected arranges, based on predetermined integrated scenario information defining a first input region allotted for the controller and a second input region allotted for the second controller within data regions for packet input data, operation input data corresponding to an operation input from a user in the first input region, and data based on extended input data obtained from an extension apparatus in the second input region, generates packet input data, and transmits it to a device main unit.

Abstract: An integrated circuit for controlling a slave device is provided. The integrated circuit includes a pin, a micro-controller and an inter integrated circuit (I2C) bus controller coupled between the micro-controller and the pin. The I2C bus controller includes a transceiver unit coupled to the slave device via the pin, and an interface unit coupled between the transceiver unit and the micro-controller. The interface unit includes a start control register and a stop control register. The start control register provides a start signal to the slave device via the transceiver unit when the start control register is programmed by the micro-controller. The stop control register provides a stop signal to the slave device via the transceiver unit when the stop control register is programmed by the micro-controller. The micro-controller programs the stop control register according to an interrupt signal from the interface unit.

Abstract: A method for read pointer maintenance of a buffering apparatus, which is arranged to buffer data of a multi-tile encoded picture having a plurality of tiles included therein, includes the following steps: judging if decoding of a first tile of the multi-tile encoded picture encounters a tile boundary of the first tile; and when it is judged that the tile boundary of the first tile is encountered, storing a currently used read pointer into a pointer buffer, and loading a selected read pointer from the pointer buffer to act as the currently used read pointer.

Abstract: A memory device is provided. The memory device includes a preamble disable memory and a memory controller. The preamble disable memory is arranged to store preamble disable data. The preamble disable data includes an indication as to whether a read preamble should be enabled or disabled. In response to a read command, if the preamble disable data includes an indication that the read preamble should be enabled, the memory controller provides the read preamble. Alternatively, in response to the read command, if the preamble disable data includes an indication that the read preamble should be disabled, the memory controller disables the read preamble.

Abstract: A computer-implemented method that includes creating a master copy of a header for all packets of a data transmission event, the master copy including a plurality of intact constant header information, the plurality of intact constant header information being constant for all packets of the data transmission event, storing unique header information for all packets of the data transmission event, the unique header information including information unique to at least one packet of the data transmission event, tokenizing identities of each packet of the data transmission event to create a tokenized packet ID for each packet, and indexing the stored unique header information based on the tokenizing. According to the method, at packet read-time, unique header information associated with the packet is overlayed onto the master copy to create a unique packet.

Abstract: A data processing apparatus may include: a data conversion unit configured to designate one-transfer data as one transfer unit and designate a predetermined number of transfer units as one conversion unit when a plurality of input data sequentially input is converted into transfer data of which the number of bits is the same as that of a data bus having a predetermined number of bits, and the transfer data is sequentially transferred, and arrange the input data in the transfer data within the conversion unit. The data conversion unit may include: a data generation unit, a first data arrangement change unit, and a first data selection unit configured to sequentially select the changed data in which the position of the input data is changed by the first data arrangement change unit and output the selected changed data as the transfer data in the data conversion unit.

Abstract: A separable peripheral device includes a first module and a second module. The first module includes first connection ports and a first processing unit. The first processing unit is connected to the first connection ports. The first processing unit executes a first algorithm and connects to at least two of the first connection ports. The second module includes second connection ports and a second processing unit. One of the second connection ports is connected to one of the first connection ports to receive a current and a data generated from one of the first connection ports. The second processing unit is connected to the second connection ports to receive the data. The second processing unit executes a second algorithm for converting the data. The second processing unit sends the converted data to one of the second connection ports.

Abstract: Data transmission from a data storage device (DSD) to a host. Data is received from a volatile memory of the DSD in an ingress buffer of the DSD and the data from the ingress buffer is formatted into formatted data. A size of data buffered in the ingress buffer is compared to a frame ingress size for data to be buffered in the ingress buffer for a frame to be transmitted to the host. It is determined based on the comparison whether to buffer all of the formatted data for the frame in an egress buffer of the DSD before transmission to the host, or to transmit at least a portion of the formatted data for the frame to the host before all of the formatted data for the frame is received in the egress buffer.

Abstract: One exemplary embodiment is directed to a connector assembly. The connector assembly comprises a port having a media interface configured to interface with a storage device interface of a connector. The connector is attached to a segment of physical communication media. The connector also includes a storage device. The connector assembly also comprises a programmable processor configured to execute software that stores information to the storage device using a plurality of redundant storage operations by which a plurality of copies of the information is sequentially stored in the storage device.

Abstract: A converter member connects between an electronic device and a load media for transmitting data. The converter member includes a first plug and a second plug electrically connected with the first plug. The first plug is detachably connected to the electronic device, and the second plug is detachably connected to the load media. The first plug and the second plug are two different type plugs. The data from the load media is transmitted to the electronic device through the second plug and the first plug orderly.

Abstract: A system including a receiving module in a device and receiving samples of data transferred from a data source. A memory stores the samples and timestamps when the data was sampled. A host module builds a frame including the samples based on a first timestamp and a predetermined latency period between the first timestamp and a second timestamp in a descriptor of the frame. The second timestamp indicates a time when the frame is expected to be received by a MAC module. A transfer module transfers the frame to the MAC module according to the second timestamp. A detector module determines a margin of latency based on a difference between a time subsequent to when the frame is finished being built and a time when the frame is received at the MAC module. The detector module updates the first predetermined latency period based on the determined margin of latency.

Abstract: Partitioning of a variable length scatter gather list including a processor for performing a method that includes requesting data from an I/O device comprising an I/O buffer. The requesting includes initiating a subchannel. The method further includes determining whether the subchannel supports data divisions by requesting SSQD data from the I/O device and inspecting at least one bit in the SSQD data. A determination is made whether the requested data includes a metadata block in response to determining that the subchannel support data divisions. Also, the subchannel is notified that the requested data includes the metadata block in response to determining that the requested data includes the metadata block. A location of storage is identified in an SBAL in response to notifying the subchannel.