Data Compression And Expansion Patents (Class 710/68)
  • Patent number: 10346064
    Abstract: A technique manages compression based on host data initially residing on a source storage array. The technique involves providing, based on source segments of the host data while the host data initially resides on the source storage array, compressibility labels (or tags) that label the source segments of the host data. Each compressibility label indicates a projected compression level for a respective source segment of the host data. The technique further involves generating a compression profile based on the compressibility labels that label the source segments of the host data. The technique further involves providing, based on the compression profile, a compression tier configuration that defines a prearrangement of compression tiers on a target storage array that receives the host data from the source storage array, the prearrangement of compression tiers providing storage units of allocation having different predefined sizes.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: July 9, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Jeremy J. O'Hare, Guy Rososhansky
  • Patent number: 10310747
    Abstract: According to one embodiment, a device includes a determination unit, compression unit, selecting unit, write updating unit, writing unit. The determination unit determines whether to compress write data based on specific information. The specific information including at least one of the type, number of accesses, access frequency and importance level of the write data. The compression unit compresses the write data when determining to compress the write data. The selecting unit selects a write region for the write data in nonvolatile memory based on the specific information. The write updating unit updates the specific information. The writing unit writes compressed write data into the write region when determining to compress the write data. The writing unit writes uncompressed write data into the write region when not determining to compress the write data.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: June 4, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsutomu Owa, Masaki Miyagawa, Atsushi Kunimatsu, Mari Takada
  • Patent number: 10311022
    Abstract: Systems and methods may implement database technology using distributed logical unit repositories (DLURs). DLURs may use a database structure related to a specific logical unit such as a customer, employee, or the like. Information used in DLUR database structures may include data, database structure, functions, and the like that helps form a complete model for a logical unit. In one embodiment, queries to a system concerning entities can be answered immediately by accessing a database using DLURs, which obviates the need to consult a number of databases in parallel and greatly reduces memory and time required to provide the requested information.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: June 4, 2019
    Assignee: K2VIEW Ltd.
    Inventors: Einav Itamar, Achi Rotem
  • Patent number: 10306301
    Abstract: Apparatus and methods for premises gateway functions that integrate or unify functions typically distributed across multiple devices within a content-based network. In one embodiment, the out-of-band (OOB) signaling functionality normally provided in each of a set-top-box (STB) and digital video recorder (DVR) are unified into a common OOB (e.g., DOCSIS) capable premises gateway device, thereby obviating OOB tuners and related components from each device. In another variant, the premises gateway is adapted for all-IP operation, such as for use with IP-based computers and IP set-top boxes, etc. Fully unified variants are also disclosed, wherein the DVR and/or STB functions are physically integrated within the premises gateway.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: May 28, 2019
    Assignee: Time Warner Cable Enterprises LLC
    Inventors: Chris Cholas, William L. Helms, Louis Williamson, Jeffrey P. Markley
  • Patent number: 10296229
    Abstract: A storage apparatus according to one aspect of the present invention includes one or more storage devices and a storage controller. The storage controller separates an area of the storage device into an overwrite storage area and an append write storage area and manages the areas, and moves data between the overwrite storage area and the append write storage area. For example, less frequently updated data among write data from a host is moved to the append write storage area from the overwrite storage area. In a state where update data directed to the data stored in the append write storage area is received from a host, the storage controller compresses the update data and then performs append write of the compressed update data to the append write storage area.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: May 21, 2019
    Assignee: HITACHI, LTD.
    Inventors: Kenichi Sawa, Hisaharu Takeuchi
  • Patent number: 10289542
    Abstract: The present disclosure includes apparatuses and methods related to a memory device as the store to program instructions. An apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller, coupled to the array and the sensing circuitry is configured to receive a block of instructions including a plurality of program instructions. The memory controller is configured to store the block of instructions in the array and retrieve program instructions to perform logical operations on the compute component.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: May 14, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jason T. Zawodny, Kyle B. Wheeler, Richard C. Murphy
  • Patent number: 10262388
    Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: Saurabh Sharma, Abhishek Venkatesh, Travis T. Schluessler, Prasoonkumar Surti, Altug Koker, Aravindh V. Anantaraman, Pattabhiraman P. K., Abhishek R. Appu, Joydeep Ray, Kamal Sinha, Vasanth Ranganathan, Bhushan M. Borole, Wenyin Fu, Eric J. Hoekstra, Linda L. Hurd
  • Patent number: 10241680
    Abstract: Methods for estimating cost savings in a storage system using an external host system. One method includes accessing over a communication network data from a unit of storage of a data storage system, wherein each of the blocks of data is uncompressed. A plurality of blocks is parsed from the data. A plurality of fingerprints is generated from the blocks using a hash algorithm. A deduplication ratio is estimated for the plurality of blocks stored in the unit of storage using a hyperloglog algorithm and a first plurality of buckets compartmentalizing the plurality of blocks, wherein the first plurality of buckets is defined by precision bits of the plurality of fingerprints. An effective compression ratio is estimated for the plurality of blocks stored in the unit of storage using the hyperloglog algorithm and a second plurality of buckets compartmentalizing the plurality of blocks, wherein the second plurality of buckets is defined by ranges of compression ratios.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 26, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Ashutosh Datar, Rajat Sharma, Sandeep Karmarkar
  • Patent number: 10210340
    Abstract: A mobile device is provided. The mobile device comprises a storage device storing one or more files and a serial port for connecting the mobile device to a remote system. The mobile device further comprises a user interface allowing a user of the mobile device to select a file stored on the storage device such that when the mobile device is connected to the remote system via the serial port, the remote system can only access the selected file.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: February 19, 2019
    Assignee: BlackBerry Limited
    Inventors: Robert H. Wood, Maxime M. Matton, Christopher E. S. Pattenden
  • Patent number: 10157444
    Abstract: In accordance with one embodiment each page table entry maps a variable page size (per entry), if multiple continuous virtual pages map to contiguous physical pages. This may drastically reduce the number of translation lookaside buffer (TLB) entries needed since each entry can potentially map a larger chunk of memory, in some embodiments.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Abhishek R. Appu, Joydeep Ray, Altug Koker, Balaji Vembu, Prasoonkumar P. Surti, Kamal Sinha, Vasanth Ranganathan, Kiran C. Veernapu, Bhushan M. Borole, Wenyin Fu
  • Patent number: 10157010
    Abstract: An application processor and a mobile apparatus are provided. The application processor includes a memory device configured to store data based upon a plurality of address mapping formats, an address mapping table configured to store information on one of the address mapping formats to access the data, a system bus configured to generate a second address based upon a first address to access the data and the address mapping table and a data processing device configured to receive the data according to the second address through the system bus.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: December 18, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kyungah Jeong
  • Patent number: 10120692
    Abstract: A method of compressing a sequence of program instructions begins by examining a program instruction stream to identify a sequence of two or more instructions that meet a parameter. The identified sequence of two or more instructions is replaced by a selected type of layout instruction which is then compressed. A method of decompressing accesses an X-index and a Y-index together as a compressed value. The compressed value is decompressed to a selected type of layout instruction which is decoded and replaced with a sequence of two or more instructions. An apparatus for decompressing includes a storage subsystem configured for storing compressed instructions, wherein a compressed instruction comprises an X-index and a Y-index. A decompressor is configured for translating an X-index and Y-index accessed from the storage subsystem to a selected type of layout instruction which is decoded and replaced with a sequence of two or more instructions.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: November 6, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Sergei Larin, Lucian Codrescu, Anshuman Das Gupta
  • Patent number: 10061518
    Abstract: In one embodiment, a computer-implemented method includes building an available frame header queue (AFHQ). The AFHQ includes one or more headers, each header including one or more frame references being no more than a maximum count of frame references. Each of the one or more frame references of each of the one or more headers refers to an available frame. A frame request is received for one or more requested frames. One or more frame references are extracted, by a computer processor, from the AFHQ in response to the frame request. The extracting includes extracting from the AFHQ one or more requested headers including the one or more frame references referring to at least a portion of the one or more requested frames.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: August 28, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Hom, Harris M. Morgenstern, Steven M. Partlow, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 10061698
    Abstract: Aspects disclosed involve reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled write operations occur. A processor-based system is provided that includes a cache memory and a compression memory system. When a cache entry is evicted from the cache memory, cache data and a virtual address associated with the evicted cache entry are provided to the compression memory system. The compression memory system reads metadata associated with the virtual address of the evicted cache entry to determine the physical address in the compression memory system mapped to the evicted cache entry. If the metadata is not available, the compression memory system stores the evicted cache data at a new, available physical address in the compression memory system without waiting for the metadata. Thus, buffering of the evicted cache data to avoid or reduce stalling write operations is not necessary.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: August 28, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Christopher Edward Koob, Richard Senior, Gurvinder Singh Chhabra, Andres Alejandro Oportus Valenzuela, Nieyan Geng, Raghuveer Raghavendra, Christopher Porter, Anand Janakiraman
  • Patent number: 10013200
    Abstract: Described embodiments may provide methods and systems for receiving an input/output (I/O) request by a storage system having at least one storage volume. The I/O request has associated payload data. The I/O request is performed with early prediction compression by compressing a first portion of the payload data and determining whether one or more remaining portions of the I/O request should be processed in a compressed manner or an uncompressed manner based, at least in part, upon the results of compressing the first portion of the payload data.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: July 3, 2018
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Vladimir Shveidel, Kirill Shoikhet
  • Patent number: 10007605
    Abstract: A computing system to compress an array using hardware-based compression and to perform various instructions on the compressed array is generally described. The computing system may receive an instruction adapted to access an address in an array. The computing system may determine whether the address is compressible. If the address is compressible, then the computing system may determine a compressed address of a compressed array based on the address. The compressed array may represent a compressed layout of the array, where a reduced size of each compressed element in the compressed array is smaller than an original size of each element in the array. The computing system may access the compressed array at the compressed address in accordance with the instruction.
    Type: Grant
    Filed: September 20, 2015
    Date of Patent: June 26, 2018
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Yan Solihin
  • Patent number: 9990298
    Abstract: Techniques for caching results of a read request to a solid state device are disclosed. In some embodiments, the techniques may be realized as a method for caching solid state device read request results comprising receiving, at a solid state device, a data request from a host device communicatively coupled to the solid state device, and retrieving, using a controller of the solid state device, a compressed data chunk from the solid state device in response to the data request. The techniques may further include decompressing the compressed data chunk, returning, to the host device, a block of the data chunk responsive to the data request, and caching one or more additional blocks of the data chunk in a data buffer for subsequent read requests.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: June 5, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC
    Inventors: Lee Anton Sendelbach, Jeffrey S. Werning
  • Patent number: 9985655
    Abstract: Embodiments described herein include a computing system that permits partial writes into a memory element—e.g., a register on a processor. For example, the data to be written into the memory element may be spread across multiple sources. The register may receive data from two different sources at different times and perform two separate partial write commands to store the data. Embodiments herein generate an ECC value for each of the partial writes. That is, when storing the data of the first partial write, the computing system generates a first ECC value for the data in the first partial write and stores this value in the memory element. Later, when performing the second partial write, the computing system generates a second ECC value for this data which is also stored in the memory element.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dhivya Jeganathan, Dung Q. Nguyen, Jose A. Paredes, David R. Terry, Brian W. Thompto
  • Patent number: 9985656
    Abstract: Embodiments described herein include a computing system that permits partial writes into a memory element—e.g., a register on a processor. For example, the data to be written into the memory element may be spread across multiple sources. The register may receive data from two different sources at different times and perform two separate partial write commands to store the data. Embodiments herein generate an ECC value for each of the partial writes. That is, when storing the data of the first partial write, the computing system generates a first ECC value for the data in the first partial write and stores this value in the memory element. Later, when performing the second partial write, the computing system generates a second ECC value for this data which is also stored in the memory element.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dhivya Jeganathan, Dung Q. Nguyen, Jose A. Paredes, David R. Terry, Brian W. Thompto
  • Patent number: 9984091
    Abstract: In a compression processing storage system, using a pool of compression cores, the compression cores are assigned to process either compression operations, decompression operations, or decompression and compression operations, which are scheduled for processing. Only decompression operations are assigned to the plurality of compression cores having an idle status, where the idle status represents those of the plurality of compression cores that have yet to process any of the compression operations, decompression operations, and decompression and compression operations during a predetermined threshold period.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan Amit, Amir Lidor, Sergey Marenkov, Rostislav Raikhman
  • Patent number: 9954552
    Abstract: Technologies for performing low-latency decompression include a managed node to parse, in response to a determination that a read tree descriptor does not match a cached tree descriptor, the read tree descriptor to construct one or more tables indicative of codes in compressed data. Each code corresponds to a different symbol. The managed node is further to decompress the compressed data with the one or more tables and store the one or more tables in association with the read tree descriptor in a cache memory for subsequent use.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, Daniel F. Cutter, James D. Guilford, Kirk S. Yap
  • Patent number: 9952866
    Abstract: A method of compressing a sequence of program instructions begins by examining a program instruction stream to identify a sequence of two or more instructions that meet a parameter. The identified sequence of two or more instructions is replaced by a selected type of layout instruction which is then compressed. A method of decompressing accesses an X-index and a Y-index together as a compressed value. The compressed value is decompressed to a selected type of layout instruction which is decoded and replaced with a sequence of two or more instructions. An apparatus for decompressing includes a storage subsystem configured for storing compressed instructions, wherein a compressed instruction comprises an X-index and a Y-index. A decompressor is configured for translating an X-index and Y-index accessed from the storage subsystem to a selected type of layout instruction which is decoded and replaced with a sequence of two or more instructions.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: April 24, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Sergei Larin, Lucian Codrescu, Anshuman Das Gupta
  • Patent number: 9916248
    Abstract: The storage device of the present invention provides a decompression VOL having no corresponding relationship (mapping) with a final storage media to a superior device, and receives accesses from the superior device to the decompression VOL. Then, data written into the decompression VOL is compressed on-line in a cache memory, and the compressed data is mapped to a compression VOL which is a volume mapped to a final storage media. At the same time, by maintaining and managing a mapping information between an area in the decompression VOL where data has been written and a location in the compression VOL to which compressed data of the relevant data is mapped, when a read request is received from a superior device regarding the decompression VOL, the storage device converts a location information in the decompression VOL designated by the read request to a location information of the final storage media.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: March 13, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Sadahiro Sugimoto, Akira Yamamoto, Kazuei Hironaka
  • Patent number: 9916340
    Abstract: Data records may be managed in a relational database by monitoring, a record length for a first data record in a page of memory, an amount of free space in the page, and a page length. In response to receiving an operator command to replace the first data record with a second data record, a database management system may determine whether an estimated record length of a compressed second data record is outside of the amount of free space in the page. In response to determining the estimated record length of a compressed second data record is outside of the amount of free space in the page, the database management system may determine whether an estimated length of a compressed page is outside of the page length. In response to determining the estimated length of a compressed page is within the page length, the page may be compressed.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: March 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Min Fang, Di Jin, Zhen Yu Shi, Nigel G. Slinger, Shu Wang, Li Fei Zheng, Wen Jie Zhu
  • Patent number: 9917597
    Abstract: A processor includes a decoder to decode an instruction to compress an input data stream and an execution unit for executing the instruction. The execution unit to generate metadata for a current input of the input data stream, the metadata comprises a first hint based on a portion of a current input that represents the input data stream at a current offset, select a first pointer to identify a location in a history buffer in a hash chain, determine whether the metadata generated for the current input matches metadata previously generated for the first pointer, and filter the first pointer from a search for a best match for the current input in the history buffer based on the determination that at least a portion of the metadata for the current input does not match a portion of the metadata for the first pointer.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: March 13, 2018
    Assignee: Intel Corporation
    Inventors: Daniel F. Cutter, Vinodh Gopal, James D. Guilford
  • Patent number: 9910879
    Abstract: Data records may be managed in a relational database by monitoring, a record length for a first data record in a page of memory, an amount of free space in the page, and a page length. In response to receiving an operator command to replace the first data record with a second data record, a database management system may determine whether an estimated record length of a compressed second data record is outside of the amount of free space in the page. In response to determining the estimated record length of a compressed second data record is outside of the amount of free space in the page, the database management system may determine whether an estimated length of a compressed page is outside of the page length. In response to determining the estimated length of a compressed page is within the page length, the page may be compressed.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Min Fang, Di Jin, Zhen Yu Shi, Nigel G. Slinger, Shu Wang, Li Fei Zheng, Wen Jie Zhu
  • Patent number: 9898198
    Abstract: In one embodiment, a computer-implemented method includes building an available frame header queue (AFHQ). The AFHQ includes one or more headers, each header including one or more frame references being no more than a maximum count of frame references. Each of the one or more frame references of each of the one or more headers refers to an available frame. A frame request is received for one or more requested frames. One or more frame references are extracted, by a computer processor, from the AFHQ in response to the frame request. The extracting includes extracting from the AFHQ one or more requested headers including the one or more frame references referring to at least a portion of the one or more requested frames.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: February 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Hom, Harris M. Morgenstern, Steven M. Partlow, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 9841904
    Abstract: Embodiments of the inventive concept include a non-volatile memory module array system. The system can include non-volatile memory modules each including a first port, a second port, solid state drives, a switch, and a port configuration logic section. The system can include a bus connected to the first or second ports. The system can include a host to communicate with the non-volatile memory modules via the bus. The port configuration logic section can toggle between a first port configuration associated with the second port and a second port configuration associated with the second port. The port configuration logic section can include a first non-volatile configuration section to store the first and second port configurations associated with the second port. The first port configuration can cause the second port to operate as a downstream port. The second port configuration can cause the second port to operate as an upstream port.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: December 12, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Zhan Ping
  • Patent number: 9769241
    Abstract: A data transfer device calculates a compression performance value which represents a quantity of data that can be compressed per unit time and a transfer performance value which represents a quantity of data that can be transferred per unit time, and calculates, based on these values, a compression ratio which represents a ratio of data to be compressed and then transferred to total data to be transferred. The data transfer device extracts, from a storage unit which stores data, the data to be transferred, and then compresses part of the extracted data based on the compression ratio, and transfers the compressed data and remaining data to another device. The compression and transfer processes are performed in parallel.
    Type: Grant
    Filed: July 4, 2013
    Date of Patent: September 19, 2017
    Assignee: NEC CORPORATION
    Inventors: Masumi Ichien, Masaki Kan, Junpei Kamimura, Norihisa Iga
  • Patent number: 9769081
    Abstract: Some of the embodiments of the present disclosure provide a method comprising managing a plurality of buffer addresses in a system-on-chip (SOC); and if a number of available buffer addresses in the SOC falls below a low threshold value, obtaining one or more buffer addresses from a memory, which is external to the SOC, to the SOC. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: September 19, 2017
    Assignee: Marvell World Trade Ltd.
    Inventors: Alon Pais, Nafea Bishara
  • Patent number: 9753811
    Abstract: Methods, devices and systems to make compressed backup copies of in-use compressed database indices are described. In general, an “oldest” time at which index pages in working memory had been updated is identified. Compressed index pages may be directly copied without the need to bring them into working memory or uncompressing them. The identified “oldest” time is then associated with the compressed backup copy. In some embodiments, an entire compressed backup copy may be associated with a single point in time (e.g., the identified “oldest” time). In other embodiments, a compressed backup copy may be associated with multiple points in time (e.g., one time for each portion of the compressed index that is being backed-up). Compressed indices copied in accordance with the invention may be used during restore operations to reconstruct database indices using the identified “oldest” time and database log files.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: September 5, 2017
    Assignee: BMC Software, Inc.
    Inventors: Thomas G. Price, Richard Cline
  • Patent number: 9734081
    Abstract: A compute server accomplishes physical address to virtual address translation to optimize physical storage capacity via thin provisioning techniques. The thin provisioning techniques can minimize disk seeks during command functions by utilizing a translation table and free list stored to both one or more physical storage devices as well as to a cache. The cached translation table and free list can be updated directly in response to disk write procedures. A read-only copy of the cached translation table and free list can be created and stored to physical storage device for use in building the cached translation table and free list upon a boot of the compute server. The copy may also be used to repair the cached translation table in the event of a power failure or other event affecting the cache.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: August 15, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Sean Lie
  • Patent number: 9710324
    Abstract: A dual in-line memory module (DIMM) supporting storage of a data indicator(s) in an error correcting code (ECC) storage unit dedicated to storing an ECC. The DIMM is configured to provide a burst ECC storage unit striped in a burst data storage unit. The DIMM is configured to stripe a received burst data word across a burst data word storage unit at a write data address for a write operation. The DIMM is also configured to stripe a received burst ECC word for the burst data word across the burst ECC storage unit at the write data address in fewer bits than a number of data bit cells in the burst ECC storage unit. In this manner, the DIMM can store at least one data indicator for a burst data word in an extra, leftover bit(s) in the burst ECC storage unit.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: July 18, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Michael Raymond Trombley
  • Patent number: 9665385
    Abstract: A storage system for simulation virtual shelves with physical storage shelves is disclosed. The storage system contains a management daemon configured to perform tasks relating to one or more virtual shelves in response to a request for a simulation test, where each physical storage shelf having one or more physical disks. It contains a simulation daemon providing a virtual shelf configuration information to the management daemon when the management daemon interacts with the one or more virtual shelves in response to the request. The storage system also contains a disk driver configured to interface the physical storage shelves with the management daemon. It further contains a simulation driver configured to, in response to the request for a simulation test, process instructions to and from the disk driver and the simulation daemon to simulate access to the one or more virtual shelves, without having to utilize multiple physical storage shelves.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 30, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Vy Nguyen, Yiqiang Ding, Venkata Ratnam Tatavarty, Zhongjie Wu
  • Patent number: 9606750
    Abstract: A method of storing data in a distributed manner based on data compression ratio prediction, and a mass storage device and system using the method are disclosed. The device includes a compression ratio predicting unit, a compressing unit, and a control unit. When an address and first unit sized data are received, the compression ratio predicting unit estimates the predicted compression ratio of the first unit sized data. The compressing unit generates compressed data. The control unit calculates the benefit of compression based on at least the estimated predicted compression ratio, stores the compressed data in a first storage area if the calculated benefit of compression is higher than a predetermined benefit threshold value, and stores the first unit sized data in the second storage area if the calculated benefit of compression is equal to or lower than the predetermined benefit threshold value.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: March 28, 2017
    Assignee: Research and Business Foundation Sungkyunkwan University
    Inventors: Eui Seong Seo, Bon Keun Seo, Hyeon Hwa Kim
  • Patent number: 9600317
    Abstract: Techniques for checking the compressibility of a memory page that is allocated to a virtual machine (VM) running on a host system are provided. In one embodiment, the host system can determine a compression ratio for the memory page by compressing the memory page using a first compression algorithm. The host system can then compare the compression ratio to a threshold. If the compression ratio does not exceed the threshold, the host system can predict that the memory page is compressible by a second compression algorithm that is distinct from the first compression algorithm. On average, the second compression algorithm can be slower, but achieve a lower compression ratio, than the first compression algorithm.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: March 21, 2017
    Assignee: VMware, Inc.
    Inventors: Fei Guo, Praveen Yedlapalli
  • Patent number: 9569474
    Abstract: A data storage subsystem having a plurality of data compression engines configured to compress data, each having a different compression algorithm. A data handling system is configured to determine a present rate of access to data; select at least one sample of data; determine the greatest degree of compression of said data compression engines; determine the compression ratios of the operated data compression engines with respect to the selected sample(s); compressing said selected at least one sample with a plurality of said data compression engines at said selected tier; operate a selected data compression engines with respect to the selected sample and determine the greatest degree of compression of the data compression engines; compress the data from which the sample was selected with one of the operated data compression engines determined to have the greatest degree of compression; and store the compressed data in data storage repositories.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael R. Groseclose, Larry Juarez, David Montgomery, Jason L. Peipelman, Joshua M. Rhoades
  • Patent number: 9564919
    Abstract: Data records may be managed in a relational database by monitoring, a record length for a first data record in a page of memory, an amount of free space in the page, and a page length. In response to receiving an operator command to replace the first data record with a second data record, a database management system may determine whether an estimated record length of a compressed second data record is outside of the amount of free space in the page. In response to determining the estimated record length of a compressed second data record is outside of the amount of free space in the page, the database management system may determine whether an estimated length of a compressed page is outside of the page length. In response to determining the estimated length of a compressed page is within the page length, the page may be compressed.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Min Fang, Di Jin, Zhen Yu Shi, Nigel G. Slinger, Shu Wang, Li Fei Zheng, Wen Jie Zhu
  • Patent number: 9514056
    Abstract: Disclosed herein is a virtual memory system including a nonvolatile memory allowing random access, having an upper limit to a number of times of rewriting, and including a physical address space accessed via a virtual address; and a virtual memory control section configured to manage the physical address space of the nonvolatile memory in page units, map the physical address space and a virtual address space, and convert an accessed virtual address into a physical address; wherein the virtual memory control section is configured to expand a physical memory capacity allocated to a virtual page in which rewriting occurs.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: December 6, 2016
    Assignee: Sony Corporation
    Inventor: Kenichi Nakanishi
  • Patent number: 9513810
    Abstract: A computerized data storage system includes at least one storage device including a nonvolatile writable medium; a cache memory and a data management controller and a storage port. The storage port is operable to receive a request to read data, and, in response to the request to read data, to send the data stored in the data storing area of the cache memory. The storage port is further operable to receive a request to write data, and, in response to the request to write data, to send the write data to the data storing area of the cache memory. The storage system further includes a thin provisioning controller operable to provide a virtual volume, and a capacity pool. The storage system further includes a data compression controller and a data decompression controller.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: December 6, 2016
    Assignee: Hitachi, Ltd.
    Inventor: Tomohiro Kawaguchi
  • Patent number: 9400754
    Abstract: Embodiments of the invention relate to mitigating page eviction from cache memory. Pages of data in the cache are compressed, and are periodically swapped to a physical storage device to create space in the cache for additional pages. To avoid the impact of eviction latencies, an asynchronous thread scanning process scans the cache for any pages that are not committed to the storage device, decompresses a selected one of the pages, and asynchronously writes the decompressed page copy to the physical storage device. The compressed copy of the selected page remains in the cache during the asynchronous write with an indicator for the page set to convey that a replica of the page has been written to physical storage, allowing for efficient eviction from the in-memory pool at a later time.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: July 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jenifer Hopper, Mark A. Peloquin, Steven L. Pratt, Karl M. Rister
  • Patent number: 9369754
    Abstract: Disclosed is an apparatus and method to determine usage rules for video content by buffer tracking. A computing device may include a secure processor configured to: store digital rights management (DRM) rules associated with a DRM key and usage rules for a session; command a cryptoprocessor to decrypt video content with the DRM key and to log an output buffer designation of the command to decrypt the video content. The secure processor may command a buffer tracking table to store the output buffer designation of the cryptoprocessor of the command to decrypt and the associated usage rules and a plurality of input and output buffer designations from a plurality of video content drivers, such that, based upon a buffer designation from an output driver to display video content received by the secure processor, the secure processor may determine usage rules to be applied to the decrypted video content for display.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: June 14, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Ron Keidar, Chenxi Zhang
  • Patent number: 9361097
    Abstract: A microprocessor includes one or more memories configured to hold microcode instructions, wherein at least a portion of the microcode instructions are compressed. The microprocessor also includes a decompression unit configured to decompress the compressed microcode instructions after being fetched from the one or more memories and before being executed. A method includes receiving from a memory a first N-bit wide microcode word, determining whether or not a predetermined portion of the first N-bit wide microcode word is a predetermined value, if the predetermined portion is not the predetermined value, decompressing the first N-bit wide microcode word to generate an M-bit wide microcode word, and if the predetermined portion is the predetermined value, receiving from the memory a second N-bit wide microcode word and joining portions of the first and second N-bit wide microcode words to generate the M-bit wide microcode word.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: June 7, 2016
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: G. Glenn Henry, Terry Parks, Brent Bean
  • Patent number: 9355108
    Abstract: A mechanism is provided for storing data files in a file system. The file system provides a plurality of reference data files, where each reference data file in the plurality of data files represents a group of similar data files. The mechanism creates a new data file and associated the new data file with one reference data file in the plurality of data files thus defining an associated reference data file of the plurality of reference data files. The mechanism informs the file system about the association of the new data file with the associated reference data file. The mechanism compresses the new data file using the associated reference data file thereby forming a compressed data file. The mechanism stores the compressed data file together with information about the association of the new data file with the associated reference data file.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 31, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jens-Peter Akelbein, Nils Haustein
  • Patent number: 9354812
    Abstract: Various embodiments of methods and systems for dynamically managing the capacity utilization of a memory component in a system on a chip (“SoC”) are disclosed. Memory utilization is optimized in certain embodiments through dynamic compression and decompression within a memory subsystem. Based on parameters of the SoC that are indicative of a quality of service (“QoS”) level, a memory controller may determine that the format of the data in a write request should be converted and stored in a relinked memory address. Subsequently, a primary memory address associated with the data may be released for storage of different data. Similarly, embodiments may return data requested in a write request in a format different than that which was requested.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: May 31, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Steven Der-Chung Cheng, Vinay Mitter
  • Patent number: 9356985
    Abstract: A method, system, and computer program product for deploying data to a web server for streaming video to a mobile device. The method can include receiving a request for streaming video from a mobile device upon the resolving of the request by a DNS. The method can further include simultaneously sending both a request to a database for the video requested and a playlist for the video to the mobile device. The method can then include receiving the video from the database. The video received is sent as a sequence of blocks, where each block can further be comprised of a sequence of chunks. The method can even further include decompressing each block and storing each chunk on a web server. The method can further include an exchange of a security credential.
    Type: Grant
    Filed: September 1, 2014
    Date of Patent: May 31, 2016
    Assignee: International Business Machines Corporation
    Inventors: Erik J. Burckart, Robert Madey, Jr., Victor S. Moore, Richard Poundstone
  • Patent number: 9344526
    Abstract: A method for executing on a local user system a body of computer-executable code that resides on a provider system is described. A modified image of the computer executable code is installed to a virtual disk on the local user system, the modified image comprising file structure information. The installing comprises creating each of the local files to the virtual disk with null data, wherein upon installation of the modified image, a plurality of disk blocks assigned to the local files contain a null indicator and do not contain any processable content. A streaming control module senses a request to access the virtual disk, determines whether streaming is indicated to satisfy the request, and transfers to the user system the processable content corresponding to the requested disk block. Streaming is indicated when the request corresponds to one of the disk blocks that does not contain any processable content.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: May 17, 2016
    Assignee: VMware, Inc.
    Inventor: Pratap Subrahmanyam
  • Patent number: 9319489
    Abstract: A network adapter receives a request to store a data block. The data block is sent from the network adapter to a compression module. The compression module generates a compressed data block from the data block. The compressed data block or a reference to the compressed data block is stored in a buffer cache. The compressed data block is stored in nonvolatile memory. It is determined that the compressed data block should be flushed a storage device. In response to determining that the compressed data block should be flushed to the storage device, the compressed data block is flushed from the nonvolatile memory to the storage device.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: April 19, 2016
    Assignee: NetApp, Inc.
    Inventors: Dnyaneshwar Pawar, Subramaniam V. Periyagaram, Sandeep Yadav
  • Patent number: 9305042
    Abstract: A system, method, and computer readable medium for removing credit card numbers from a financial transaction record is provided. A temporary record containing only numeric characters is generated by parsing non-numeric characters from the financial transaction record. Numeric strings are then parsed from the temporary record and evaluated to determine if the parsed numeric strings potentially comprise a credit card number. Numeric strings that are evaluated as potentially comprising credit card numbers may then be further evaluated to determine if the numeric strings comprise valid credit card numbers. The original financial transaction record may then be searched for numeric strings evaluated as valid credit card numbers. Any string of consecutive characters that match a validated credit card number may then be replaced with white space characters or other innocuous characters in the transaction record.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: April 5, 2016
    Assignee: West Corporation
    Inventors: David Archbold, Scott D. Westbrook, James V. Frisbie
  • Patent number: 9280364
    Abstract: An apparatus and a method for enhancing memory utilization by compressing unused programs and their system files are provided. The method for generating a profile for a selective loading of a terminal includes receiving a selection of at least one application program that is to be activated, identifying that there is at least one application program to be activated among present deactivated application programs and to be deactivated among present activated application programs, compressing other application programs and system files related to the other application programs than at least one application program to be activated and generating a profile comprising a list of at least one application program to be activated.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: March 8, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Min Lee, Jang-Hyun Yoon