Abstract: A system is provided for enabling a non-speculative pre-fetch operation for processing instructions to be performed in the background ahead of immediate packet processing by a packet processor. The system comprises a packet-management unit for accepting data packets and en-queuing them for processing, a processor unit for processing the data packets, a processor core memory for holding context registers and functional units for processing, a memory for holding a plurality of instruction threads and a software-configurable hardware table for relating queues to pointers to beginnings of instruction threads. The packet-management unit selects an available context in the processor core for processing of a data packet, consults the table, and communicates the pointer to the processor, enabling the processor to perform the non-speculative pre-fetch for instructions.

Abstract: A data look-ahead control is provided to realize a high cache hit rate and improves responsiveness in an information processing system. In the data look-ahead control, when it is determined that the current input/output request is an access to a specific database that was the subject of a recent input/output request and whose I/O count exceeds a predetermined value, and it is also determined that a cache memory can be occupied to some extent and that there would be no impact on other input/output requests, data including one or more blocks (logical tracks) larger than a block that is the subject of the current I/O request are loaded to the cache memory.

Abstract: A method and apparatus to detect and filter out redundant cache line addresses in a prefetch input queue, and to adjust the detector window size dynamically according to the number of detector entries in the queue for the cache-to-memory controller bus. Detectors correspond to cache line addresses that may represent cache misses in various levels of cache memory.

Abstract: A method and processor for selecting instructions in a prefetch buffer in the event of a miss in an instruction cache with a zero cycle penalty. A first, second and third hash may be performed on an address retrieved from a program counter. The first hashed address may be used to index into the instruction cache. The second hashed address may be used to index into the prefetch buffer. If the value stored in the indexed entry in an effective address array of the instruction cache does not equal the value of the third hash of the address (an instruction cache miss), then the instructions in the indexed entry in the prefetch buffer are selected. In this manner, instructions may be selected in the prefetch buffer in the event of a miss in the instruction cache with a zero cycle penalty.

Abstract: An apparatus and method in a high performance processor for issuing instructions, comprising; a classification logic for sorting instructions in a number of priority categories, a plurality of instruction queues storing the instruction of differing priorities, and a issue logic selecting from which queue to dispatch instructions for execution. This apparatus and method can be implemented in both in-order, and out-of-order execution processor architectures. The invention also involves instruction cloning, and use of various predictive techniques.

Abstract: A processor is disclosed including a register, functional unit(s), and a control unit. The register stores multiple bits, wherein one or more of the bits has a value representing a current electrical power dissipation mode (i.e., power mode) of the processor. The functional unit(s) respond to the power mode signal by altering their electrical power dissipation and issuing an acknowledge signal. The control unit receives a power mode input representing a request to enter a new power mode, and issues the power mode signal in response. The control unit waits for the acknowledge signal(s), and responds to the acknowledge signal(s) by modifying the one or more bits of the register to reflect the new power mode. A method is described for transitioning from a current power mode to a new power mode. A data processing system is disclosed including a peripheral device coupled to the processor.

Abstract: System and method for reducing access latency to a shared program memory. The program memory is shared by more than one processor. The system includes fetch buffers (one per processor), prefetch buffers (one per processor), program fetch logic units (one per processor), and an arbiter. Each fetch buffer stores local instructions that are local to an instruction being used by an associated processor. Each prefetch buffer stores subsequent instructions that are subsequent to the local instructions stored in an associated fetch buffer. Each program fetch logic unit determines from where to fetch a next instruction required by the associated processor. The arbiter arbitrates between instruction fetch requests received for the fetch buffers and the prefetch buffers from the various processors. The arbiter determines which of the instruction fetch requests will next gain access to the program memory.

Abstract: An information processing system includes a processing unit which executes a prefetch instruction included as one of a plurality of instructions of a program in a main memory two hierarchical level caches connected to the processing unit and the main memory as arranged so that a primary cache close to the processing unit is a first level cache, and a secondary cache close to the main memory is a second level cache. The prefetch instruction, when executed, causes the processing unit to perform a prefetch operation by transferring operand data to be used in a subsequent load instruction from the main memory to the two hierarchical level data caches, prior to executing the subsequent load instruction. The prefetch instruction includes a plurality of indication bits for specifying cache levels to which the operand data is to be transferred.

Abstract: An information processing system which includes a main memory, a processing unit which executes a prefetch instruction included as one of a plurality of instructions of a program in the main memory, an internal cache controlled as a first level cache, and a cache control function which controls an external cache external of the processing unit as a second level cache. The prefetch instruction, when executed, causes the processing unit to selectively perform a prefetch operation by transferring operand data to be used in a subsequent load instruction from the main memory to the first and second level caches or the second level cache only, prior to executing the subsequent load instruction. The prefetch instruction includes a plurality of indication bits for specifying cache levels to which the operand data is to be transferred.

Abstract: A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pipeline and a non-essential portion that is executed on the h-flow pipeline. The non-essential portion includes hint calculus that is used to provide hints to the main pipeline. The conjugate processor also includes a conjugate mapping table that maps triggers to h-flow targets. Triggers can be instruction attributes, data attributes, state attributes or event attributes. When a trigger is satisfied, the h-flow code specified by the target is executed in the h-flow pipeline.

Abstract: An information handling system processes a loop of instructions. In response to detecting processing of a particular instruction during a pass through the loop, the system initiates a fetch of an initial instruction that is programmed at a start of the loop, and stores an identification of a different instruction that is programmed between the initial instruction and the particular instruction. According to the stored identification, in response to detecting processing of the different instruction during an additional pass through the loop, the system initiates an additional fetch of the initial instruction.

Abstract: The present invention provides a data processing apparatus and method for predicting instructions in a data processing apparatus. The data processing apparatus comprises a processor core for executing instructions from any of a plurality of instruction sets, and a prefetch unit for prefetching instructions from a memory prior to sending those instructions to the processor core for execution. Further, prediction logic is used to predict which instructions should be prefetched by the prefetch unit, the prediction logic being arranged to review a prefetched instruction to predict whether execution of that prefetched instruction will cause a change in instruction flow, and if so to indicate to the prefetch unit an address within the memory from which a next instruction should be retrieved.

Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.

Abstract: A system including a data requester and a storage system. The storage system determines which prefetch data to include with demand data, without the data requester specifying the prefetch data, and provides information enabling the data requestor to discern the demand data from the prefetch data. The data requestor can be a disk drive driver which copies the demand data in fulfilling an operating system request, and then caches the prefetch data. The storage system can be a disk drive.

Abstract: A microprocessor apparatus is provided that enables write back and invalidation of a block of cache lines from memory. The apparatus includes translation logic and execution logic. The translation logic translates a block write back and invalidate instruction into a micro instruction sequence that directs a microprocessor to write back and invalidate a block of cache lines from cache to memory, where the number of cache lines in the block has been previously entered in a register in the microprocessor by a preceding micro instruction. The execution logic is coupled to the translation logic. The execution logic receives the micro instruction sequence, and issues transactions over a memory bus that writes back data corresponding to each of the cache lines within the block.

Abstract: A cache controller is disclosed. The cache controller includes potential replacement list, a plurality of valid bits and a number of counters. The potential replacement list includes a number of entries. Each of the valid bits corresponds to one of the entries. Each of the counters also corresponds to the one of the entries.

Abstract: A method includes providing a prefetch cache of entries corresponding to communication rings stored in memory, the communication rings to store information passed from at least one first processing agent to at least one second processing agent. The method also includes detecting that one of the communication rings has an entry, and determining if the communication ring having an entry is to be prefetched. The method further includes prefetching information stored in the communication ring having an the entry by issuing a ring read operation that causes the information to be placed in a corresponding one of the entries in the prefetch cache.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: A processor and method for handling out-of-order instructions is provided. In one embodiment, the processor comprises instruction pre-fetch logic configured to pre-fetch instructions from memory. The processor further comprises instruction information logic configured to store information about instructions fetched from memory. The processor further comprises control logic configured to control temporary storage of the information related to a pre-fetched instruction if there is currently an active memory access and the currently pre-fetched instruction is an out-of-order instruction. The method pre-fetches the out-of-order in instruction, temporarily stores information associated with the out-of-order instruction in a storage location, and if the memory access completes without encountering a data fault, then saves the temporarily stored information and processes the pre-fetched instruction.

Abstract: A synchronous memory device and its method of operation which can be set to operate at a plurality of supported prefetch modes. The prefetch mode may be set by programming a portion of a mode register of the memory device or by setting one or more programmable elements. For read operations, the synchronous memory device internally reads data corresponding to the largest supported prefetch size, and outputs read data corresponding to the current mode. For write operations the synchronous memory accepts write data corresponding to the selected prefetch mode and writes the received data to the array. Data words corresponding to data not received are masked from writing via a write masking circuit.

Abstract: A method and apparatus for providing a plurality of aligned instructions from an instruction stream provided by a memory unit for execution within a pipelined microprocessor is described. The microprocessor comprises a prefetch buffer, whereby the prefetch buffer stores prefetched instructions and additional information about the validity and size of the prefetch buffer. The method and apparatus use the prefetch buffer to buffer a part of an instruction stream. The actually aligned instruction stream is issued from the prefetch buffer or directly by instructions fetched from the memory, or from a combination of prefetched instructions and actually fetched instructions.

Abstract: A system and method for analyzing data accesses to determine data access patterns. Data address accesses are traced and transformed into Whole Program Streams (WPS). WPS may then be used to discover higher-level data abstractions, such as hot data streams and data flow graphs. Hot data streams provide information related to sequences of data addresses that are repeatedly accessed together. Data flow graphs indicate how hot data streams are related and include frequencies of each hot data stream following another. Hot data streams and data flow graphs may be used with pre-fetching and/or cache managers to improve program performance.

Abstract: Techniques to buffer and present chunks are disclosed. In some embodiments, a first interface may receive chunks of a first cache line, and a second interface may receive chunks of a second cache line. A buffer may store chunks of the first cache line in a first chunk order and may store chunks of the second cache line in a second chunk order. A control unit may present a requester via the second interface with one or more chunks of the first cache line from the buffer.

Abstract: A circuit and method are contemplated herein for improving instruction fetch time by determining mapping information prior to storage of the mapping information in a lower-level memory device. In one embodiment, the circuit and method are adapted to format and align the prefetched instructions into predecoded instructions, and determine mapping information relating the prefetched instructions to the predecoded instructions. In addition, the circuit and method may be adapted to store the mapping information along with corresponding predecoded instructions. By determining the mapping information prior to storage of the mapping information within the lower-level memory device, the circuit and method advantageously increases the rate at which the predecoded instructions may be fetched from the lower-level memory device.

Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.

Abstract: A processor that has a plurality of instruction slots each of which stores an instruction to be executed in parallel. One of the plurality of instruction slots is a first instruction slot and another a second instruction slot. A special instruction stored in the first instruction slot is executed by a first functional unit that executes instructions stored in the first instruction slot, and a second functional unit that executes instructions stored in the second instruction slot. An instruction stored in the second instruction slot is executed in parallel by a third functional unit that executes instructions stored in the second instruction slot.

Abstract: A pipelined CPU includes a pre-fetch (PF) stage for performing branch prediction, and an instruction fetch (IF) stage for fetching instructions that are to be later processed by an execution (EX) stage. The PF stage has a PF address (PFA) register for storing the address of an instruction being processed by the PF stage, and the IF stage has an IF address (IFA) register for storing the address of an instruction to be fetched for later execution. The CPU also includes address register control (ARC) circuitry for setting the contents of the PFA and the IFA. The ARC accepts branch-prediction results from the PF stage to determine the subsequent contents of the PFA and the IFA. If the PF stage predicts a branch, then the ARC sets the next address of the PFA to be sequentially after a predicted branch address, and simultaneously sets the next address of the IFA to be the predicted branch address.

Abstract: A method and processor architecture are provided that enables efficient pre-fetching of instructions for multithreaded program execution. The processor architecture comprises an instruction pre-fetch unit, which includes a pre-fetch request engine, a pre-fetch request buffer, and additional logic components. A number of pre-defined triggers initiates the generation of a pre-fetch request that includes an identification (ID) of the particular thread from which the request is generated. Two counters are utilized to track the number of threads and the number of executed instructions within the threads, respectively. The pre-fetch request is issued to the lower level cache or memory and returns with a corresponding cache line, tagged with the thread ID. The cache line is stored in the pre-fetch request buffer along with its thread ID.

Abstract: Based on an area which was accessed by a just-previous read command and an area which is required by a present read command, the direction of the access, the interval between the areas, and the area size are detected, and the position and size of an area on a disk memory medium where prereading of data is to be carried out are determined by using the detected values. Therefore, prereading of data can be efficiently carried out in response to continuous read commands which request data that are located in the backward direction, i.e., the direction in which an address decreases, or data that are located separately at equal intervals.

Abstract: An apparatus and method for prefetching cache data in response to data requests. The prefetching uses the memory addresses of requested data to search for other data, from a related address, in a cache. This, or other data, may then be prefetched based on the result of the search.

Abstract: A compiler-directed speculative approach to resolve performance-degrading long latency events in an application is described. One or more performance-degrading instructions are identified from multiple instructions to be executed in a program. A set of instructions prefetching the performance-degrading instruction is defined within the program. Finally, at least one speculative bit of each instruction of the identified set of instructions is marked to indicate a predetermined execution of the instruction.

Abstract: A method and apparatus are described for protecting cache lines allocated to a cache by a run-ahead prefetcher from premature eviction, preventing thrashing. The invention also prevents premature eviction of cache lines still in use, such as lines allocated by the run-ahead prefetcher but not yet referenced by normal execution. A protection bit indicates whether its associated cache line has protected status in the cache or whether it may be evicted.

Abstract: This invention provides a dual usage cache reload buffer (CRB) to hold both demand loads as well as prefetch loads. A new form of a data cache block touch (DCBT) instruction specifies which level of the cache hierarchy to prefetch data into. A first asynchronous form of a DCBT instruction is issued to prefetch a stream of data into a L2 cache. A second synchronous form of a DCBT instruction is used to prefetch data from the L2 cache to the CRB in the main CPU, which will bypass the L1 data cache and forward data directly to the register file. This CRB has a dual usage and is used to hold both normal cache reloads as well as the aforementioned prefetched cache lines.

Abstract: A system and method are described for a memory management processor which, using a table of reference addresses embedded in the object code, can open the appropriate memory pages to expedite the retrieval of information from memory referenced by instructions in the execution pipeline. A suitable compiler parses the source code and collects references to branch addresses, calls to other routines, or data references, and creates reference tables listing the addresses for these references at the beginning of each routine. These tables are received by the memory management processor as the instructions of the routine are beginning to be loaded into the execution pipeline, so that the memory management processor can begin opening memory pages where the referenced information is stored. Opening the memory pages where the referenced information is located before the instructions reach the instruction processor helps lessen memory latency delays which can greatly impede processing performance.

Abstract: Method and apparatus for inserting prefetch instructions in an executable computer program. Profile data are generated for executed load instructions and store instructions. The profile data include instruction addresses, target addresses, data loaded and stored, and execution counts. From the profile data, recurring patterns of instructions resulting in cache-miss conditions are identified. Prefetch instructions are inserted prior to the instructions that result in cache-miss conditions for patterns of instructions recurring more than a selected frequency.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: A microprocessor is configured to continue execution in a special Speculative Prefetching After Data Cache Miss (SPAM) mode after a data cache miss is encountered. The microprocessor includes additional registers and program counter, and optionally additional cache memory for use during the special SPAM mode. By continuing execution during the SPAM mode, multiple outstanding and overlapping cache fill requests may be issued, thus improving performance of the microprocessor.

Abstract: A computer. An instruction pipeline and memory access unit execute instructions in a logical address space of a memory of the computer. An address translation circuit translates address references generated by the program from the program's logical address space to the computer's physical address space. Profile circuitry is cooperatively interconnected with the instruction pipeline and configured to detect, without compiler assistance for execution profiling, occurrence of profilable events occurring in the instruction pipeline, and is cooperatively interconnected with the memory access unit to record profile information describing physical memory addresses referenced during an execution interval of the program.

Abstract: A method, apparatus, and system that compares a current fetch request having a first start address and length associated with the current fetch request to a second start address of the next fetch request, determines whether the content already loaded in a buffer will be used to at least partially fulfill the next fetch request based upon the comparison, and inhibits access to an instruction cache based upon the comparison.

Abstract: A method and apparatus for applying patches to a code or data residing on a non-volatile memory device is illustrated. A code residing at a first location in a non-volatile memory can be replaced by a codes residing at a second locations in a memory map. A patching device compares a first address of a first code to an address identified by a pre-fetch instruction. If the first address matches the address identified by the pre-fetch instruction, a pre-fetch abort is issued to facilitate replacing a bad code residing at the first address with a good code. The good code can be pointed to by a vector in a vector table where the address of the vector is dynamically loaded into a program counter.

Abstract: Method and apparatus for prefetching cache with requested data are described. A processor initiates a read access to main memory for data which is not in the main memory. After the requested data is brought into the main memory, but before the read access is reinitiated, the requested data is prefetched from main memory into the cache subsystem of the processor which will later reinitiate the read access.

Abstract: A branch history information write control device in an instruction execution processing apparatus includes a memory unit storing an instruction string, and a branch prediction unit performing a branch prediction of a branch instruction. A control unit in the device controls the memory unit and the branch prediction unit in such a way that writing of branch history information in the branch prediction unit and control over fetching of the instruction string in the memory unit may not occur simultaneously so that no instruction fetch is held. A bypass unit in the device makes the branch history information of the branch instruction a research target of a branch prediction, where said control unit uses a counter to count several clock cycles (several states) to delay, for a period of several clock cycles (several states), the writing of the branch history information and control, beforehand, the fetching of the instruction string.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: An instruction control apparatus, and method, used with a device including a cache memory, a lower memory, an instruction fetch device issuing an instruction fetch request for a target of a first branch instruction to the cache memory, and an instruction control device processing a instruction sequence stored in the cache memory. The apparatus and method pre-prefetch a target instruction sequence for a target of a second branch instruction. A predetermined instruction sequence based on a past history is preliminarily transferred from the lower memory to the cache memory when the target instruction sequence for the target of the first branch instruction is not in the cache memory.

Abstract: The present invention provides a mechanism for supporting high bandwidth instruction fetching in a multi-threaded processor. A multi-threaded processor includes an instruction cache (I-cache) and a temporary instruction cache (TIC). In response to an instruction pointer (IP) of a first thread hitting in the I-cache, a first block of instructions for the thread is provided to an instruction buffer and a second block of instructions for the thread are provided to the TIC. On a subsequent clock interval, the second block of instructions is provided to the instruction buffer, and first and second blocks of instructions from a second thread are loaded into a second instruction buffer and the TIC, respectively.

Abstract: According to one embodiment of the invention, a prefetcher in a memory controller is described which includes logic to receive memory request hints from a CPU. The memory request hints are used by the prefetcher in the memory controller to prefetch information from one or more memory devices coupled to the memory controller via a memory bus. The prefetcher in the memory controller further includes logic to determine the types of memory request hints provided by the CPU, the types of memory request hints are used to indicate whether the hints provided by the CPU are for instruction memory read request or data memory read request. The prefetcher in the memory controller also includes logic to generate prefetch requests to prefetch information from the one or more memory devices, based on the types of memory request hints provided by the CPU and bandwidth availability of the memory bus.

Abstract: A synchronous memory device and its method of operation which can be set to operate at a plurality of supported prefetch modes. The prefetch mode may be set by programming a portion of a mode register of the memory device or by setting one or more programmable elements. For read operations, the synchronous memory device internally reads data corresponding to the largest supported prefetch size, and outputs read data corresponding to the current mode. For write operations the synchronous memory accepts write data corresponding to the selected prefetch mode and writes the received data to the array. Data words corresponding to data not received are masked from writing via a write masking circuit.

Abstract: A microcontroller, connected to a memory which stores instructions and data, includes an instruction execution unit for reading instructions and data from the memory and processing the read instructions and a prefetch circuit unit that receives the instructions and data read from the memory and detects pseudo instructions included in the instructions and data. A pseudo instruction precedes a branch instruction and indicates the existence of the branch instruction and the branch to address. The prefetch circuit unit includes a prefetch buffer connected between the instruction execution unit and the memory for temporarily storing instructions and data being transferred from the memory to the instruction execution unit and a pseudo instruction buffer for temporarily storing instructions and data located at the address of the branch instruction which follows the pseudo instruction.

Abstract: According to one embodiment of the invention, a method is provided in which memory requests from a first component and a second component are received. The memory requests are issued by the first component and the second component to access one or more memory devices via a memory controller. The memory requests received from the first component are accumulated in a first queue and the memory requests received from the second component are accumulated in a second queue, respectively. The memory requests accumulated in the first queue are sent to the memory controller for processing as a block of memory requests. The memory requests accumulated in the second queue are sent to the memory controller for processing as a block of memory requests.

Abstract: A central processing system can maintain an efficient information reading operation even when a program executed by a central processing unit contains many branch commands. A prefetch queue of the central processing unit reads and information expected to be processed next by the central processing unit from a main memory. The function of the prefetch queue is deactivated in accordance with a control signal provided from a prefetch queue control unit. A block transfer function of a cache memory is also deactivated when unnecessary information is read from the main memory in accordance with the block transfer function.