Abstract: An information processing unit and method for controlling a cache according to a software prefetch instruction, are disclosed. Indicator or indication bits are provided for indicating a hierarchical level of a cache to which an operand data is to be transferred or a quantity of an operand data to be transferred, or both. The indication bits are provided in a software prefetch instruction such that at the time of a transfer of block data or line data, a required data is transferred to a cache based on the indication bits in the prefetch instruction. Thus, it is not necessary to change the timing for executing a software prefetch instruction depending on which one of the caches of the hierarchical levels is hit, and a compiler can generate an instruction sequence more easily.

Abstract: A standard CPU (with a data cache) is modified in such a way as to permit the programmer to bypass the data cache when necessary in order to fetch or store data items directly from/to the memory, ensuring that data accesses exhibiting a high degree of locality are made to the cache, while those accesses that are non-local, or referencing shared data items, are made directly to the main memory, bypassing the cache. The fundamental observation is that in most situations the programmer of the CPU could very easily determine which data items could benefit from being placed into the data cache and which ones could not. This is especially true in embedded communications environments where the programmer has explicit control over data items that are shared between the program running on the CPU and the remainder of the hardware elements.

Abstract: An apparatus and method for prefetching data into a cache memory system is provided. A prefetch instruction includes a hint type that allows a programmer to designate whether, during a data retrieval operation, a hit in the cache is to be ignored or accepted. If accepted, the prefetch operation completes. If ignored, the prefetch operation retrieves data from the main memory, even though the cache believes it contains valid data at the requested memory location. Use of this invention in a multiple bus master processing environment provides the advantages of using a cache memory, i.e., burst reads and a relatively large storage space as compared to a register file, without incurring disadvantages associated with maintaining data coherency between the cache and main memory systems.

Abstract: A method and apparatus for prefetching data in a computer system that inces a processor. A prefetch instruction is executed and, in response, data is prefetched from a memory location. It is determined if a memory exception occurred during the prefetching of the data. If a memory exception occurred, the exception is handled if the prefetch instruction indicates to do so.

Abstract: An instruction fetch unit that employs sequential way prediction. The instruction fetch unit comprises a control unit configured to convey a first index and a first way to an instruction cache in a first clock cycle. The first index and first way select a first group of contiguous instruction bytes within the instruction cache, as well as a corresponding branch prediction block. The branch prediction block is stored in a branch prediction storage, and includes a predicted sequential way value. The control unit is further configured to convey a second index and a second way to the instruction cache in a second clock cycle succeeding the first clock cycle. This second index and second way select a second group of contiguous instruction bytes from the instruction cache.

Abstract: A central processing unit (CPU) of a computer has a data caching unit which includes a novel dual-ported prefetch cache configured in parallel with a conventional single-ported data cache. In response to a data cache miss, the requested data is fetched from external memory and loaded into the data cache and into the prefetch cache. Thereafter, if a prefetch cache hit occurs, the physical address of the corresponding data request is provided to a prefetch engine which, in turn, adds a stride to the physical address to derive a prefetch address. This prefetch address identifies data which is predicted to be soon requested in subsequent instructions of the computer program. Data corresponding to the prefetch address is then retrieved from external memory and loaded into the prefetch cache. This prefetching operation frequently results in the prefetch cache storing data that is requested by subsequently executed instructions in a computer program.

Abstract: The present invention minimizes unneeded memory accesses by providing a digital processor having control circuit for terminating on-going memory accesses, and by a data transfer circuit that allow jump instructions to be detected sooner in the decode unit. The digital processor includes a decode unit, fetch unit and a memory controller. When the decode unit of the present invention processor determines that a discontinuity must occur in the instruction fetch sequence, it asserts a "jump taken" signal to the fetch unit to indicate that any pre-fetched instruction codes are to be discarded and that fetching is to resume at a new fetch program counter (FPC) value. If the fetch unit is currently stalled because of an outstanding request to the memory controller unit, then the fetch unit asserts an "abort" signal to the memory controller.

Abstract: A microprocessor is configured to execute a prefetch instruction specifying a cache line to be transferred into the microprocessor, as well as an access mode for the cache line. The microprocessor includes caches optimized for the access modes. In one embodiment, the microprocessor includes functional units configured to operate upon various data type. Each different type of functional unit may be connected to different caches which are optimized for the various access modes. The prefetch instruction may include a functional unit specification in addition to the access mode. In this manner, data of a particular type may be prefetched into a cache local to a particular functional unit.

Abstract: The performance of a disk cache subsystem is enhanced by dynamically sizing read requests based upon the current disk cache hit rate. Any data requested in the read request which is not the immediately requested data is located adjacent to the immediately requested data. Accordingly, the size of the read request depends upon at least one variable factor other than the size of the requested data. More specifically, the size of the read request is reduced as the disk cache hit rate declines, and the size of the read request is increased as the disk cache hit rate increases. Short-term and long-term disk cache hit rates are tracked. The short-term disk cache hit rate is used to determine the reduction in the size of the read request, and the long-term disk cache hit rate is used to determine the increase in the size of the read request.

Abstract: Within a data processing system implementing primary and secondary caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. Prefetching may be performed on cache misses or hits. Cache misses on successive cache lines may allocate a stream of cache lines to the stream buffers. Control circuitry, coupled to a stream filter circuit, selectively controls fetching and prefetching of data from system memory to the primary and secondary caches associated with a processor and to a stream buffer circuit.

Abstract: A microprocessor includes an instruction alignment unit for locating instructions and conveying the located instructions to a set of decode units. The instruction alignment unit includes dual instruction queues. The first instruction queue receives instruction blocks fetched from the instruction cache. The instruction alignment unit uses instruction identification information provided by the instruction cache to select instructions from the first instruction queue for conveyance to the second instruction queue. Additionally, the instruction alignment unit applies a predetermined selection criteria to the instructions within the second instruction queue in order to select instructions for dispatch to the decode units. Selection logic for the first instruction queue need not consider the type of instruction, etc., in selecting instructions for conveyance to the second instruction queue. Selection logic for the second instruction queue considers instruction type, etc.

Abstract: A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. In a first embodiment, the CPU receives general purpose instructions, such as X86 instructions, wherein certain X86 instruction sequences implement DSP functions. The CPU includes a processor mode register which is written with one or more processor mode bits to indicate whether an instruction sequence implements a DSP function. The CPU also includes an intelligent DSP function decoder or preprocessor which examines the processor mode bits and determines if a DSP function is being executed. If a DSP function is being implemented by an instruction sequence, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction.

Abstract: A caching apparatus and method for enhancing retrieval of data from an optical storage device are provided. The apparatus preferably includes a first memory device for storing data therein. The first memory device preferably includes a predetermined application. An optical storage device is positioned in communication with the first memory device for optically storing data therein. The optical storage device includes a plurality of data storage sectors. A second memory device is positioned in communication with the first memory device for storing data. The second memory device preferably has a predetermined amount of data storage space. The predetermined amount of data storage space includes a caching space defined by only a portion of the predetermined amount of data storage space of the second memory device.

Abstract: A mechanism is described that predicts the success or failure of prefetching instructions based on the previous performance of the instructions. A prefetching instruction is successful if the block of information prefetched into the cache is used by the processor before it is discarded from the cache. A prefetching instruction is unsuccessful, a failure, if the block of information prefetched into the cache is not used while in the cache. The prediction regarding the success or failure of the prefetching instruction is performed utilizing a table that records the history regarding the usefulness of each prefetch made by a prefetching instruction at a given memory location. The table is called a Touch-History-Table (THT). The THT is preferably accessed during the decode phase of each instruction using the memory location of the instruction. The table records the history of previous outcomes (success or failure) of the prefetching instruction up to the table size.

Abstract: A method and hardware apparatus for data prefetching. In one embodiment, the method of the present invention comprises first calculating a local stride value by computing the value between two address references of a first load instruction. The local stride value of the first load instruction is used as a global stride value for address prefetching for a second load instruction, where the second load instruction is different from the first load instruction. An appropriate global stride value is added to a previous address value associated with a previous occurrence of the second load instruction, producing an address location for prefetching a block of data.

Abstract: A method and system for efficiently transferring data between a host computer and a peripheral component which is removably coupled to the host computer. In one embodiment of the present invention, a peripheral component such as, for example, a network interface card receives information from a peripheral component driver, such as, for example, a network interface card driver. In this embodiment, the information triggers the peripheral component to transmit a read request to the host computer such that the peripheral component can access data present at the host computer. Next, the peripheral component determines from the information received at the peripheral component, which type of read request to transmit to the host computer. In this embodiment, the type of read request is selected such that only a desired portion of the data will be prefetched and stored in memory of the host computer.

Abstract: Improved scheduling of instructions within a loop for execution by a computer system having hardware lookahead is provided. A dependence graph is constructed which contains all the nodes of a dependence graph corresponding to the loop, but which only contains loop-independent dependence edges. A start node simulating a previous iteration of the loop may be added to the dependence graph, and an end node simulating a next iteration of the loop may also added to the dependence graph. A loop-independent edge between a source node and the start node is added to the dependence graph, and a loop-independent edge between a sink node and the end node is added to the dependence graph. Loop-carried edges which satisfy a computed lower bound on the time required for a single loop iteration are eliminated from a dependence graph, and loop-carried edges which do not satisfy the computed lower bound are replaced by a pair of loop-independent edges. Instructions may be scheduled for execution based on the dependence graph.

Abstract: A central processing unit includes an adder dedicated to address calculation provided separately from an ALU, a first address data route connected to a program counter and a stack pointer register, a second address data route connected to a prefetch que, a predecoder for determining whether an instruction to be executed calls for an addressing mode whereby a value in the program counter or the SP register is added to an immediate address in an instruction code. With this arrangement, if the addressing mode is called for, address calculation by the adder is performed concurrently with computation using an operand for another instruction, in accordance with a control signal output by the predecoder.

Abstract: A data processing system having a processor core 4, a memory management unit 6 and a cache memory 8 uses the memory management unit 6 to produce a confirm signal C that indicates that a memory access request will be processed no further, i.e. the outcome is fully determined. The next memory access request is initiated prior to this confirm signal C being available and accordingly if the confirm signal C indicates a result different to that predicted, then a stall of the system is required until the non-confirmed memory access request can be dealt with.

Abstract: A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and generating for to each instruction a compounding information which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit with the compounding information. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit.

Abstract: A central processing unit (CPU) of a computer includes a novel prefetch cache configured in parallel with a conventional data cache. If a data cache miss occurs, the requested data is fetched from external memory and loaded into the data cache and into the prefetch cache. Thereafter, if a prefetch cache hit occurs, a prefetch address is derived, and data corresponding to the prefetch address is prefetched into the prefetch cache. This prefetching operation frequently results in the prefetch cache storing data that is requested by subsequently executed instructions in a computer program, thereby eliminating latencies associated with external memory. A software compiler of the computer ensures the validity of data stored in the prefetch cache. The software compiler alerts the prefetch cache that data stored within the prefetch cache is to be rewritten and, in response thereto, the prefetch cache invalidates the data.

Abstract: A pipelined x86 processor implements a method of detecting self-modifying code in which a prefetched block of instruction bytes may contain an instruction that is modified by a store instruction preceding it in the execution pipeline. The processor includes a Prefetch unit having a multi-block prefetch buffer, a Branch unit with a branch target cache (BTC), and a Load/Store (LDST) unit having store reservation stations.

Abstract: When the OS judges that a read request to the secondary storage device from the user process is the sequential access, the OS judges whether prefetching is to be stopped before the data succeeding to the data designated by the request is prefetched, so as to decrease replacement of data prefetched to the main memory by other data before the data is used. The judgment is executed to prevent that succeeding data from being replaced by other data after the succeeding data is prefetched to the cache area in the main memory. That is, it is judged whether the data requested by the read request has already been prefetched, and has already been replaced by other data before the requested data is used by the user process, if the requested data has been prefetched. When these two conditions are met, prefetch is useless. The prefetching accompanying this read request is not executed, the prefetch stop flag is set, and prefetching is prohibited to the succeeding sequential access by this prefetch stop flag.

Abstract: An instruction cache employing a cache holding register is provided. When a cache line of instruction bytes is fetched from main memory, the instruction bytes are temporarily stored into the cache holding register as they are received from main memory. The instruction bytes are predecoded as they are received from the main memory. If a predicted-taken branch instruction is encountered, the instruction fetch mechanism within the instruction cache begins fetching instructions from the target instruction path. This fetching may be initiated prior to receiving the complete cache line containing the predicted-taken branch instruction. As long as instruction fetches from the target instruction path continue to hit in the instruction cache, these instructions may be fetched and dispatched into a microprocessor employing the instruction cache. The remaining portion of the cache line of instruction bytes containing the predicted-taken branch instruction is received by the cache holding register.

Abstract: An FPSCR (Floating Point Status and Control Register) mechanism supports de-serialized floating point unit (FPU) instruction execution. The FPSCR mechanism provides for speculative execution of all FPU instructions. In particular, instructions that directly alter FPSCR data values may be executed speculatively. Instructions of this type which may be de-serialized include the move-from FPSCR instruction, the move-to-condition register from FPSCR instruction, the move-to FPSCR field immediate instruction, the move-to FPSCR field instruction, the move-to FPSCR bit 0 instruction, the move-to FPSCR bit 1 instruction, as well as FPU register-to-register instructions having a recording bit set. Speculative execution is implemented by providing an accurate working FPSCR at the time the speculatively executing instruction sources FPSCR data. Moreover, the FPSCR mechanism re-establishes the working FPSCR when exceptions occur, or speculative execution is cancelled.

Abstract: A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.

Abstract: A method is provided for optimizing a program by inserting memory prefetch operations in the program executing in a computer system. The computer system includes a processor and a memory. Latencies of instructions of the program are measured by hardware while the instructions are processed by a pipeline of the processor. Memory prefetch instructions are automatically inserted in the program based on the measured latencies to optimize execution of the program. The latencies measure the time from when a load instructions issues a request for data to the memory until the data are available in the processor. A program optimizer uses the measured latencies to estimate the number of cycles that elapse before data of a memory operation are available.

Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes an XY address for rendering the graphics primitives. A graphics processor, which includes a bypass logic circuit, enables the graphics processor to temporarily store display list commands in an internal storage device while previously fetched display list data is being processed. The bypass logic circuit allows the graphics processor to bypass the internal storage device and write fetched command directly to an execution unit in the graphics processor. By having the bypass capabilities, the graphics processor is able to optimize the internal storing of commands in the display list in the internal storage unit.

Abstract: A computer system for executing branch instructions and a method of executing branch instructions are described. Tow instruction fetchers respectively fetch a sequence of instructions from memory for execution and a sequence of instructions commencing from a target location identified by a set branch instruction in a sequence of instructions being executed. When an effect branch signal is generated, the target instructions are next executed, and the fetcher which was fetching the instructions for execution commences fetching of the target instructions. The effect branch signal is generated separately from the set branch instruction. In another aspect, the effect branch signal is generated on execution of a conditional effect branch instruction, located at the point in the instruction sequence where the branch is to be taken.

Abstract: The present invention provides a data processing apparatus for fetching an instruction in to an instruction cache, comprising an instruction cache for storing instructions, and a processor core for outputting an instruction address to the instruction cache on an instruction address bus, and for receiving the instruction corresponding to that instruction address on an instruction data bus The processor core is arranged to issue a predetermined control signal to the instruction cache when outputting the instruction address to cause the instruction cache to perform an instruction fetch procedure.

Abstract: The invention is a system providing adaptive stream buffers using instruction-specific prefetching avoidance (ISPA). According to the invention, each time the CPU executes an instruction resulting in prefetched cache lines not being used, the instruction address is stored in a table. Subsequent instruction addresses are compared to the instruction addresses in the table, and a stream buffer is not allocated when the subsequent instruction address is found within the table.

Abstract: A method and apparatus for prefetching data in a computer system that includes a processor. A prefetch instruction is executed and, in response, data is prefetched from a memory location. It is determined if a memory exception occurred during the prefetching of the data. If a memory exception occurred, the exception is handled if the prefetch instruction indicates to do so.

Abstract: A microprocessor is configured to execute a prefetch instruction including an access count field defining an access count corresponding to a cache line identified by the prefetch instruction. The access count indicates a number of accesses expected to the cache line. The microprocessor attempts to retain the cache line until at least the number of accesses specified by the access count are recorded. Effectively, a "lifetime" for the cache line to be stored in the cache is specified. The lifetime indicates not only how long the cache line should be retained in the cache (in terms of the number of cache accesses), but also more accurately indicates the time at which the cache line can be removed from the cache (i.e. upon expiration of the access count). In one embodiment, a prefetched cache line and the corresponding access count are stored in a data cache within the microprocessor. The stored access count is decremented upon access to the cache line.

Abstract: A process is provided for determining the beginning and ending of each instruction of a variable length instruction. Data lines are stored in a first memory area which illustratively is an instruction cache. Each data line comprises a sequence of data words that are stored at sequential address in a main memory. The data lines contain multiple encoded variable length instructions that are contiguously stored in the main memory. Multiple indicators are stored in a second memory area, including one indicator associated with each data word of the data lines stored in the first memory area. Each indicator indicates whether or not its associated data word is the initial data word of a variable length instruction. A sequence of data words may be fetched from the cache. The fetched sequence of data words includes a starting data word and at least the number of data words in the longest permissible instruction. Plural indicators (i.e.

Abstract: A prefetch unit stores a plurality of prefetch control fields in a data history table. Each prefetch control field selects one of multiple prefetch algorithms for use in prefetching data. As an instruction stream is fetched, the fetch address is provided to the data history table for selecting a prefetch control field. Since multiple prefetch algorithms are supported, many different data reference patterns may be prefetched. The prefetch unit is configured to gauge the effectiveness of the selected prefetch algorithm, and to select a different prefetch algorithm if the selected prefetch algorithm is found to be ineffective. The prefetch unit monitors the load/store memory operations performed in response to the instruction stream (i.e. the non-prefetch memory operations) to determine the effectiveness. Alternatively, the prefetch unit may evaluate each of the prefetch algorithms with respect to the observed set of memory references and select the algorithm which is most accurate.

Abstract: A microprocessor having an instruction prefetch function includes a storage circuit in which an instruction externally supplied to the microprocessor via an external interface is stored, a first latch circuit which latches a write address value of the storage circuit in response to an interrupt signal externally supplied to the microprocessor, and an internal interrupt signal outputting circuit which compares a read address value of the storage circuit indicating the instruction stored in the storage circuit with the write address value supplied from the first latch circuit and which generates the internal interrupt signal only when the read address value and the write address value coincide with each other. The microprocessor processes an interrupt process in response to the internal interrupt signal.

Abstract: A structure for, and a method of operating, an operand cache to store operands retrieved from a memory. An instruction requiring an operand stored in the memory, is allowed to speculatively execute in an execution unit of a processor using an operand stored in an entry (corresponding to the address of the instruction) of the operand cache. When the actual operand is later retrieved from the memory it is compared to the cached operand used for speculative execution. If the cached and actual operands are unequal then the speculatively executed instruction and all subsequent instructions are aborted and the processor resumes execution at the address of the instruction that was speculatively executed.

Abstract: When a processor (102) issues a request for an address (502), a determination is made as to whether or not the address is contained within a buffer (103) or cache associated with the processor (102), or the address is contained within a line of data currently being fetched from an external memory system (105). If the address is not contained within the buffer or cache and is not contained within a line being currently fetched, the current fetch will be cancelled (515, 516).