Abstract: A data processing system includes a vector data processing unit that includes a shared scheduler queue configured to store in a same queue, at least one entry that includes at least a mask type instruction and another entry that includes at least a vector type instruction. Shared pipeline control logic controls a vector data path or a mask data path, based a type of instruction picked from the same queue. In some examples, at least one mask type instruction and the at least one vector type instruction each include a source operand having a corresponding shared source register bit field that indexes into both a mask register file and a vector register file. The shared pipeline control logic uses a mask register file or a vector register file depending on whether bits of the shared source register bit field identify a mask source register or a vector source register.

Abstract: A method of updating registers, including: providing a bitmap register; providing a target register; establishing a mapping between each bit in the bitmap register and a corresponding target content block in the target register; providing a register update instruction, the register update instruction including: one or more flag bits at specified locations, wherein each flag bit corresponds to a bit in the bitmap register, indicating whether the target content block corresponding to the bit needs to be updated; wherein for each target content block indicated by the bit that needs to be updated, the register update instruction further comprises a new content of the target content block or a source of the new content; writing the one or more flag bits in the register update instruction into the bitmap register; and executing the register update instruction to update the target content blocks.

Abstract: A computer-implemented method, system and computer program product for effectively searching for values in a multi-byte array of elements using an n-byte search instruction. Multiple values to be searched in an N-byte array of elements in a loop are received. The loop is optimized by searching the received search values at the starting address of the N-byte array of elements using the n-byte search instruction. A successful search is performed if the received return address points to an address found in the lowest n-bytes of the N-byte array of elements and an element of the address corresponds to a search value. Otherwise, a subsequent search for the search values at the address of the next element in the N-byte array of elements is performed if there are additional elements in the N-byte array of elements to be searched.

Abstract: A processor includes a time counter and a time-resource matrix and statically dispatches baseline and extended instructions. The processor includes a plurality of register sets of a register file and a plurality of sets of functional units which are coupled by sets of dedicated read and write buses to allow parallel execution of baseline and extended instructions.

Abstract: Methods, systems, and devices for a split cache for address mapping data are described. A memory system may include a cache (e.g., including a first and second portion) for storing data that indicates a mapping between logical addresses associated with a host system and physical addresses of the memory system. The memory system may store data (e.g., the address mapping data) within the first portion of the cache. Additionally, the memory system may store an indication of whether the data is used for any access operations during a duration that the data is stored in the first portion of the cache. The memory system may transfer subsets of the data to the second portion of the cache if they are used for access operations during the duration.

Abstract: A register management system is coupled to a register. The register management system receives an address and functional data for a write operation to be performed on the register. The functional data includes write bits and mask bits associated with the write bits. One or more mask bits having a first logic state indicate that associated one or more write bits are to be written to the register, respectively. Based on the address, the register management system selects a first half of the register or a second half of the register to perform the write operation. Further, the register management system writes the one or more write bits associated with the one or more mask bits having the first logic state to one or more storage elements of the first half of the register or the second half of the register, respectively.