Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

Abstract: The present disclosure relates to methods and devices for data or graphics processing including an apparatus, e.g., a GPU. The apparatus may receive at least one bitstream including a plurality of bits, each of the bits corresponding to a position in the at least one bitstream, and each of the bits being associated with color data. The apparatus may also arrange an order of the plurality of bits in the at least one bitstream, such that at least one of the bits corresponds to an updated position in the at least one bitstream. Additionally, the apparatus may convert, upon arranging the order of the bits, the color data associated with each of the plurality of bits in the at least one bitstream. The apparatus may also compress, upon converting the color data associated with each of the bits, the plurality of bits in the at least one bitstream.