Abstract: Techniques are disclosed relating to instruction scheduling in the context of instruction cache misses. In some embodiments, first-stage scheduler circuitry is configured to assign threads to channels and second-stage scheduler circuitry is configured to assign an operation from a given channel to a given execution pipeline based on decode of an operation for that channel. In some embodiments, thread replacement circuitry is configured to, in response to an instruction cache miss for an operation of a first thread assigned to a first channel, deactivate the first thread from the first channel.

Abstract: A processor includes a loop detection unit to detect an OOO-loop based on the reserved resources for execution of the OOO loop. The processor executes the OOO loop by reading source operand data on first iteration of the loop and write back data on the last iteration of the loop while allowing instructions after the loop to be concurrently executed.

Abstract: The present disclosure provides a multiplication and accumulation circuit based on radix-4 booth code and differential weight storage. The circuit includes an input data encoding circuit, a differential weight storage circuit, an integral calculation circuit and a differential ADC circuit. The input data encoding circuit is configured to encode original input data. The differential weight storage circuit is configured to store weight values, and multiply the original input data after being encoded by the weight values stored to obtain multiplication results. The integral calculation circuit is configured to respectively accumulate a positive value and a negative value of each multiplication result. The differential ADC circuit is configured to perform analog-to-digital conversion on a difference between accumulated results of the positive values and the negative values to obtain a digital multiplication and accumulation result.

Abstract: Systems, methods, and apparatuses relating to a configurable accelerator having dataflow execution circuits are described.

Abstract: A method and system for authorizing a secure transaction using a portable device is disclosed. The method includes an authorization process performed in real-time that includes two phases: an authentication phase and a transaction processing phase. In the authentication phase, a resource provider system may receive a cryptogram from a portable device and verify the cryptogram. Upon the resource provider system obtaining an authentication response indicator, the transaction processing phase may include the resource provider system generating and transmitting an authorization request message to a processing computer. The resource provider system may then receive an authorization response message from the processing computer including an authorization response indicator, which completes the authorization process.

Abstract: The logging techniques described herein can enable using logging tools without having to use different methods for sandbox implementations and push out the log data to storage without problems. The log data is treated as sensitive data and is protected according to the defined security policies. Further, the results may be compressed and encrypted.

Abstract: The subject technology runs a compiled neural network (NN) model on a particular processor with multiple priority queues for executing different processes, the compiled NN model being assigned to a particular priority queue, and the compiled NN model includes context switch instructions that were previously inserted into a neural network (NN) model from which the compiled NN model was compiled. The subject technology determines that a particular context switch instruction has been executed by the particular processor. The subject technology determines that a different process is waiting to be executed, the different process being assigned to a different priority queue and the different process being a higher priority process than the running compiled NN model. In response to executing the particular context switch instruction, the subject technology performs a context switch to the different process assigned to the different priority queue when the different process is waiting to be executed.

Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

Abstract: Systems and methods for encrypted content management are provided and include generating a user private key, a user public key, and a symmetric encryption key. A group private key, a group public key, and a group symmetric encryption key are generated and the group private key is encrypted with the group symmetric encryption key. A first shared-secret key is generated based on the user public key and the group private key using a diffie-hellman exchange algorithm. The group symmetric encryption key is encrypted using the first shared-secret key to generate an escrow key. Plaintext data is encrypted using a content symmetric key. A second shared-secret key is generated based on an ephemeral private key and the group public key using a diffie-hellman exchange algorithm. The content symmetric key is encrypted using the second shared-secret key.

Abstract: A method of predicting the evolution of simulation results for an Internet of Things (IoT) network by creating a source digital twin for the IoT network, driven by real-time sensed data from objects fed to models of the objects interconnected as object nodes in a directed acyclic graph (DAG) with the interconnections representing flow of data, the source digital twin outputting a state of one or more of the objects in real time; creating a clone digital twin of the source digital twin; connecting input of the clone digital twin with output of the source digital twin via a data stream synthesizer node, the data stream synthesizer node adds a time increment to the output of the source digital twin to drive the clone digital twin at the incremented time. The source digital twin and the clone digital twin are executed to indicate an evolved state of one or more of the objects at the incremented time as the output of the clone digital twin.

Abstract: In an embodiment, a processor implements a different atomicity size (for memory consistency order) than the operation size. More particularly, the processor may implement a smaller atomicity size than the operation size. For example, for multiple register loads, the atomicity size may be the register size. In another example, the vector element size may be the atomicity size for vector load instructions. In yet another example, multiple contiguous vector elements, but fewer than all the vector elements in a vector register, may be the atomicity size for vector load instructions.

Abstract: To facilitate backwards compatibility, a computing device may respond to a call from an application for information regarding a processor on the computing device by returning information regarding a different processor than the processor on the computing device, including one or more of processor model, processor family, cache capabilities, translation lookaside buffer capabilities, processor serial number, processor brand, processor manufacturer, thread/core topology, cache topology, extended features, virtual address size, or physical address size that differs when the processor determines that the application is a legacy device application.

Abstract: VLIW directed Power Management is described. In accordance with described techniques, a program is compiled to generate instructions for execution by a very long instruction word machine. During the compiling, power configurations for the very long instruction word machine to execute the instructions are determined, and fields of the instructions are populated with the power configurations. In one or more implementations, an instruction that includes a power configuration for the very long instruction word machine and operations for execution by the very long instruction word machine is obtained. A power setting of the very long instruction word machine is adjusted based on the power configuration of the instruction, and the operations of the instruction are executed by the very long instruction word machine.

Abstract: Systems, methods, devices, and computer-implemented instructions for processor power management implemented in a compiler. In some implementations, a characteristic of code is determined. An instruction based on the determined characteristic is inserted into the code. The code and inserted instruction are compiled to generate compiled code. The compiled code is output.

Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.

Abstract: Disclosed are apparatuses, methods, and computer-readable media for providing flexible command pointers to microcodes in a memory device. In one embodiment, a method is disclosed comprising receiving a command to access a memory device; accessing a configuration parameter; identifying a program counter value based on the configuration parameter and the command; and loading and executing a microcode based on the program counter.

Abstract: A method for emulating a guest centralized flag architecture by using a native distributed flag architecture. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks, wherein each of the instruction blocks comprise two half blocks; scheduling the instructions of the instruction block to execute in accordance with a scheduler; and using a distributed flag architecture to emulate a centralized flag architecture for the emulation of guest instruction execution.

Abstract: A mechanism is described for facilitating optimization of cache associated with graphics processors at computing devices. A method of embodiments, as described herein, includes introducing coloring bits to contents of a cache associated with a processor including a graphics processor, wherein the coloring bits to represent a signal identifying one or more caches available for use, while avoiding explicit invalidations and flushes.

Abstract: A system and method for the secure and private demonstration of cloud-based cyber-security tools. Using an advanced sandboxing design patterns, isolated instances of virtual networks allow a potential client to compare their existing cyber defense tools against a set of cloud-based tools. Capitalizing on non-persistent and secure sandboxes allow the invention to demonstrate fully functional and devastating cyber-attacks while guaranteeing strict privacy and security to both existing customers and potential ones. Additionally, instantiating separate sandboxed observed systems in a single multi-tenant infrastructure provide each customer with the ability to rapidly create actual representations of their enterprise environment offering the most realistic and accurate demonstration and comparison between products.

Abstract: Two clocks, a fast clock and a slow clock are provided for clocking a processing unit. A plurality of frequency settings, referred to as gears, are defined for the two clock. Each of these gears indicates a maximum frequency for the fast clock and a minimum frequency for the slow clock, such that the gap between the two frequencies may be kept to a manageable level so as to reduce transients upon switching between the two clocks. The system switches between the gears as required. In response to a determination to increase the frequency of the clock signal, a higher gear is selected at which the maximum and minimum frequencies defined for that gear are higher than the previous selected gear.

Abstract: Disclosed herein is a method for managing of NOP instructions in a microcontroller, the method comprising duplicating all jump instructions causing a NOP instruction to form a new instruction set; inserting an internal NOP instruction into each of the jump instructions; when a jump instruction is executed, executing a subsequent instruction of the new instruction set; and executing the internal NOP instruction when an execution of the subsequent instruction is skipped.

Abstract: Systems and methods for encrypted content management are provided and include generating a user private key, a user public key, and a symmetric encryption key. A group private key, a group public key, and a group symmetric encryption key are generated and the group private key is encrypted with the group symmetric encryption key. A first shared-secret key is generated based on the user public key and the group private key using a diffie-hellman exchange algorithm. The group symmetric encryption key is encrypted using the first shared-secret key to generate an escrow key. Plaintext data is encrypted using a content symmetric key. A second shared-secret key is generated based on an ephemeral private key and the group public key using a diffie-hellman exchange algorithm. The content symmetric key is encrypted using the second shared-secret key.

Abstract: Systems and techniques are provided for a resource transfer setup and verification. A request for transfer conditions for a transfer of resources may be received from a first computing device. A set of transfer conditions may be generated in response to the request for transfer conditions and sent to the first computing device. The set of transfer conditions and an indication of an acceptance of the set of transfer conditions by a second computing device may be received from the first computing device. A transfer identifier for the set of transfer conditions may be generated from data from the set of transfer conditions which may specify a first sub-transfer. Transfer instructions may be sent to a third computing device, including instructions for a sub-transfer specified in the set of transfer conditions. The set of transfer conditions may be stored with the transfer identifier as a transfer record in non-volatile storage.

Abstract: A data storage device includes a shared command queue, a queue controller, a processor, and a memory. The command queue is configured to queue a plurality of jobs transmitted from a plurality of host processors. The queue controller is configured to classify the plurality of jobs into a plurality of levels of jobs according to priority threshold values and assign jobs of the plurality of levels of jobs the processor. The processor is configured to process the jobs assigned by the queue controller. The memory may store data needed to process the job.

Abstract: A graphics pipeline includes a cache having cache lines that are configured to store data used to process frames in a graphics pipeline. The graphics pipeline is implemented using a processor that processes frames for the graphics pipeline using data stored in the cache. The processor processes a first frame and writes back a dirty cache line from the cache to a memory concurrently with processing of the first frame. The dirty cache line is retained in the cache and marked as clean subsequent to being written back to the memory. In some cases, the processor generates a hint that indicates a priority for writing back the dirty cache line based on a read command occupancy at a system memory controller.

Abstract: According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.

Abstract: An information processing device that includes: a memory; and a monitoring processor that is coupled to the memory, wherein the monitoring processor is configured to, in accordance with temperature information of a chip on which a plurality of monitored processors are mounted, stop execution of tasks designated as having low degrees of priority that are set in advance, among a plurality of tasks that are respectively executed at any of the plurality of monitored processors.

Abstract: An application framework that provides field configuration of exception handlers by one or more applications, rather than defining exceptions at runtime. The exception handler may operate as a remote service in communication with an application executing locally. When an exception is received, the exception handler can consume the exception and return a defined object based on the exception type.

Abstract: The logging techniques described herein can enable using logging tools without having to use different methods for sandbox implementations and push out the log data to storage without problems. The log data is treated as sensitive data and is protected according to the defined security policies. Further, the results may be compressed and encrypted.

Abstract: An electronic apparatus includes: a communicator configured to communicate with an intermediate server and an other electronic apparatus; a memory in which an encryption key and a decryption key generated by the electronic apparatus are stored; and a controller configured to transmit the encryption key generated by the electronic apparatus to the other electronic apparatus through the intermediate server and performs control such that a network with the other electronic apparatus is formed.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces addresses of data elements. A stream head register stores data elements next to be supplied to functional units for use as operands. Stream metadata is stored in response to a stream store instruction. Stored stream metadata is restored to the stream engine in response to a stream restore instruction. An interrupt changes an open stream to a frozen state discarding stored stream data. A return from interrupt changes a frozen stream to an active state.

Abstract: The present invention relates to a flash storage device and an operation control method therefor, and when the flash storage device or a mobile terminal on which the flash storage device is mounted is connected to an external power supply, the flash storage device detects and classifies a power supply type, and according to detection and classification information thereof, the reliability and performance of the data of the device can be improved by performing an internal operation thereof.

Abstract: A memory module includes semiconductor memory devices mounted on a circuit board and a control device mounted on the circuit board. Each semiconductor memory device includes a memory cell array to store data. The control device receives a command and an access address from an external device and provides the command and the access address to the semiconductor memory devices. Each semiconductor memory device performs an address swapping operation to randomly swap a portion of bits of the access address to generate a swapped address in response to a power-up signal or a reset signal, and enables a respective target word-line from among word-lines in the memory cell array such that two or more of the semiconductor memory devices enable different target word-lines in response to the access address.

Abstract: Systems and methods for managing context switches among threads in a processing system. A processor may perform a context switch between threads using separate context registers. A context switch allows a processor to switch from processing a thread that is waiting for data to one that is ready for additional processing. The processor includes control registers with entries which may indicate that an associated context is waiting for data from an external source.

Abstract: A method and apparatus for application thread prioritization to mitigate the effects of operating system noise is disclosed. The method generally includes executing in parallel a plurality of application threads of a parallel application. An interrupt condition of an application thread of the plurality of application threads is detected. A priority of the interrupted application thread is changed relative to priorities of one or more other application threads of the plurality of application threads, and control is returned to the interrupted application thread after the interrupt condition. The interrupted application thread then resumes execution in accordance with the changed priority.

Abstract: A simultaneous multithreading processor is configured to select a first thread of the plurality of threads according to a predefined scheme, and access an instruction completion table to determine whether the first thread is eligible to have a first instruction prioritized. Responsive to determining that the first thread is eligible to have the first instruction prioritized, the simultaneous multithreading processor is further configured to execute the first instruction of the first thread using a dedicated prioritization resource.

Abstract: A method and an apparatus for a memory device including a dynamically updated portion of compressed memory for a virtual memory are described. The memory device can include an uncompressed portion of memory separate from the compressed portion of memory. The virtual memory may be capable of mapping a memory address to the compressed portion of memory. A memory region allocated in the uncompressed portion of memory can be compressed into the compressed portion of memory. As a result, the memory region can become available (e.g. after being compressed) for future allocation requested in the memory device. The compressed portion of memory may be updated to store the compressed memory region. The compressed memory region may be decompressed back to the uncompressed portion in the memory device in response to a request to access data in the compressed memory region.

Abstract: Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

Abstract: In some aspects, systems and methods provide for forming groupings of a plurality of independently-specified computation workloads, such as graphics processing workloads, and in a specific example, ray tracing workloads. The workloads include a scheduling key, which is one basis on which the groupings can be formed. Workloads grouped together can all execute from the same source of instructions, on one or more different private data elements. Such workloads can recursively instantiate other workloads that reference the same private data elements. In some examples, the scheduling key can be used to identify a data element to be used by all the workloads of a grouping. Memory conflicts to private data elements are handled through scheduling of non-conflicted workloads or specific instructions and/or deferring conflicted workloads instead of locking memory locations.

Abstract: A method from managing power state transitions in a computing system is disclosed. A processor may initiate a change in power state from a first initial power state to a first new power state and, in response to initiating the change, send an initial notification to a system integrated circuit using a first communication channel, and deactivate the first communication based on responses to the initial notification. The processor may enter the first new power state in response to the deactivation of the first communication channel, and send a final notification to a management controller using a second communication channel. The management controller may send a message to the system integrated circuit upon receiving the final notification. The system integrated circuit may then transition from a second initial power state to a second new power state based on the message.

Abstract: A method of charging a battery of a computing device includes determining an amount of charge remaining in a battery coupled to the computing device. The method further includes, in response to a determination that the amount of charge remaining in the battery has decreased more than a first predetermined percentage since connection to a power source during a first predetermined amount of time, adjusting a power state of at least one power consuming circuit of the computing device other than the battery.

Abstract: A method and an apparatus for a memory device including a dynamically updated portion of compressed memory for a virtual memory are described. The memory device can include an uncompressed portion of memory separate from the compressed portion of memory. The virtual memory may be capable of mapping a memory address to the compressed portion of memory. A memory region allocated in the uncompressed portion of memory can be compressed into the compressed portion of memory. As a result, the memory region can become available (e.g. after being compressed) for future allocation requested in the memory device. The compressed portion of memory may be updated to store the compressed memory region. The compressed memory region may be decompressed back to the uncompressed portion in the memory device in response to a request to access data in the compressed memory region.

Abstract: A processing pipeline for processing instructions with instructions from multiple threads in flight concurrently may have control circuitry to detect a stalling event associated with a given thread. In response, at least one instruction of the given thread may be flushed from the pipeline, and the control circuitry may trigger fetch circuitry to reduce a fraction of the fetched instructions which are fetched from the given thread. A mechanism is also described to determine when to trigger a predetermined action when a delay in accessing information becomes greater than a delay threshold, and to update the delay threshold based on a difference between a return delay when the information is returned from the storage circuitry and the delay threshold.

Abstract: This document describes techniques and apparatuses for limiting processing resources incurred due to refreshing a user interface. In various embodiments, an event is received, and it is determined whether a delay time period has elapsed. A length of the delay time period is based on a timing of receipt of one or more previous events. If the delay time period has not elapsed, refreshing of the user interface is postponed. When the delay time period elapses, the user interface is refreshed to display an indication of the event.

Abstract: Apparatus for transmitting media content in multimedia streaming system is provided. Apparatus includes a transceiver configured to receive a request for the media content; and transmit a plurality of segments regarding the media content, wherein the plurality of segments comprises an initialization segment (IS) and a media segment (MS), wherein the IS includes a moov box and a stsd box, wherein the stsd box includes sample description entries required to decode all representations within a representation group, and wherein each sample description entry in the stsd box corresponds to coding information of a media component in each of the representations, wherein the MS includes a moof box including a sample description index and a mdat box including media data, and wherein a value of the sample description index is an index of one of the sample description entries in the stsd box.

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to monitor a thread switching overhead parameter for an application executing in a processing system and in response to a determination that the thread switching overhead parameter exceeds a threshold, to activate a thread management algorithm to reduce thread switching in the processing system. Other embodiments are also disclosed and claimed.

Abstract: A method for transmitting a content in a multimedia streaming system is provided. The method includes transmitting, to a client device, control information regarding contents, and transmitting, to the client device, a plurality of segments specified by the control information, where the plurality of segments comprises an initialization segment (IS) and a media segment (MS) and the media data in the plurality of segments are addressed by using relative addressing.

Abstract: Various example implementations are directed to circuits and methods for debugging logic circuits utilizing a data bus for communication. According to an example implementation, an apparatus includes a logic circuit configured to communicate data over a data bus according to a communication protocol. The apparatus also includes a logic analyzer circuit coupled to the data bus. The logic analyzer circuit is configured to capture, in response to a control signal, samples of data signals communicated on the data bus. The logic analyzer circuit determines respective pairs of start and end positions of the data transactions in the captured samples. The logic analyzer circuit outputs the samples of the data signals and a set of metadata including the determined pairs of start and end positions of data transactions in the samples.

Abstract: A data processing system having debugging circuitry and a method for operating the data processing system is provided. In the system, a processor has a cache memory and is coupled to a system bus. An instruction is received which indicates an effective address. The instruction is executed and it is determined if the effective address results in a hit or a miss in the cache. If the effective address results in a hit, data associated with the effective address is provided from the cache to the system bus without modifying a state of the cache. The instruction allows real-time debugging circuits to be able to view the current value of one or more variables in memory that may be hidden from access due to cache hierarchy without modifying the value or impacting the current state of the cache.