Abstract: A method for executing a machine code using a microprocessor includes, after an operation of decoding a current loaded instruction, constructing a mask from the signals generated by an instruction decoder in response to decoding of the current loaded instruction by the decoder. The constructed mask varies as a function of the current loaded instruction. Subsequently, before an operation of decoding a next loaded instruction, the next loaded instruction is unmasked using the constructed mask.

Abstract: In some examples, a system receives, as part of a service to update a data store, a collection of operations that are to be performed with respect to the data store, wherein the collection of operations comprises a plurality of different types of operations for respective data blocks of the data store. Multiple operations of a respective type of the different types of operations are batched to produce a batch of operations of the respective type, and the batch of operations of the respective type is flushed to the data store. The system progressively updates a tracking data structure that tracks batching and flushing of operations of the collection of operations during the service, where the tracking data structure includes metrics representing flushes of batches of operations of the different types. After an interruption of the service, the system resumes the service using a checkpointed version of a resume portion of the tracking data structure.

Abstract: Simple, low-cost systems and methods allow to shape the output spectrum of pre-equalized Tomlinson Harashima Precoding (THP)-equalized transmitters in a manner such as to create a relatively narrow DC null to facilitate transmission over DC-null channels in AC-coupled communication channels. Advantageously, this may be accomplished without significantly adding to the peak value of the to-be-transmitted signal and without the need to resort to high-order filters in the signal path or the use of recursive taps to compensate such filters.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register specifies a circular address mode for the loop, first and second block size numbers and a circular address block size selection. For a first circular address block size selection the block size corresponds to the first block size number. For a first circular address block size selection the block size corresponds to the first block size number. For a second circular address block size selection the block size corresponds to a sum of the first block size number and the second block size number.

Abstract: A method to design parallel TH precoders and a circuit architecture to implement parallel TH precoders have been presented. The parallel design relies on the fact that a TH precoder can be viewed as an IIR filter with an input equal to the sum of the original input to the TH precoder and a compensation signal. The parallel design also relies on the fact that the compensation signal has finite levels. Therefore, precomputation techniques can be applied to calculate intermediate signal values for all possible values of the compensation signal.

Abstract: Methods and apparatus are provided for performing circular buffer addressing. Upper boundaries, lower boundaries, circular buffer lengths, addresses, and offsets are set to allow circular buffer access efficiency. An addition/subtraction unit is provided to simplify implementation. Comparators are rearranged and in some instances replaced with combined adder/comparator logic units. The additional logic units and the rearrangement allow efficient implementation of circular buffer addressing, particularly on programmable chips.