Abstract: A method for restoring a mapper of a processor core includes saving first information in a staging latch. The first information represents a newly dispatched first instruction of the processor core and is saved in an entry latch of a save-and-restore buffer. In response to reception of a flush command of the processor core, the restoration of the mapper is begun with the first information from the staging latch without waiting for a comparison of a flush tag of the flush command with the entry latch of the save-and-restore buffer. A processor core configured to perform the method described above is also provided. A processor core is also provided that includes a dispatch, a mapper, a save-and-restore buffer that includes entry latches and is connected to the mapper via at least one pipeline, and a register disposed in the at least one pipeline.

Abstract: A processor of an aspect includes a decode unit to decode a matrix multiplication instruction. The matrix multiplication instruction is to indicate a first memory location of a first source matrix, is to indicate a second memory location of a second source matrix, and is to indicate a third memory location where a result matrix is to be stored. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the matrix multiplication instruction, is to multiply a portion of the first and second source matrices prior to an interruption, and store a completion progress indicator in response to the interruption. The completion progress indicator to indicate an amount of progress in multiplying the first and second source matrices, and storing corresponding result data to the third memory location, that is to have been completed prior to the interruption.

Abstract: An agent control device configured to execute a plurality of agents and including a processor, the processor being configured to: request execution of each of the agents at a prescribed trigger; store an interruptibility list that stipulates interruptibility of execution for each function of a given agent being executed or for an execution status of the given agent; reference the interruptibility list in order to set permissibility information relating to executability of another one of the agents in conjunction with execution of the given agent; and perform management such that, in a case in which there is a request for execution of the other agent while the given agent is executing and the permissibility information indicates that the other agent is not executable, execution of the given agent continues without responding to the request.

Abstract: Disclosed is a display apparatus including: a first memory configured to store a plurality of instructions to execute a program; a second memory; and a processor configured to load the plurality of instructions stored in the first memory to the second memory, based on execution of the program, sequentially fetch and decode the plurality of instructions loaded to the second memory, and reload a first instruction among the plurality of instructions stored in the first memory to the second memory based on the first instruction being identified as undecodable, and fetch and decode the reloaded first instruction.