Abstract: An electronic control device includes a processing control unit and an information acquisition unit.

Abstract: A control computer for a magnetic resonance imaging system has an analog-to-digital conversion array, a multiplexer array connected to the analog-to-digital conversion array, and a control module that receives at least one input signal via the multiplexer array and the analog-to-digital conversion array. A signal processing board for a magnetic resonance imaging system has a substrate with the aforementioned components thereon that form the aforementioned control computer.

Abstract: Method of automatic synthesis of circuits comprising the generation of a network of regular processes reading or writing data in channels, according to which a single producer process is authorized to write in a channel and a single consumer process is authorized to read in a channel; and a synchronization unit associated with said channel authorizes or disables the implementation of a new iteration of said producer process, respectively consumer process, as a function of a comparison of a position of execution determined as a function of the value of a new iteration collected from the producer process, respectively consumer process, and of a position of execution determined as a function of a last iteration value collected from the consumer process, respectively producer process.

Abstract: This invention is data processing apparatus and method. Data is protecting from corruption using an error correction code by generating an error correction code corresponding to the data. In this invention the data and the corresponding error correction code are carried forward to another set of registers without regenerating the error correction code or using the error correction code for error detection or correction. Only later are error correction detection and correction actions taken. The differing data/error correction code registers may be in differing pipeline phases in the data processing apparatus. This invention forwards the error correction code with the data through the entire datapath that carries the data. This invention provides error protection to the whole datapath without requiring extensive hardware or additional time.

Abstract: A system, method, and computer program product for generating flow-control signals for a processing pipeline is disclosed. The method includes the steps of generating, by a first pipeline stage, a delayed ready signal based on a downstream ready signal received from a second pipeline stage and a throttle disable signal. A downstream valid signal is generated by the first pipeline stage based on an upstream valid signal and the delayed ready signal. An upstream ready signal is generated by the first pipeline stage based on the delayed ready signal and the downstream valid signal.

Abstract: A design structure for a pipeline electronic processor device may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a pipeline electronic circuit that enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit design structure to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.

Abstract: A pipeline electronic circuit and design methodology enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.