Abstract: Embodiments relate to a heterogeneous core microarchitecture. An aspect includes binding, by an operating system that is executing on a processor comprising a core comprising a heterogeneous microarchitecture comprising two or more flows, a job that is being executed by the operating system to a flow of the two or more flows. Another aspect includes issuing an instruction corresponding to the job with a tag indicating the binding of the job to which the instruction corresponds. Yet another aspect includes executing the instruction by the flow in the core that is indicated by the tag.

Abstract: Embodiments relate to a heterogeneous core microarchitecture. An aspect includes binding, by an operating system that is executing on a processor comprising a core comprising a heterogeneous microarchitecture comprising two or more flows, a job that is being executed by the operating system to a flow of the two or more flows. Another aspect includes issuing an instruction corresponding to the job with a tag indicating the binding of the job to which the instruction corresponds. Yet another aspect includes executing the instruction by the flow in the core that is indicated by the tag.

Abstract: Described are methods, systems and computer readable media for data source refreshing.

Abstract: Embodiments relate to a heterogeneous core microarchitecture. An aspect includes binding, by an operating system that is executing on a processor comprising a core comprising a heterogeneous microarchitecture comprising two or more flows, a job that is being executed by the operating system to a flow of the two or more flows. Another aspect includes issuing an instruction corresponding to the job with a tag indicating the binding of the job to which the instruction corresponds. Yet another aspect includes executing the instruction by the flow in the core that is indicated by the tag.

Abstract: Embodiments relate to a heterogeneous core microarchitecture. An aspect includes binding, by an operating system that is executing on a processor comprising a core comprising a heterogeneous microarchitecture comprising two or more flows, a job that is being executed by the operating system to a flow of the two or more flows. Another aspect includes issuing an instruction corresponding to the job with a tag indicating the binding of the job to which the instruction corresponds. Yet another aspect includes executing the instruction by the flow in the core that is indicated by the tag.

Abstract: A method and circuit arrangement provide support for a hybrid pipeline that dynamically switches between out-of-order and in-order modes. The hybrid pipeline may selectively execute instructions from at least one instruction stream that require the high performance capabilities provided by out-of-order processing in the out-of-order mode. The hybrid pipeline may also execute instructions that have strict power requirements in the in-order mode where the in-order mode conserves more power compared to the out-of-order mode. Each stage in the hybrid pipeline may be activated and fully functional when the hybrid pipeline is in the out-of-order mode. However, stages in the hybrid pipeline not used for the in-order mode may be deactivated and bypassed by the instructions when the hybrid pipeline dynamically switches from the out-of-order mode to the in-order mode. The deactivated stages may then be reactivated when the hybrid pipeline dynamically switches from the in-order mode to the out-of-order mode.