Abstract: The disclosed systems, structures, and methods are directed to optimizing address calculations in a computer. This is achieved in a compiler that identifies an address calculation in code that is being compiled and transforms the code by splitting the address calculation into a first portion in which an offset is determined and a second portion, in which the offset is combined with a base pointer to generate an address. The address and the base pointer have a first bit-length, and the offset has a second bit-length shorter than the first bit-length. The offset is determined using an operation performed at the second bit-length. In some implementations the first bit-length is 64 bits and the second bit-length is 32 bits.

Abstract: A programmable hardware system for machine learning (ML) includes a core and a streaming engine. The core receives a plurality of commands and a plurality of data from a host to be analyzed and inferred via machine learning. The core transmits a first subset of commands of the plurality of commands that is performance-critical operations and associated data thereof of the plurality of data for efficient processing thereof. The first subset of commands and the associated data are passed through via a function call. The streaming engine is coupled to the core and receives the first subset of commands and the associated data from the core. The streaming engine streams a second subset of commands of the first subset of commands and its associated data to an inference engine by executing a single instruction.

Abstract: Methods and apparatus relating to techniques for multi-tile memory management. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, a shader core communicatively coupled to the cache memory and comprising a processing element to decompress a first data element extracted from an in-memory database in the cache memory and having a first bit length to generate a second data element having a second bit length, greater than the first bit length, and an arithmetic logic unit (ALU) to compare the data element to a target value provided in a query of the in-memory database. Other embodiments are also disclosed and claimed.

Abstract: The disclosure provides a method and an apparatus for scheduling an out-of-order execution queue in an out-of-order processor. The method includes: constructing a sequence maintenance queue with a same number of items as the out-of-order execution queue, and allocating an empty item for instructions and data entering the out-of-order execution queue, in which the sequence maintenance queue comprises at least one identity (id) field; numbering each item of the out-of-order execution queue sequentially, and recording an id number of each item of the out-of-order execution queue in the id field of the sequence maintenance queue; enabling the instructions to enter an item of the out-of-order execution queue corresponding to an id number pointed by a tail of the sequence maintenance queue; and selecting instructions in ready items for execution from the out-of-order execution queue according to id number information indicated by the sequence maintenance queue.

Abstract: A method of operating a storage device includes storing received input data of a first format, converting the input data into a second format for an operation to be performed on the input data of the second format using an operator included in the storage device, and converting the input data into a second format for an operation to be performed on the input data, through an operator included in the storage device, and re-storing the input data of the second format.

Abstract: The present disclosure discloses a processing element and a neural processing device including the processing element. The processing element includes a weight register configured to store a weight, an input activation register configured to store input activation, a flexible multiplier configured to generate result data by performing a multiplication operation of the weight and the input activation by using a first multiplier of a first precision or using both the first multiplier and a second multiplier of the first precision in response to a calculation mode signal and a saturating adder configured to generate a partial sum by using the result data.

Abstract: A fractal computing device according to an embodiment of the present application may be included in an integrated circuit device. The integrated circuit device includes a universal interconnect interface and other processing devices. The calculating device interacts with other processing devices to jointly complete a user specified calculation operation. The integrated circuit device may also include a storage device. The storage device is respectively connected with the calculating device and other processing devices and is used for data storage of the computing device and other processing devices.

Abstract: A transaction ordering system is configured to order various transactions initiated by one device for execution with another device. The transaction ordering system includes ordering circuitry that is configured to generate two pointer values such that one pointer value corresponds to a transaction identifier (ID) of a transaction that is to be processed, and another pointer value corresponds to a transaction ID of a latest initiated transaction. Based on the two pointer values, the ordering circuitry orders the transactions such that if a first transaction is initiated before a second transaction, a set of data packets associated with the first transaction is transmitted to the transaction initiating device before a set of data packets associated with the second transaction is transmitted.

Abstract: Disclosed is a general-purpose computing accelerator which includes a memory including an instruction cache, a first executing unit performing a first computation operation, a second executing unit performing a second computation operation, an instruction fetching unit fetching an instruction stored in the instruction cache, a decoding unit that decodes the instruction, and a state control unit controlling a path of the instruction depending on an operation state of the second executing unit. The decoding unit provides the instruction to the first executing unit when the instruction is of a first type and provides the instruction to the state control unit when the instruction is of a second type. Depending on the operation state of the second executing unit, the state control unit provides the instruction of the second type to the second executing unit or stores the instruction of the second type as a register file in the memory.

Abstract: A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.

Abstract: Technologies are shown for storing sub-component state data for a resource on a blockchain involving generating a resource data block that corresponds to a resource that includes links that correspond to sub-components of the resource, generating a first sub-component state data block for a sub-component of the resource on a blockchain that includes first state data for the first sub-component, and setting the link for the sub-component to reference the first sub-component state data block. Subsequently, a second sub-component state data block can be generated for the sub-component with second state data and the second sub-component state data block linked to the first sub-component state data block.

Abstract: Various implementations described herein are related to a device having multiplier circuitry with an array of summation result cells that holds summation bit values for shifted arrays added together. The device may include latch circuitry having one or more gated elements disposed between the summation result cells, and the gated elements may be adapted to provide a portion of the summation bit values based on a gating signal.

Abstract: In one disclosed embodiment, a processor includes a first execution unit and a second execution unit, a register file, and a data path including a plurality of lanes. The data path and the register file are arranged so that writing to the register file by the first execution unit and by the second execution unit is allowed over the data path, reading from the register file by the first execution unit is allowed over the data path, and reading from the register file by the second execution unit is not allowed over the data path. The processor also includes a power control circuit configured to, when a transfer of data between the register file and either of the first and second execution units uses less than all of the lanes, power down the lanes of the data path not used for the transfer of the data.

Abstract: A content-addressable processing engine, also referred to herein as CAPE, is provided. Processing-in-memory (PIM) architectures attempt to overcome the von Neumann bottleneck by combining computation and storage logic into a single component. CAPE provides a general-purpose PIM microarchitecture that provides acceleration of vector operations while being programmable with standard reduced instruction set computing (RISC) instructions, such as RISC-V instructions with standard vector extensions. CAPE can be implemented as a standalone core that specializes in associative computing, and that can be integrated in a tiled multicore chip alongside other types of compute engines. Certain embodiments of CAPE achieve average speedups of 14× (up to 254×) over an area-equivalent out-of-order processor core tile with three levels of caches across a diverse set of representative applications.

Abstract: Embodiments disclosed herein provide a method, an electronic device, and a computer program product for processing a computing job. The method includes determining a first dependency relationship between a plurality of computing tasks included in a to-be-processed computing job. The method further includes determining, based on the first dependency relationship and demands of the plurality of computing tasks for computing resources, a group of computing tasks for combination from the plurality of computing tasks. The method further includes combining the group of computing tasks into a target computing task. The method further includes determining, based on the first dependency relationship, a second dependency relationship between the target computing task and computing tasks that are other than the group of computing tasks in the plurality of computing tasks.

Abstract: An approach is provided in which a mapper control unit receives dispatch information corresponding to an instruction that targets a first field in a first register and a second field in a second register, the first register being a first register type and the second register being a second register type. As such, the mapper control unit selects a history buffer entry in a history buffer that is adapted to concurrently store content corresponding to the first register type and the second register type. In turn, the mapper control unit stores first content from the first register's targeted first fields and second content from the second register's targeted second fields into the selected history buffer entry.

Abstract: A multi-threaded microprocessor for processing instructions in threads, including, in one embodiment, (1) at least one processor pipeline for the instructions; (2) a storage for a thread power management configuration; and (3) a power control circuit coupled to said at least one processor pipeline and responsive to said storage for thread power management configuration to control power used by different parts of the at least one processor pipeline depending on the threads, wherein said power control circuit is operable to establish different power voltages in different parts of the at least one processor pipeline depending on the threads.

Abstract: Systems and methods for folding a single instruction multiple data (SIMD) array include a newly defined processing element group (PEG) that allows interconnection of PEGs by abutment without requiring a row or column weave pattern. The interconnected PEGs form a SIMD array that is effectively folded at its center along the North-South axis, and may also be folded along the East-West axis. The folding of the array provides for north and south boundaries to be co-located and for east and west boundaries to be co-located. The co-location allows wrap-around connections to be done with a propagation distance reduced effectively to zero.

Abstract: A device system and method for processing program instructions, for example, to execute intra vector operations. A fetch unit may receive a program instruction defining different operations on data elements stored at the same vector memory address. A processor may include different types of execution units each executing a different one of a predetermined plurality of elemental instructions. Each program instruction may be a combination of one or more of the elemental instructions. The processor may receive a vector of data elements stored non-consecutively at the same vector memory address to be processed by a same one of the elemental instructions and a vector of configuration values independently associated with executing the same elemental instruction on the non-consecutive data elements. At least two configuration values may be different to implement different operations by executing the same elemental instruction using the different configuration values on the vector of non-consecutive data elements.

Abstract: A priority circuit is connected to a reservation station and a plurality of arithmetic units that processes different operations and dispatches, when it is determined that an executable flag indicating that an instruction can be executed by only a specific arithmetic unit is on, an instruction to an arithmetic unit that is different from the specific arithmetic unit and of which a queue is vacant in accordance with the input performed by an instruction decoder and the reservation station.

Abstract: In an embodiment, the present invention discloses a flexible and reconfigurable architecture with efficient memory data management, together with efficient data transfer and relieving data transfer congestion in an integrated circuit. In an embodiment, the output of a first functional component is stored to an input memory of a next functional component. Thus when the first functional component completes its processing, its output is ready to be accessed as input to the next functional component. In an embodiment, the memory device further comprises a partition mechanism for simultaneously accepting output writing from the first functional component and accepting input reading from the second functional component. In another embodiment, the present integrated circuit comprises at least two functional components and at least two memory devices, together with a controller for switching the connections between the functional components and the memory devices.

Abstract: One embodiment of a computing system configured to manage divergent threads in a SIMD thread group includes a stack configured to store state information for processing control instructions. A parallel processing unit is configured to perform the steps of determining if one or more threads diverge during execution of a conditional control instruction. A disable mask allows for the use of conditional return and break instructions in a multithreaded SIMD architecture. Additional control instructions are used to set up thread processing target addresses for synchronization, breaks, and returns.