Abstract: A data processing system includes: a host suitable for generating an initialization command and generating program mode information by selecting a program mode; a memory device including a plurality of memory cells storing a single level data and a multiple-level data; and a controller suitable for: receiving the initialization command and the program mode information from the host; controlling the memory device to perform an initialization operation on the memory device in response to the initialization command; and controlling the memory device to perform a program operation on the memory device based on the program mode information after the initialization operation is performed.

Abstract: The present disclosure includes apparatuses, electronic device readable media, and methods for memory controlled data movement and timing. A number of electronic device readable media can store instructions executable by an electronic device to provide programmable control of data movement operations within a memory. The memory can provide timing control, independent of any associated processor, for interaction between the memory and the associated processor.

Abstract: Embodiments of improved systems and methods are provided herein to reset all datapath logic within a peripheral slave device having multiple clock domains. An embodiment of the disclosed method includes receiving a reset request from a host clock device to reset the peripheral slave device, synchronizing the received reset request to each peripheral clock domain included within the peripheral slave device, and using the synchronized reset request generated within each peripheral clock domain to reset datapath logic contained within that peripheral clock domain.

Abstract: A sensor system includes a sensor having a charge storage device controllably connected to a voltage source under control of a signal under test; and a readout circuit coupled to the charge storage device to determine whether the pulse width of the signal under test has changed greater than a threshold amount according to a voltage at the charge storage device. In some cases, the determination of whether the pulse width of the signal under test has changed includes determining whether the voltage satisfies a condition with respect to a comparison voltage. In some cases, the determination of whether the pulse width of the signal under test has changed is based on a propagation delay through a delay chain, where the propagation delay is dependent on the voltage.

Abstract: A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface.

Abstract: System on chip including plurality of processors including first and second processors; plurality of intellectual properties (IPs) including first and second IPs; memory interface; internal clock circuit to receive reference clock signal, generate first internal clock signal, and provide first internal clock signal to first IP; memory interface clock circuit to receive reference clock signal, generate memory interface clock signal, and provide memory interface clock signal to memory interface; and power management unit (PMU), wherein first internal clock signal drives first IP, memory interface clock signal drives memory interface, PMU generates first control signal based on operational states of plurality of processors, and provides first control signal to internal clock circuit, PMU generates second control signal based on operational states of plurality of processors, and provides second control signal to memory interface clock circuit, internal clock circuit sets clock rate of first internal clock signal

Abstract: Drivers for read and write operations of memory arrays are described. In one aspect, a memory device can include an input/output (I/O) circuit to facilitate read and write operations with the memory device. One driver can generate clock signals for the command circuit to aid with the performance of the write operations. Another driver can generate clock signals for the I/O circuit to aid with the performance of the read operations.

Abstract: Systems and methods for providing audio streams over peripheral component interconnect (PCI) express (PCIE) links are disclosed. In particular, exemplary aspects of the present disclosure are used to calculate an uplink timing requirement and adjust a margin time before a modem encodes audio data so that the encoding is done before data is transmitted to an external network. Further aspects of the present disclosure allow a first integrated circuit (IC) to synchronize its clock with that of the modem.

Abstract: A processor is described having a functional unit of an instruction execution pipeline. The functional unit has comparison bank circuitry and adder circuitry. The comparison bank circuitry is to compare one or more elements of a first input vector against an element of a second input vector. The adder circuitry is coupled to the comparison bank circuitry to add the number of elements of the second input vector that match a value of the first input vector on an element by element basis of the first input vector.

Abstract: Examples embodiments of a method and system for synchronizing active illumination pulses in a multi-sensor imager is provided. Example embodiments of the method disclosed herein include the provision of an illumination pulse for each of N sensors, each of N illumination pulses are set to have the same pulse period and active pulse width. Moreover, example embodiments include setting the active width pulse for each of the N illumination pulses to have maximum exposure time for each of N image sensors, and in further examples, ensuring that the time to capture a frame plus the time interval between subsequent image captures is the same for each sensor. In yet further examples, an offset period between subsequent frame synchronous signals is determined. In yet further example embodiments, an interval between frame captures is adjusted and a negative edge of the frame synchronous signal and an illumination pulse is aligned.

Abstract: Embodiments include methods, systems and circuits for operating an error trapping logic circuit in a memory device. Aspects include receiving, during a first clock cycle, data and check bits for the data from a memory location and determining, during the first clock cycle, whether the data includes any error by calculating an error syndrome from the data and the check bits. Aspects also include determining, during a second clock cycle, a type of the error based on a full decoding of the error syndrome. Aspects further include determining whether to store the data, the check bits and the error syndrome in trap registers of the error trapping logic circuit based on an operating mode of the error trapping logic circuit and the type of the error.

Abstract: The present disclosure relates to a mobile terminal in which a clock frequency of a memory varies as needed and a control method thereof, and the mobile terminal may include a memory provided with a table comprising information on a memory clock frequency corresponding to a different multiple of a preset source clock frequency, and a controller configured to primarily change the memory clock frequency of the mobile terminal to any one of frequencies according to the table in accordance with at least one of functions or applications carried out in the mobile terminal, wherein when the memory clock frequency is primarily changed, the controller secondarily changes the changed memory clock frequency to a frequency different from the changed memory clock frequency according to whether or not the communication performance of the mobile terminal is degraded.

Abstract: An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.

Abstract: A fault diagnosis method for a series hybrid electric vehicle AC/DC (Alternating Current/Direct Current) converter, implementing identifying and diagnosing of an open circuit fault of a power electronic components in an AC/DC converter, and including the following steps: first, establishing a simulation model for a series hybrid electric vehicle AC/DC converter, and selecting a DC bus output current as a fault characteristic; then classifying fault types according to a quantity and locations of faulty power electronic components; next, decomposing the fault characteristic, that is, the DC bus output current by means of fast Fourier transform to different frequency bands, and selecting harmonic ratios of the different frequency bands as fault diagnosing eigenvectors; and finally, identifying the fault types by using a genetic algorithm-based BP (Back Propagation) neural network.

Abstract: A parallel processing apparatus includes, a plurality of operational circuits that execute operations for data in parallel, and a control circuit that, upon an end of operations for a first portion of the data, finds estimated operation time for operations for a second portion that is an object of operations subsequent to the first portion, based on target time for operational processing for the data and a data amount of remaining data for which no operation has been executed in the data, finds a second parallelism of the operations for the second portion, based on a first parallelism of the operations for the first portion, a measurement value of operation time for the operations for the first portion, and the estimated operation time, and causes operational circuits, numbering in a number indicated by the second parallelism among the plurality of operational circuits, to execute the operations for the second portion.

Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

Abstract: A digital state device may include a first circuit terminal that obtains a clock signal from a first integrated circuit. The digital state device may further include a second circuit terminal that transmits the clock signal to a second integrated circuit. The digital state device may further include digital logic circuitry coupled to the first circuit terminal and the second circuit terminal. In response to obtaining an in-band notification signal in reverse of the clock signal and from the second integrated circuit, the digital logic circuitry sets the clock signal to a first predetermined value. In response to the digital logic circuitry determining that the clock signal exceeds a predetermined amount of time at the first predetermined value, the digital logic circuitry sets the clock signal to a second predetermined value that is different from the first predetermined value.

Abstract: Methods, systems, and devices for system-level timing budget are described. Each memory die in a memory device may determine an offset between its system clock signal and its data clock signal. The offsets of each memory die in the memory device may be different; e.g., having different magnitudes and/or polarities. A memory die in the memory device may adjust its own data clock signal by a delay that is based on the offsets of two or more memory die in the device. The memory die may adjust its data clock signal by setting a fuse in a delay adjuster on the memory die. Adjusting the data clock signal may match an offset of a first memory die with an offset of a second memory die.

Abstract: A source driver of a display apparatus includes a receiving controller receiving a first status information signal and outputting a second status information signal and a receiving circuit receiving a transmission signal in response to the second status information signal and recovering the transmission signal to receiving data. The receiving controller includes a transition detection circuit detecting a transition of the first status information signal and outputting a transition detection signal, a delay circuit delaying the transition detection signal by a predetermined time and outputting a delay detection signal, and an output circuit receiving the first status information signal and outputting the second status information signal in response to the delay detection signal.

Abstract: A system and method for providing a configurable timing control of a memory system is disclosed. In one embodiment, the system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has a plurality of flip-flops, a multiplexor coupled to the plurality of flip-flops, a first control block for controlling to hold an input data within the plurality of flip-flops, and a second control block for controlling a timing of an output data from the plurality of flip-flops via the multiplexor with a programmable delay. The input data is received via the second interface. The programmable delay is received via the first interface. The output data is sent out with the timing delay via the third interface.

Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

Abstract: The formulation of a merged sorted list from multiple input sorted lists in multiple phases using an array pair. Initially, the first array is contiguously populated with the input sorted lists. In the first phase, the first and second input sorted lists are merged into a first intermediary merged list within the second array. Each subsequent phase merges a prior intermediary merged list resulting from the prior phase and, a next input sorted list in the first array to generate a next intermediary merged list, or a merged sorted list if there or no further input in the first array. The intermediary merged lists alternate between the first array and the second array from one phase to the next phase.

Abstract: An analysis system that is able to obtain correct encryption key is provided. The analysis system includes a processing circuitry configured to function as a cryptanalysis processing unit. The cryptanalysis processing unit includes: a key candidate extraction unit that is configured to extract, from second data, one or more candidates of key data that include an encryption key that enables to decrypt first data encrypted by a specific encryption scheme, based on data indicating a feature of the key data; and a decryption unit that is configured to extract, from the extracted candidates of key data, correct key data that enables to correctly decrypt the encrypted first data, based on a result of decrypting the first data by use of the extracted candidates of key data.

Abstract: Methods, apparatus, systems, and articles of manufacture to enable status change detection in a low power mode of a microcontroller unit are disclosed herein. An example integrated circuit (IC) includes a controller to determine that the IC is to enter a low power mode. The example IC includes a universal serial bus (USB) physical layer integrated circuit including a transceiver and a detector circuit. The transceiver is disabled while in the low power mode. The detector circuit is enabled while in the low power mode. The detector circuit is to determine whether a pinout of a USB receptacle is shorted to ground. The example IC includes a power control module (PCM) to disable the controller when entering the low power mode. Upon receipt of an indication that the ID pinout of the USB receptacle is shorted to the ground, the PCM initiates a boot sequence.

Abstract: The disclosed computer-implemented method for remediating computer stability issues may include (i) determining that a device has experienced a computer stability problem, (ii) obtaining, from the device, one or more computer-generated log lines that potentially include information pertaining to a cause of the computer stability problem, (iii) directly analyzing text included within the computer-generated log lines, (iv) identifying information relating to the computer stability problem based on the direct analysis of the text, and (v) remediating the device to resolve the computer stability problem. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: According to an embodiments, a system and method for managing electromagnetic interference in an electronic charging unit is disclosed. The operating frequencies of multiple electronic devices interfacing with the electronic charging unit may be dynamically altered to manage electromagnetic interference from each electronic device such that the aggregated electromagnetic interference from all electronic devices remains within predetermined limits.

Abstract: Techniques provide for hardware accelerated data movement between main memory and an on-chip data movement system that comprises multiple core processors that operate on the tabular data. The tabular data is moved to or from the scratch pad memories of the core processors. While the data is in-flight, the data may be manipulated by data manipulation operations. The data movement system includes multiple data movement engines, each dedicated to moving and transforming tabular data from main memory data to a subset of the core processors. Each data movement engine is coupled to an internal memory that stores data (e.g. a bit vector) that dictates how data manipulation operations are performed on tabular data moved from a main memory to the memories of a core processor, or to and from other memories. The internal memory of each data movement engine is private to the data movement engine.

Abstract: A circuit includes a plurality of series-coupled delay buffers and a plurality of logic gates. Each logic gate includes first and second inputs. The first input of each logic gate is coupled to a corresponding one of the delay buffers. The circuit also includes a plurality of flip-flops. Each flip-flop includes a data input and a data output. The data input is coupled to an output of a corresponding one of the logic gates and the data output is coupled to the second input of one of the corresponding logic gates.

Abstract: A capability for management of computing infrastructure under emergency peak capacity conditions is presented. The capability for management of computing infrastructure under emergency peak capacity conditions may support configuration of computing infrastructure to provide additional computing capacity for the emergency peak capacity conditions. The computing infrastructure may include capacity supporting equipment configured to provide computing capacity of the computing infrastructure and environmental equipment configured to support operation of the capacity supporting equipment. The configuration of computing infrastructure to support additional computing capacity for an emergency peak capacity condition may include configuration of capacity supporting equipment to operate in emergency operating mode, rather than normal operating mode, to support the additional computing capacity for the emergency peak capacity condition.

Abstract: The present disclosure provides a personal working system with a dynamic structure, including a central control unit, wherein the central control unit includes a peripheral identifying component for identifying a plurality of peripherals and connecting the plurality of identified peripherals to constitute a working system; a weak (or short-range) communication interface for communication between the central control unit and the peripherals; a strong (or medium-, or long-range) communication interface for communication between the central control unit and an external node; wherein the weak communication interface includes Bluetooth; and the strong communication interface includes a WiFi connection, an Internet connection, a Local Area Network connection, and a wireless telephone connection. An advantage of the present disclosure is that the peripherals will not be outdated and are universal outside of the system.

Abstract: In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.

Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

Abstract: A gate integrated driving circuit for a display panel. The gate integrated driving circuit may comprise N reset circuits. For each of the N reset circuits, a first terminal thereof may be coupled to a reference signal terminal, a second terminal thereof may be coupled to signal output terminals of a set of input and output circuits respectively, a third terminal thereof may be coupled to control terminals of driving circuits of the set of input and output circuits respectively, and a fourth terminal thereof may be coupled to a clock signal terminal coupled to input terminals of the driving circuits of the set of input and output circuits respectively. N may be an integer of at least 3. The set of input and output circuits may contain two or more input and output circuits.

Abstract: A high-speed converter includes at least one converter among a first converter for converting an analog signal into a digital value; a second converter for converting a digital value into an analog signal; a third converter for converting an electrical signal into a digital signal; and a fourth converter for converting a digital signal into an electrical signal, and causes the at least one converter to operate by a method based on information acquired via a network.

Abstract: Methods, systems, and computer program products are provided for supervised power management between a primary platform and a secondary platform. Communication between a primary platform and a secondary platform is established. An application running on the secondary platform is captured. Input features and output measures are collected to build a training set for the application, wherein the input features are collected through direct measurement and the output measures reflect characteristics of the application. Based on the training set, power consumption of the secondary platform with an expected performance level is predicted for a new application running on the secondary platform. Accordingly, an optimal power management policy is derived that minimizes the total power consumption of the primary and secondary platforms.

Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to identify a plurality of dump units associated with a translation table in a storage device, determine a plurality of snapshot markers associated with the plurality of dump units, calculate a first value of a first snapshot marker from the plurality of snapshot markers in the storage device, identify a second snapshot marker from an additional source, the second snapshot marker having a second value satisfying the first value, retrieve a dump unit associated with the second snapshot marker from the additional source, and reconstruct the translation table using the dump unit.

Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

Abstract: Methods and devices for controlling frequency of a bus are disclosed. A method may include determining a total-pending load value indicative of a number of a bytes that will pass through the bus in the future and calculating an expected load value based upon i) the total-pending load value, ii) a number of bytes that passed through the bus during a prior time window, and iii) a time duration the bus was active during the prior time window. The frequency of the bus is decreased if the expected load value is less than a lower threshold and increased if the expected load value is greater than an upper threshold. A frequency of the bus is maintained if the expected load value is greater than the lower threshold and less than the upper threshold.

Abstract: In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent read commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.

Abstract: The computer performance control system includes a performance management unit, a performance integration unit, and an activation unit. A user initiates the activation unit through keyboard and the activation unit activates the performance management unit and the performance integration unit simultaneously. The performance management unit displays the operation statuses of the hardware parts of the computer, and provides a number of modes for a user to set operation frequencies of the hardware parts. The performance integration unit executes a performance integration parameter corresponding a selected mode so as to adjust the performance of the computer. As such, a user can conveniently adjust the performance of the CPU, GPU, and RAM of a multi-tasking computer simultaneously and synchronously through some simple key strokes.

Abstract: A content delivery network (CDN) is enhanced to enable mobile network operators (MNOs) to provide their mobile device users with a content prediction and pre-fetching service. Preferably, the CDN enables the service by providing infrastructure support comprising a client application, and a distributed predictive pre-fetching function. The client application executes in the user's mobile device and enables the device user to subscribe to content (e.g., video) from different websites, and to input viewing preferences for such content (e.g.: “Sports: MLB: Boston Red Sox”). This user subscription and preference information is sent to the predictive pre-fetching support function that is preferably implemented within or across CDN server clusters. A preferred implementation uses a centralized back-end infrastructure, together with front-end servers positioned in association with the edge server regions located nearby the mobile core network.

Abstract: Techniques are described herein for efficient movement of data from a source memory to a destination memory. In an embodiment, in response to a particular memory location being pushed into a first register within a first register space, the first set of electronic circuits accesses a descriptor stored at the particular memory location. The descriptor indicates a width of a column of tabular data, a number of rows of tabular data, and one or more tabular data manipulation operations to perform on the column of tabular data. The descriptor also indicates a source memory location for accessing the tabular data and a destination memory location for storing data manipulation result from performing the one or more data manipulation operations on the tabular data.

Abstract: Techniques are described herein for efficient movement of data from a source memory to a destination memory. In an embodiment, in response to a particular memory location being pushed into a first register within a first register space, the first set of electronic circuits accesses a descriptor stored at the particular memory location. The descriptor indicates a width of a column of tabular data, a number of rows of tabular data, and one or more tabular data manipulation operations to perform on the column of tabular data. The descriptor also indicates a source memory location for accessing the tabular data and a destination memory location for storing data manipulation result from performing the one or more data manipulation operations on the tabular data.

Abstract: Systems, apparatuses, and methods for time shifting tasks in a computing system. A system may include a display control unit configured to process pixels for display. The display control unit may include at least one or more pixel processing pipelines, a control unit, and a pixel buffer. The control unit may be configured to monitor the amount of data in the pixel buffer and set the priority of pixel fetch requests according to the amount of data in the pixel buffer. If the control unit determines that an inter frame period will occur within a given period of time, the control unit may prevent the priority of pixel fetch requests from being escalated if the amount of data in the pixel buffer falls below a threshold. The control unit may also be configured to fill the buffers of the display control unit with as much data as possible during the inter frame period.

Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to identify a plurality of dump units associated with a translation table in a storage device, determine a plurality of snapshot markers associated with the plurality of dump units, calculate a first value of a first snapshot marker from the plurality of snapshot markers in the storage device, identify a second snapshot marker from an additional source, the second snapshot marker having a second value satisfying the first value, retrieve a dump unit associated with the second snapshot marker from the additional source, and reconstruct the translation table using the dump unit.

Abstract: According to one embodiment, a skew correcting device includes a skew calculation circuit and a sampling timing correction circuit. The skew calculation circuit calculates a skew between data and a strobe signal based on sampling values obtained by sampling, at a cycle one half of or shorter than one half of a cycle of the strobe signal, the data and the strobe signal respectively based on a same clock. The sampling timing correction circuit corrects the sampling timing of the data based on the skew calculated by the skew calculation circuit.

Abstract: Embodiments of a synchronous digital system are disclosed that may include generation of clock and synchronization signals. Any of a plurality of available clock signals may be selected for use as a primary clock, without causing clock-induced errors in the synchronous digital system. A clock signal generated on-chip with the synchronous digital system may be automatically selected in response to detecting a condition indicating that use of a local clock may be necessary. Such conditions may include detection of tampering with the synchronous digital system. If an indication of tampering is detected, security measures may be performed.

Abstract: An apparatus and method for managing a frequency of a computer processor. The apparatus includes a power control unit (PCU) to manage power in a computer processor. The PCU includes a data collection module to obtain transaction rate data from a plurality of communication ports in the computer processor and a frequency control logic module coupled to the data collection module, the frequency control logic to calculate a minimum processor interconnect frequency for the plurality of communication ports to handle traffic without significant added latency and to override the processor interconnect frequency to meet the calculated minimum processor interconnect frequency.

Abstract: Certain aspects are directed to an interceptor system for characterizing digital data communicated between certain points in a telecommunication system. The interceptor system includes an interface device and a processing device. The interface device can retrieve data from at least one communication link between a radio frequency processing unit and a baseband processing unit of a telecommunication system. The data includes digital data communicated between the radio frequency processing unit and the baseband processing unit. The processing device can determine an interface link protocol for communicating with terminal equipment via the telecommunication system. The interface link protocol can be determined based on an organization of the data retrieved from the communication link.