Clock Control Of Data Processing System, Component, Or Data Transmission Patents (Class 713/600)
  • Patent number: 10382025
    Abstract: A circuit includes a plurality of series-coupled delay buffers and a plurality of logic gates. Each logic gate includes first and second inputs. The first input of each logic gate is coupled to a corresponding one of the delay buffers. The circuit also includes a plurality of flip-flops. Each flip-flop includes a data input and a data output. The data input is coupled to an output of a corresponding one of the logic gates and the data output is coupled to the second input of one of the corresponding logic gates.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: August 13, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Robert Callaghan Taft
  • Patent number: 10367881
    Abstract: A capability for management of computing infrastructure under emergency peak capacity conditions is presented. The capability for management of computing infrastructure under emergency peak capacity conditions may support configuration of computing infrastructure to provide additional computing capacity for the emergency peak capacity conditions. The computing infrastructure may include capacity supporting equipment configured to provide computing capacity of the computing infrastructure and environmental equipment configured to support operation of the capacity supporting equipment. The configuration of computing infrastructure to support additional computing capacity for an emergency peak capacity condition may include configuration of capacity supporting equipment to operate in emergency operating mode, rather than normal operating mode, to support the additional computing capacity for the emergency peak capacity condition.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: July 30, 2019
    Assignees: Nokia of America Corporation, Alcatel Lucent
    Inventors: Eric J. Bauer, John H. Haller, Frederik G A Vandeputte
  • Patent number: 10313859
    Abstract: The present disclosure provides a personal working system with a dynamic structure, including a central control unit, wherein the central control unit includes a peripheral identifying component for identifying a plurality of peripherals and connecting the plurality of identified peripherals to constitute a working system; a weak (or short-range) communication interface for communication between the central control unit and the peripherals; a strong (or medium-, or long-range) communication interface for communication between the central control unit and an external node; wherein the weak communication interface includes Bluetooth; and the strong communication interface includes a WiFi connection, an Internet connection, a Local Area Network connection, and a wireless telephone connection. An advantage of the present disclosure is that the peripherals will not be outdated and are universal outside of the system.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: June 4, 2019
    Assignee: Zhenhua LI
    Inventors: Zhenhua Li, Shuang Sa
  • Patent number: 10235327
    Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: March 19, 2019
    Assignee: INTEL CORPORATION
    Inventors: Huimin Chen, Duane G. Quiet
  • Patent number: 10234930
    Abstract: In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Victor W. Lee, Edward T. Grochowski, Daehyun Kim, Yuxin Bai, Sheng Li, Naveen K. Mellempudi, Dhiraj D. Kalamkar
  • Patent number: 10223324
    Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventors: Huimin Chen, Duane G. Quiet
  • Patent number: 10210834
    Abstract: A gate integrated driving circuit for a display panel. The gate integrated driving circuit may comprise N reset circuits. For each of the N reset circuits, a first terminal thereof may be coupled to a reference signal terminal, a second terminal thereof may be coupled to signal output terminals of a set of input and output circuits respectively, a third terminal thereof may be coupled to control terminals of driving circuits of the set of input and output circuits respectively, and a fourth terminal thereof may be coupled to a clock signal terminal coupled to input terminals of the driving circuits of the set of input and output circuits respectively. N may be an integer of at least 3. The set of input and output circuits may contain two or more input and output circuits.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: February 19, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Min He, Haixia Xu, Dongxu Han, Meng Li
  • Patent number: 10175739
    Abstract: Methods, systems, and computer program products are provided for supervised power management between a primary platform and a secondary platform. Communication between a primary platform and a secondary platform is established. An application running on the secondary platform is captured. Input features and output measures are collected to build a training set for the application, wherein the input features are collected through direct measurement and the output measures reflect characteristics of the application. Based on the training set, power consumption of the secondary platform with an expected performance level is predicted for a new application running on the secondary platform. Accordingly, an optimal power management policy is derived that minimizes the total power consumption of the primary and secondary platforms.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: January 8, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventor: Hwisung Jung
  • Patent number: 10175896
    Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to identify a plurality of dump units associated with a translation table in a storage device, determine a plurality of snapshot markers associated with the plurality of dump units, calculate a first value of a first snapshot marker from the plurality of snapshot markers in the storage device, identify a second snapshot marker from an additional source, the second snapshot marker having a second value satisfying the first value, retrieve a dump unit associated with the second snapshot marker from the additional source, and reconstruct the translation table using the dump unit.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: January 8, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ajith Kumar Battaje, Tanay Goel, Rajendra Prasad Mishra
  • Patent number: 10178450
    Abstract: A high-speed converter includes at least one converter among a first converter for converting an analog signal into a digital value; a second converter for converting a digital value into an analog signal; a third converter for converting an electrical signal into a digital signal; and a fourth converter for converting a digital signal into an electrical signal, and causes the at least one converter to operate by a method based on information acquired via a network.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: January 8, 2019
    Assignee: FANUC CORPORATION
    Inventors: Kouji Hada, Yoshito Miyazaki, Hideki Otsuki, Masao Kamiguchi, Susumu Itou, Hitoshi Hirota
  • Patent number: 10127187
    Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: November 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: Huimin Chen, Duane G. Quiet
  • Patent number: 10102173
    Abstract: Methods and devices for controlling frequency of a bus are disclosed. A method may include determining a total-pending load value indicative of a number of a bytes that will pass through the bus in the future and calculating an expected load value based upon i) the total-pending load value, ii) a number of bytes that passed through the bus during a prior time window, and iii) a time duration the bus was active during the prior time window. The frequency of the bus is decreased if the expected load value is less than a lower threshold and increased if the expected load value is greater than an upper threshold. A frequency of the bus is maintained if the expected load value is greater than the lower threshold and less than the upper threshold.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: October 16, 2018
    Assignee: QUALCOMM Innovation Center, Inc.
    Inventors: Tatyana Brokhman, Asutosh Das, Talel Shenhar
  • Patent number: 10090026
    Abstract: In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent read commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: October 2, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Hyun Yoo Lee, Jongtae Kwak, Suryanarayana Tatapudi
  • Patent number: 10073757
    Abstract: The computer performance control system includes a performance management unit, a performance integration unit, and an activation unit. A user initiates the activation unit through keyboard and the activation unit activates the performance management unit and the performance integration unit simultaneously. The performance management unit displays the operation statuses of the hardware parts of the computer, and provides a number of modes for a user to set operation frequencies of the hardware parts. The performance integration unit executes a performance integration parameter corresponding a selected mode so as to adjust the performance of the computer. As such, a user can conveniently adjust the performance of the CPU, GPU, and RAM of a multi-tasking computer simultaneously and synchronously through some simple key strokes.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: September 11, 2018
    Assignee: EVGA CORPORATION
    Inventor: Tai-Sheng Han
  • Patent number: 10063653
    Abstract: A content delivery network (CDN) is enhanced to enable mobile network operators (MNOs) to provide their mobile device users with a content prediction and pre-fetching service. Preferably, the CDN enables the service by providing infrastructure support comprising a client application, and a distributed predictive pre-fetching function. The client application executes in the user's mobile device and enables the device user to subscribe to content (e.g., video) from different websites, and to input viewing preferences for such content (e.g.: “Sports: MLB: Boston Red Sox”). This user subscription and preference information is sent to the predictive pre-fetching support function that is preferably implemented within or across CDN server clusters. A preferred implementation uses a centralized back-end infrastructure, together with front-end servers positioned in association with the edge server regions located nearby the mobile core network.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: August 28, 2018
    Assignee: Akamai Technologies, Inc.
    Inventors: Prasandh Balakrishnan, James V. Luciani, Ravi S. Aysola, Richard G. D'Addio, Lawrence Gensch, Ittehad Shaikh
  • Patent number: 10061714
    Abstract: Techniques are described herein for efficient movement of data from a source memory to a destination memory. In an embodiment, in response to a particular memory location being pushed into a first register within a first register space, the first set of electronic circuits accesses a descriptor stored at the particular memory location. The descriptor indicates a width of a column of tabular data, a number of rows of tabular data, and one or more tabular data manipulation operations to perform on the column of tabular data. The descriptor also indicates a source memory location for accessing the tabular data and a destination memory location for storing data manipulation result from performing the one or more data manipulation operations on the tabular data.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: August 28, 2018
    Assignee: Oracle International Corporation
    Inventors: David A. Brown, Rishabh Jain, Michael Duller, Sam Idicula, Erik Schlanger, David Joseph Hawkins
  • Patent number: 10055809
    Abstract: Systems, apparatuses, and methods for time shifting tasks in a computing system. A system may include a display control unit configured to process pixels for display. The display control unit may include at least one or more pixel processing pipelines, a control unit, and a pixel buffer. The control unit may be configured to monitor the amount of data in the pixel buffer and set the priority of pixel fetch requests according to the amount of data in the pixel buffer. If the control unit determines that an inter frame period will occur within a given period of time, the control unit may prevent the priority of pixel fetch requests from being escalated if the amount of data in the pixel buffer falls below a threshold. The control unit may also be configured to fill the buffers of the display control unit with as much data as possible during the inter frame period.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: August 21, 2018
    Assignee: Apple Inc.
    Inventors: Peter F. Holland, Benjamin K. Dodge
  • Patent number: 10055358
    Abstract: Techniques are described herein for efficient movement of data from a source memory to a destination memory. In an embodiment, in response to a particular memory location being pushed into a first register within a first register space, the first set of electronic circuits accesses a descriptor stored at the particular memory location. The descriptor indicates a width of a column of tabular data, a number of rows of tabular data, and one or more tabular data manipulation operations to perform on the column of tabular data. The descriptor also indicates a source memory location for accessing the tabular data and a destination memory location for storing data manipulation result from performing the one or more data manipulation operations on the tabular data.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: August 21, 2018
    Assignee: Oracle International Corporation
    Inventors: David A. Brown, Rishabh Jain, Sam Idicula, Erik Schlanger, David Joseph Hawkins
  • Patent number: 10031680
    Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to identify a plurality of dump units associated with a translation table in a storage device, determine a plurality of snapshot markers associated with the plurality of dump units, calculate a first value of a first snapshot marker from the plurality of snapshot markers in the storage device, identify a second snapshot marker from an additional source, the second snapshot marker having a second value satisfying the first value, retrieve a dump unit associated with the second snapshot marker from the additional source, and reconstruct the translation table using the dump unit.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: July 24, 2018
    Assignee: HGST Netherlands B.V.
    Inventors: Ajith Kumar Battaje, Tanay Goel, Rajendra Prasad Mishra
  • Patent number: 10020035
    Abstract: According to one embodiment, a skew correcting device includes a skew calculation circuit and a sampling timing correction circuit. The skew calculation circuit calculates a skew between data and a strobe signal based on sampling values obtained by sampling, at a cycle one half of or shorter than one half of a cycle of the strobe signal, the data and the strobe signal respectively based on a same clock. The sampling timing correction circuit corrects the sampling timing of the data based on the skew calculated by the skew calculation circuit.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: July 10, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masayuki Usuda, Hiroo Yabe
  • Patent number: 10007293
    Abstract: Embodiments of a synchronous digital system are disclosed that may include generation of clock and synchronization signals. Any of a plurality of available clock signals may be selected for use as a primary clock, without causing clock-induced errors in the synchronous digital system. A clock signal generated on-chip with the synchronous digital system may be automatically selected in response to detecting a condition indicating that use of a local clock may be necessary. Such conditions may include detection of tampering with the synchronous digital system. If an indication of tampering is detected, security measures may be performed.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: June 26, 2018
    Assignee: Coherent Logix, Incorporated
    Inventors: Carl S. Dobbs, Michael R. Trocino, Kenneth R. Faulkner, Christopher L. Schreppel
  • Patent number: 9977482
    Abstract: An apparatus and method for managing a frequency of a computer processor. The apparatus includes a power control unit (PCU) to manage power in a computer processor. The PCU includes a data collection module to obtain transaction rate data from a plurality of communication ports in the computer processor and a frequency control logic module coupled to the data collection module, the frequency control logic to calculate a minimum processor interconnect frequency for the plurality of communication ports to handle traffic without significant added latency and to override the processor interconnect frequency to meet the calculated minimum processor interconnect frequency.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Ankush Varma, Ian M. Steiner, Krishnakanth V. Sistla, Matthew M. Bace, Vivek Garg, Martin T. Rowland, Jeffrey S. Wilder
  • Patent number: 9898362
    Abstract: Systems, methods, circuits and computer-readable mediums for multi-channel RAM system with error-correcting code (ECC) protection for partial writes are provided. In one aspect, a method includes accessing a plurality of bursts of partial data units from a plurality of respective bus ports, forming a plurality of memory addresses for a plurality of memory channels by interleaving addresses from the plurality of bus ports, and performing read-modify-write (RMW) error-correcting code (ECC) processes to write partial data units from the plurality of bursts into memory portions corresponding to the formed memory addresses in the plurality of memory channels.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: February 20, 2018
    Assignee: Atmel Corporation
    Inventor: Franck Lunadier
  • Patent number: 9805038
    Abstract: A method, article of manufacture, and apparatus for efficient conflict resolution among stateless processes is disclosed. In some embodiments, a file system view request is sent to a process manager. A check is then made to ensure that a connection to the requested file system is available. A stateless process to interact with the file system is created, a stateless process to display the file system is created, and a state machine to check the validity of operational requests to be performed on the file system is also created. A display is then used to select one conflict resolution mechanism. A plurality of operational requests to interact with the file system is sent to the process manager. For each operational request, the state machine is used to check for valid requests. The valid requests are then performed. For each invalid operational request, the selected conflict resolution mechanism is used to determine whether to terminate or perform the invalid operational request.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: October 31, 2017
    Assignee: EMC IP Holding Company LLC
    Inventor: Michael D. Hartway
  • Patent number: 9778677
    Abstract: A bus interface, for allowing a plurality of devices to communicate with one another via the bus, includes a bit timing symmetrization component for symmetrizing the bit stream. For an incoming bit stream, the bit timing symmetrization component further includes an input delay filter for delaying recessive to dominant edges for a given received bit stream and sampling the delayed input signal at the sample point. In one embodiment, bit timing synchronization may still be performed with the undelayed recessive to dominant edges. For an outgoing bit stream, the bit timing symmetrization component transmits a recessive bit, that followed a previously transmitted dominant bit, before the start of the next bit time, and transmits a dominant bit, that followed a previously transmitted recessive bit, with a delay of a configurable amount of time.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: October 3, 2017
    Assignee: Infineon Technologies AG
    Inventor: Achim Vowe
  • Patent number: 9753830
    Abstract: A serial transmission peripheral device for transmitting serial transmission data with a variable data length includes a pulse forming unit; and a register programmable to set a desired transmission length. The peripheral device is operable to determine an actual transmission length and calculate a length of a pause pulse and to add the pause pulse at the end of a transmission to generate a transmission having a constant length.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: September 5, 2017
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Stephen Bowling, Samar Naik
  • Patent number: 9715397
    Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: July 25, 2017
    Assignee: Intel Corporation
    Inventors: Andrew Herdrich, Ramesh Illikkal, Donald Newell, Ravishankar Iyer, Vineet Chadha
  • Patent number: 9703352
    Abstract: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: July 11, 2017
    Assignee: Intel Corporation
    Inventors: Travis T. Schluessler, Russell J. Fenger
  • Patent number: 9633718
    Abstract: There is provided a nonvolatile memory device having a writing error preventing function with high noise resistance. This structure includes a switch and a noise filter circuit connected in parallel to a clock terminal, wherein a clock pulse monitoring circuit compares the number of clocks input from the clock terminal with a prescribed number, and when detecting abnormality in the number of clocks, switches to a noise countermeasure mode in which the switch is turned off to validate the noise filter circuit.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: April 25, 2017
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Makoto Mitani, Hironori Hayashida
  • Patent number: 9575897
    Abstract: A method includes, in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions include symbolic expressions that specify memory addresses in an external memory in terms of one or more register names. Based on respective formats of the memory addresses specified in the symbolic expressions, a sequence of load instructions that access a predictable pattern of memory addresses in the external memory is identified. At least one cache line that includes a plurality of data values is retrieved from the external memory. Based on the predictable pattern, two or more of the data values that are requested by respective load instructions in the sequence are saved from the cache line to the internal memory. The saved data values are assigned to be served from the internal memory to one or more instructions that depend on the respective load instructions.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: February 21, 2017
    Assignee: CENTIPEDE SEMI LTD.
    Inventors: Noam Mizrahi, Jonathan Friedmann
  • Patent number: 9537488
    Abstract: An field programmable gate array (FPGA) includes a circuit implemented using the FPGA fabric. The FPGA further includes another circuit implemented as hardened circuitry. The FPGA also includes a configurable interface circuit that is adapted to couple together the two circuits.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: January 3, 2017
    Assignee: Altera Corporation
    Inventors: Sean R. Atsatt, Kent Orthner, Daniel R. Mansur
  • Patent number: 9432011
    Abstract: A semiconductor integrated circuit includes, a fixed frequency-division clock generation unit configured to generate a fixed frequency-division clock with a fixed frequency based on an output clock of a clock source, a variable frequency-division clock generation unit configured to generate a variable frequency-division clock with a variable frequency based on the output clock of the clock source, and a data path selection unit configured to select a data path. The data path selection unit selects a data path with or without a synchronization unit for converting the data into clock-synchronous data on a receiving side according to whether the variable frequency-division clock is or is not, respectively, generated by the variable frequency-division clock generation unit.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: August 30, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hiroaki Niitsuma
  • Patent number: 9430247
    Abstract: A semiconductor device includes a power-up signal generation unit suitable for receiving a first power supply voltage and a second power supply voltage higher the first power supply voltage and generating a power-up signal when the first and second power supply voltage increase to reach target levels, respectively, a voltage level adjusting unit suitable for generating a third power supply voltage by adjusting a voltage level of the second power supply voltage, a boot-up signal generation unit suitable for generating a boot-up signal in response to the power-up signal, and a circuit operation unit suitable for performing a boot-up operation using the third power supply voltage in response to the boot-up signal.
    Type: Grant
    Filed: December 15, 2013
    Date of Patent: August 30, 2016
    Assignee: SK Hynix Inc.
    Inventor: Yun-Seok Hong
  • Patent number: 9405431
    Abstract: An application control approach using generated position information of a control device and adapted for use with a display, such as a monitor or TV, is disclosed. The control device may be conveniently held by a user. An imager is employed to image the control device to detect reference fields and generate position information. This information is used by the control device to control an application.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: August 2, 2016
    Assignee: I-INTERACTIVE LLC
    Inventor: David L. Henty
  • Patent number: 9395208
    Abstract: The disclosure relates to a meter for monitoring usage of power provided by a power transmission system to a site and a related method. The meter comprises: a meter module connected to a power feed associated with the transmission system to provide readings relating to the power; a connection to a household AC power supply providing power to the meter; a rectifier circuit connected to the AC power to generate a DC power signal; a voltage detection circuit to detect a low voltage condition where an output from the rectifier circuit drops below an operational threshold for the meter and to generate a low voltage signal upon detection of same; and a message generation module for receiving the low voltage signal and for generating a power loss message for transmission carried on a message carrier having on a carrier having frequency between approximately 2 MHz and 30 MHz.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: July 19, 2016
    Assignee: Corinex Communications Corp.
    Inventors: Peter Sobotka, Xiao Ming Shi, Yan Long
  • Patent number: 9378175
    Abstract: A data processing apparatus comprising at least one initiator operable to communicate with at least one recipient via a bus; said at least one initiator comprising an output port for sending data to said bus and an input port for receiving data from said bus; said data processing apparatus further comprising an initiator clock signal generator, an initiator output enable signal generator and an initiator input enable signal generator, said initiator being clocked by said initiator clock signal; said output port being clocked by said initiator output enable signal such that said output port is operable to assert data to a write channel on said bus in response to said initiator output enable signal having a first predetermined level and said input port is operable to latch data received on a read channel on said bus in response to said initiator input enable signal having a second predetermined level; wherein said initiator output enable signal generator and initiator input enable signal generator are configure
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: June 28, 2016
    Assignee: ARM Limited
    Inventors: Nicolas Chaussade, Pierre Michel Broyer, Phillipe Luc
  • Patent number: 9380331
    Abstract: An exemplary method includes a dynamic help content presentation system detecting a user input command provided by a user, the user input command requesting help with content being presented by a media content access subsystem, identifying, in response to the user input command, a context of the content being presented by the media content access subsystem, and automatically presenting help content associated with the identified context by way of a mobile device while the content is being presented by the media content access subsystem. Corresponding methods and systems are also disclosed.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: June 28, 2016
    Assignee: VERIZON PATENT AND LICENSING INC.
    Inventors: Brian F. Roberts, Donald H. Relyea, Anthony M. Lemus
  • Patent number: 9311207
    Abstract: Described are techniques for processing I/O (input/output) operations. A first observed value of a first performance metric denoting any of a current workload or performance for a first physical device is determined. A target time delay for the first physical device is identified based on the first observed value of the first performance metric. The target time delay specifies a minimum time delay between consecutive host I/Os directed to the first physical device. The target time delay is enforced with respect to consecutive host I/Os directed to the first physical device.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: April 12, 2016
    Assignee: EMC Corporation
    Inventors: Marik Marshak, Alexandr Veprinsky, Dan Aharoni, Stephen F. Modica
  • Patent number: 9304580
    Abstract: An electronic circuit includes a processor having a functional mode and a low power mode, said processor comprising state flip-flops and additional flip-flops; said state flip flips are arranged to store state information about a state of the processor when the processor is in the functional mode; said state flip-flops comprise non-reset flip-flops that are arranged to store at least one non-reset value when the processor exits the functional mode; a power management circuit for providing power to the processor when the processor is in the functional mode, and for preventing power from the processor when the processor is in the low power mode; a non-reset value identification module, coupled to the state flip-flops, said non-reset value identification module is arranged to identify the non-reset flip-flops and to generate non-reset information that identifies the non-reset flip-flops; and a recovery circuit, coupled to a memory module and to the state flip-flops.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: April 5, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael Priel, Dan Kuzmin, Anton Rozen
  • Patent number: 9262837
    Abstract: Circuits, methods, and apparatus for modifying the data rate of a data bus. In a circuit having two processors coupled by a data bus, the processors each learn that the other is capable of operating at a modified data rate. The data rate is then changed to the modified rate. Each processor may learn of the other's capability by reading a vendor identification, for example from a vendor defined message stored on the other processor. Alternately, each processor may provide an instruction to the other to operate at the modified rate, for example by writing to the other processor's extended capability registers. In another circuit having two processors communicating over a bus, it is determined that both are capable of transmitting and receiving data at a modified data rate. An instruction is provided to one or both of the processors to transmit at the modified rate.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: February 16, 2016
    Assignee: NVIDIA Corporation
    Inventors: Anthony Michael Tamasi, William Tsu, Colyn S. Case, David G. Reed
  • Patent number: 9256493
    Abstract: In accordance with some embodiments, memory modules containing phase change memory elements may be organized so that each memory integrated circuit includes both data and error correcting code. As a result of including the error correcting code in each integrated circuit, extra accesses of the memory module to extract the error correcting code can be avoided, improving the performance of the overall memory module in some embodiments.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: February 9, 2016
    Assignee: Intel Corporation
    Inventors: Murugasamy K. Nachimuthu, Mohan J. Kumar, Debaleena Das, Dimitrios Ziakas
  • Patent number: 9251723
    Abstract: Example embodiments of the systems and methods of multidimensional encrypted data transfer disclosed herein also introduce novel and unobvious methods to store and access information. In example embodiments of the systems and methods of multidimensional encrypted data transfer disclosed herein, a multidimensional data structure is developed. For example, at least one additional dimension is added to a 2D data structure. Data may be encoded within multiple facets. Example embodiments of the multidimensional encoding include non-limiting examples of stacking or providing images or tiles in a very short period of time and moving a 3-dimensional object in space. In one example application, a number of distinct 2D data structures are presented over a time period in a .gif file.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 2, 2016
    Inventors: Jonas Moses, Luke Lovette
  • Patent number: 9229886
    Abstract: A method for transferring management data between processors over an Input/Output (I/O) bus system (232) includes receiving the management data at a managing processor (212) from a managed host processor (202) over the I/O bus system; and storing the management data in an addressable memory (304) of an I/O bus interface device (218) of the managing processor (212).
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: January 5, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: John M. Hemphill, Thomas J. Bonola
  • Patent number: 9223366
    Abstract: An electronic apparatus that includes a CPU and at least one device and that is identical to or different from an electronic apparatus in which the CPU is capable of simultaneously executing multiple applications. The electronic apparatus includes: a determiner that determines usage rates of the CPU and the device for each application being executed, on the basis of at least one of statistical information and log information of the CPU and the device; a divider that determines proportions of power consumptions of the CPU and the device relative to a power consumption of the entire electronic apparatus; and an estimator that estimates a proportion of a power consumption for each application relative to the power consumption of the entire electronic apparatus, on the basis of the determined usage rates and the determined proportions.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: December 29, 2015
    Assignee: Sony Corporation
    Inventors: Takashi Kida, Masahiro Tamori, Hiroki Nagahama
  • Patent number: 9208120
    Abstract: This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: December 8, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kai Chirca, Matthew D. Pierson, Daniel B. Wu, Timothy D. Anderson
  • Patent number: 9203601
    Abstract: The CDR circuit 100 includes first to second data delaying cells ID1, ID2. The CDR circuit 100 includes first to fourth oscillation delaying cells IC1, IC2, IC3, IC4. The CDR circuit 100 outputs a second data signal d2 at a data output terminal TDout as a recovery data signal Dout. The CDR circuit 100 outputs an oscillation clock signal a0 at a clock output terminal TRCK as a recovery clock signal RCK.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: December 1, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junji Wadatsumi, Shouhei Kousai, Daisuke Miyashita
  • Patent number: 9201819
    Abstract: A command processing apparatus and method are provided for optimally processing commands issued asynchronously from a plurality of masters to a storage apparatus including a plurality of banks, where each master issues commands for a bank 0 and a bank 1 alternately. The command processing apparatus includes buffer units that obtain commands issued from the plurality of masters, an arbitration unit that arbitrates the obtained commands, and an issuance unit that issues commands to the storage apparatus according to the arbitration. The arbitration unit reads the commands of the plurality of masters obtained in the buffer units, and selects one command as a result of arbitration. The arbitration unit waits until a next command of a master relating to the selected command becomes readable, and reads the next command. The issuance unit consecutively issues the selected command and the read command to the storage apparatus.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: December 1, 2015
    Assignee: SOCIONEXT INC.
    Inventors: Nobuyuki Ichiguchi, Tetsuji Mochida, Ryuta Nakanishi, Takaharu Tanaka
  • Patent number: 9197515
    Abstract: The present invention provides a method of processing information associated with off-line billed communications in a communications network. The method includes providing at least one charging data record to a rating engine. The charging data record(s) include information associated with at least one off-line communication and are provided in response to receiving the charging data record(s). The rating engine determines costs of the off-line communication(s) at a time determined based on at least one time control category associated with the charging data record(s). The method also includes modifying the charging data record(s) to include information indicative of the cost(s) of the off-line communication(s) determined by the rating engine.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: November 24, 2015
    Assignee: Alcatel Lucent
    Inventors: Yigang Cai, Xiangyang Li
  • Patent number: 9195296
    Abstract: Apparatus and methods are disclosed for power optimization in a wireless device. The apparatus and methods effect monitoring the amount of data stored in a data buffer that buffers data input to and data output from a processor. Dependent on the amount of data stored in the buffers parameters of a control function, such as a Dynamic Clock and Voltage Scaling (DCVS) function are modified based on the amount of data stored in the data buffer. By modifying or pre-empting the parameters of the control function, which controls at least processor frequency, the processor can process applications more dynamically over default parameter settings, especially in situations where one or more real-time activities having strict time constraints for completion are being handled by the processor as evinced by increased buffer depth. As a result, power usage is further optimized as the control function is more responsive to processing conditions.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: November 24, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Reza Shahidi, Alex Kuang-Hsuan Tu, Brian J. Salsbery, Ajith T. Payyappilly, Xiaodong Chen
  • Patent number: 9176651
    Abstract: An electronic device can receive a request from an accessory to provide a user interface to be displayed by the accessory. The electronic device can determine whether an accessory has a first set of one or more user input devices or a second set of one or more user input devices. In accordance with a determination that the accessory has a first set of one or more user input devices, the electronic device can provide to the accessory a first user interface configured to be controlled with the first set of user input devices. In accordance with a determination that the accessory has a second set of one or more user input devices, the electronic device can provide to the accessory a second user interface, different from the first user interface, the second user interface configured to be controlled with the second set of user input devices.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: November 3, 2015
    Assignee: Apple Inc.
    Inventors: Emily Clark Schubert, Peter T. Langenfeld