Abstract: Methods and systems for cross-layer forgiveness exploitation include executing one or more applications using a processing platform that includes a first reliable processing core and at least one additional processing core having a lower reliability than the first processing core, modifying application execution according to one or more best-effort techniques to improve performance, and controlling parameters associated with the processing platform and the best-effort layer that control performance and error rate such that performance is maximized in a region of low hardware-software interference.

Abstract: A method and system of deadlock detection in a parallel program, the method comprising: recording lock events during the operation of the parallel program and a first order relation among the lock events; converting information relevant to the operation of the parallel program into gate lock events and recording the gate lock events; establishing a second order relation among the gate lock events and lock events associated with the gate lock events and adding the second order relation to the first order relation; constructing a lock graph corresponding to the operation procedure of the parallel program based on the added first order relation; and performing deadlock detection on the constructed lock graph. The deadlock detection method of the invention can improve the accuracy of deadlock detection without depending on the deadlock detection algorithm per se, and can be applied with facility to various development environments and reduce development costs.

Abstract: A method for performance monitoring in a computing system is described. In some embodiments, an addressable memory stores data and instructions for performing context switch sampling. A processor includes hardware event counters, and is coupled with the addressable memory to access said instructions and in response to said instructions, the processor counts occurrences of a first hardware event in a first hardware event counter and counts occurrences of a second hardware event in a second hardware event counter. After a specified number of occurrences of the first hardware event have been counted, the second hardware event counter is sampled and hardware event counters are reset. In some embodiments the processor counts occurrences of segment register load events in the first hardware event counter and then records the sampled second hardware event counter value with a process identifier value and/or a thread identifier value.