Abstract: A method, computer program product, and/or system is disclosed for changing the events monitored by a processor including: determining whether a change in the monitoring of the first event to the second different event has been requested; copying, in response to a request to change the monitoring of the first event to the second different event, op-codes from memory into microcode executable by a general processing engine; and executing the op-codes from memory by the general processing engine to change the first event monitored by the counter to the second different event.

Abstract: A program is executed on a processor to produce execution events. The execution events are traced using a first trace mode during a first portion of the program execution, wherein a portion of trace information for the execution events is omitted from a trace report while tracing in the first trace mode. The mode of tracing is dynamically changed to a second trace mode in response to an event trigger, such that all execution events that occur during the change of mode are captured. Execution events are traced during a second portion of the program execution using the second trace mode, wherein additional trace information for the execution events is included in the trace report while tracing in the second trace mode. The trace mode may be dynamically switched between the two trace modes during execution of the program.

Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

Abstract: A method includes incrementing a counter with transmission of a process data from a first processor to a second processor, periodically decrementing the counter, if the counter is greater than a predetermined floor threshold value, wherein a period is a predetermined time interval; and stalling the first processor, if the counter is above a configurable load threshold value, so as to re-schedule the transmission of the process data from the first processor to the second processor.

Abstract: Systems, devices, and techniques relating to remote debugging are described. A described device includes a first processor core configured to provide an application execution environment, memory coupled with the first processor core; a second processor core configured to provide a secure execution environment; and a communication interface coupled with the first processor core and the second processor core, the communication interface being configured to communicate with external devices, the communication interface being shared at least between the application execution environment and the secure execution environment.

Abstract: A system and method for determining operational robustness of a system on a chip (SoC) includes modifying one or more internal states of the SoC, during operation of the SoC, to mimic an effect which one or more disturbances have on the SoC, generating one or more signal traces that correspond to at least one internal state of the SoC after modifying the one or more internal states of the SoC, and determining if the operation of the SoC is stable based on the one or more generated signal traces.

Abstract: Some embodiments of the invention relate to a single processor configured to comprise configurable hardware extensions, disposed within a data path configured to selectively provide either encoded data or original data, that allow for two modes of operation. In a high performance mode, the hardware extensions allow for increased processing bandwidth by using the hardware extensions for processing extended data (i.e., additional original data). In a safety integrity mode the hardware extensions allow for parallel processing of encoded data concurrent with the processor executing a SBST by processing a self-test program and self-test data. Therefore, the single channel processor provides a single core system that can selectively achieve either high safety integrity levels (e.g., SIL3) for safety relevant applications or high performance for non-safety relevant applications.

Abstract: A computer system comprises a memory configured to store software instructions; a set of registers; and a processing unit configured to temporarily store passed parameters in the set of registers during execution of the software instructions, the processing unit further configured to skip save and restore operations when executing a logging function to log the passed parameters.