Nanotechnology Related Integrated Circuit Design Patents (Class 716/30)
  • Patent number: 9579796
    Abstract: The disclosure provides an approach for automatically determining task-specific robot model reductions. In one embodiment, a simplification application determines a smallest order statespace model whose stabilizing controller also stabilizes a full-order robot model. The simplification application may determine such a model via an iterative procedure in which the reduced order is initialized to the number of unstable poles of the open-loop full-order system and, while the closed loop full-order system with the balanced reduced order system's stabilizing controller is unstable, fractional balanced reduction is applied to generate a balanced reduced system. If one or more unstable closed-loop poles exist in the full-order system with the stabilizing controller of the newly-generated balanced reduced system, the reduced order is incremented by one, and fractional balanced reduction repeated, until no unstable closed-loop poles remain.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: February 28, 2017
    Assignee: Disney Enterprises, Inc.
    Inventors: Umashankar Nagarajan, Katsu Yamane
  • Patent number: 9324718
    Abstract: A three dimensional multilayer circuit (600) includes a plurality of crossbar arrays (512) made up of intersecting crossbar segments (410, 420) and programmable crosspoint devices (514) interposed between the intersecting crossbar segments (410, 420). Shift pins (505, 510) are used to shift connection domains (430) of the intersecting crossbar segments (410, 420) between stacked crossbar arrays (512) such that the programmable crosspoint devices (514) are uniquely addressed. The shift pins (505, 510) make electrical connections between crossbar arrays (512) by passing vertically between crossbar segments (410, 510) in the first crossbar array (512) and crossbar segments in a second crossbar array. A method for transforming multilayer circuits is also described.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: April 26, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Wei Wu, R. Stanley Williams
  • Patent number: 9286420
    Abstract: Various processes or modules described herein enable the schematic design tools to obtain physical data of a physical design and to perform one or more simulations in the schematic domain with such physical data such that the schematic design tools are made electrically aware of the physical data. Various types of data in the physical domain may be transferred to the schematic domain for the performance of one or more schematic simulations with the transferred data. The schematic designs are thus made electrically aware of such data from the physical domain and may incorporate any layout induced effects early in the schematic design stage or even at the time a schematic instance of a physical module is to be created in the schematic domain.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: March 15, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Prakash Krishnan, Jeremiah Cessna, Akshat Shah, Keith Dennison
  • Patent number: 9141741
    Abstract: Some aspects are directed at methods and systems that directly specifies or uses standardized power data in standardized format(s) in various design tasks for implementing mixed-signal electronic designs by using native process(es) or module(s) of standardized power format framework(s) to evaluate legal signals or expressions to generate the first output and evaluation process(es) or module(s) to evaluate illegal signals or expressions to generate the second output for the design tasks, without using wrappers to encapsulate circuit blocks generating illegal signals and hence disrupt the original design hierarchical structures or using translators to translate illegal signals or expressions into corresponding legal signals or expressions for the standardized power format frameworks.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: September 22, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Qingyu Lin, Nan Zhang, Zhong Fan
  • Patent number: 9027158
    Abstract: A download method of media contents, and which includes receiving and storing, by an electronic book terminal, a DRM (Digital Right Management) code from a contents server, the DRM code being stored in a memory of the electronic book terminal; receiving a media contents list from the contents server by requesting the media contents list at the contents server; decoding the received media contents list with the DRM code stored in the memory; displaying the media contents list on a screen of the electronic book terminal; requesting at least one media contents at the contents server, the at least one media contents being selected in the media contents list in response to a user input; receiving the at least one media contents from the contents server; and decoding the received at least one media contents with the DRM code stored in the memory.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: May 5, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventors: Hyoungki Nam, Hongil Kwon
  • Patent number: 8683393
    Abstract: Systems for integrated electronic and photonic design include a graphical user interface (GUI) configured to lay out electronic and photonic design components in a design environment; a design rule checking (DRC) module configured to check design rules for electronic and photonic components according to manufacturing requirements; and a processor configured to adjust photonic components according to photonic design requirements and to reconcile conflicts between electronic and photonic components.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Emrah Acar, Michael P. Beakes, William M. Green, Jonathan E. Proesel, Alexander V. Rylyakov, Yurii A. Vlasov
  • Publication number: 20140063587
    Abstract: A method of designing a nanophotonic scattering structure can include establishing an initial design having an array of discrete pixels variable between at least two pixel height levels. A performance metric for the structure can be a function of the heights of the pixels. The height of a pixel can be varied, and then the performance metric can be calculated. The steps of varying the pixel height and calculating the performance metric can be repeated to increase the performance metric. The above steps can be repeated for each pixel within the array and then the method can be iterated until the performance metric reaches an optimized value. Nanophotonic scattering structures can be produced from designs obtained through this process.
    Type: Application
    Filed: September 5, 2013
    Publication date: March 6, 2014
    Inventors: Rajesh Menon, Peng Wang
  • Patent number: 8631367
    Abstract: Systems and methods are provided for improving fidelity of a quantum operation on a quantum bit of interest. A controlled quantum gate operation, controlled by the quantum bit of interest, id performed on an ancillary quantum bit. An energy state of the ancillary quantum bit is measured to facilitate the improvement of the fidelity of the quantum operation.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: January 14, 2014
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Aaron A. Pesetski, James E. Baumgardner
  • Patent number: 8627240
    Abstract: Methods for integrated electronic and photonic design include laying out electronic and photonic design components in a design environment; adjusting photonic components according to photonic design requirements using a processor; checking design rules for electronic and photonic components according to manufacturing requirements; and adjusting component positioning and size to reconcile conflicts between electronic and photonic components.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Emrah Acar, Michael P. Beakes, William M. Green, Jonathan E. Proesel, Alexander V. Rylyakov, Yurii A. Vlasov
  • Patent number: 8612490
    Abstract: An exemplary embodiment may provide a repository for containing representations that represent a model or a portion of the model. A user may store the representations in the repository, for example, as functions. The functions stored in the repository may be shared and used for processing another model that includes a pattern performing the same or similar function as the representations stored in the repository. A checksum may be compared to determine an equivalent function in the repository. In a different embodiment, the intermediate representation of the pattern may be compared to determine an equivalent function in the repository.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: December 17, 2013
    Assignee: The MathWorks, Inc.
    Inventors: Michael David Tocci, John Edward Ciolfi, Pieter J. Mosterman
  • Patent number: 8560977
    Abstract: According to one embodiment, a plurality of test drop recipes are first created based on design data on a semiconductor integrated circuit. Based on a defect inspection result of a pattern of a hardening resin material, which is formed by pressing a template on which patterns of the semiconductor integrated circuit are formed onto the hardening resin material applied to a substrate to be processed by use of the test drop recipes, a drop recipe with least defects is selected per press position on the substrate to be processed from the test drop recipes. The selected drop recipes for respective press positions are collected per functional circuit block configuring the semiconductor integrated circuit, thereby to generate a drop recipe creation assistant database.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: October 15, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Matsuoka, Takumi Ota, Ryoichi Inanami
  • Patent number: 8548223
    Abstract: Optical image data of a mask is acquired. Reference image data associated with the optical images is created from design pattern data. Regional image data that includes pixel values denoted by multi-valued resolution based on importance level information of the patterns is created from region data including at least one portion of the patterns defined in the design pattern data. Defect determination is conducted on a pixel-by-pixel basis by comparing the optical image data with the reference image data, by means of either a plurality of threshold values determined by each pixel value within the regional image data or a plurality of defect determination methods. Image data of a section whose Mask Error Enhancement Factor (MEEF) is equal to or greater than a predetermined value is created from the region data including at least one portion of the patterns defined in the design pattern data.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: October 1, 2013
    Assignee: NuFlare Technology, Inc.
    Inventors: Takafumi Inoue, Hideo Tsuchiya
  • Patent number: 8504948
    Abstract: In general, the invention relates to a method for designing a biological circuit. The method includes obtaining a target circuit objective for the biological circuit, determining an objective function corresponding to the target circuit objective, obtaining a number of nodes for the biological circuit, obtaining a set of possible circuit subgraphs using the number of nodes, obtaining a specific dissipation energy (SDE) for each one of the set of possible circuit subgraphs by optimizing the objective function, selecting at least one circuit subgraph from the set of possible circuit subgraphs with the lowest SDE, and designing the biological circuit using the at least one selected one circuit subgraph.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: August 6, 2013
    Assignees: William Marsh Rice University, The General Hospital Corporation
    Inventors: Deepak Nagrath, Marco Avila-Elchiver, Martin Yarmush
  • Publication number: 20130146429
    Abstract: A nano-electromechanical switch and a method for designing a nano-electromechanical switch. The nano-electromechanical switch includes at least one actuator electrode and a curved cantilever beam. The curved cantilever beam is adapted to flex in response to an activation voltage applied between the actuator electrode and the curved cantilever beam to provide an electrical contact between the curved cantilever beam and an output electrode of the nano-electromechanical switch. Before, during and after the curved cantilever beam flex in response to the activation voltage, a remaining gap between the curved cantilever beam and the actuator electrode is uniform.
    Type: Application
    Filed: December 6, 2012
    Publication date: June 13, 2013
    Applicant: International Business Machines Corporation
    Inventor: International Business Machines Corporation
  • Patent number: 8345955
    Abstract: A method for characterizing thermomechanical properties of an organic substrate is provided.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: January 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Hien Phu Dang, Arun Sharma, Sri M. Sri-Jayantha
  • Publication number: 20120180004
    Abstract: The underlying dynamics (?t?=iH?) of quantum electrodynamics are symmetric with respect to time (T and CPT), but traditional calculations and design in electronics and electromagnetics impose an observer formalism or causality constraints which assume a gross asymmetry between forwards time and backwards time. My paper in the International Journal of Theoretical Physics (see http://arxiv.org/abs/0801.1234) describes how to construct physics based on the dynamics alone, without these extraneous assumptions. It showed that this changes certain predictions of physics, and that evidence from experiment favors the new and simpler theory. This disclosure follows up on that paper, by describing methods for circuit design based on the new physics.
    Type: Application
    Filed: May 8, 2011
    Publication date: July 12, 2012
    Inventor: Paul John Werbos
  • Publication number: 20120117518
    Abstract: In general, the invention relates to a method for designing a biological circuit. The method includes obtaining a target circuit objective for the biological circuit, determining an objective function corresponding to the target circuit objective, obtaining a number of nodes for the biological circuit, obtaining a set of possible circuit subgraphs using the number of nodes, obtaining a specific dissipation energy (SDE) for each one of the set of possible circuit subgraphs by optimizing the objective function, selecting at least one circuit subgraph from the set of possible circuit subgraphs with the lowest SDE, and designing the biological circuit using the at least one selected one circuit subgraph.
    Type: Application
    Filed: September 30, 2011
    Publication date: May 10, 2012
    Applicant: WILLIAM MARSH RICE UNIVERSITY
    Inventors: Deepak Nagrath, Marco Avila-Elchiver, Martin Yarmush
  • Patent number: 8156147
    Abstract: An exemplary embodiment may provide a repository for containing representations that represent a model or a portion of the model. A user may store the representations in the repository, for example, as functions. The functions stored in the repository may be shared and used for processing another model that includes a pattern performing the same or similar function as the representations stored in the repository. A checksum may be compared to determine an equivalent function in the repository. In a different embodiment, the intermediate representation of the pattern may be compared to determine an equivalent function in the repository.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: April 10, 2012
    Assignee: The MathWorks, Inc.
    Inventors: Michael David Tocci, John Ciolfi, Pieter J. Mosterman
  • Patent number: 8112700
    Abstract: One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines to 2k or fewer nanowires, employing supplemental, internal address lines to map 2k nanowire addresses to a larger, internal, n-bit address space, where n>k. A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2k nanowires, with n>k, using 2k, well-distributed, n-bit external addresses to access the 2k nanowires.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: February 7, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Philip J. Kuekes, J. Warren Robinett, Gadiel Seroussl, R. Stanley Williams
  • Patent number: 8112726
    Abstract: The present invention discloses a method of designing a set of two tiled masks, as well as, a mask including: a first tile, the first tile being transparent to a light, the first tile having a first characteristic linear dimension that is 15% or less of a wavelength of the light; a second tile, the second tile being transparent to the light, the second tile having a second characteristic linear dimension that is 15% or less of the wavelength of the light; and a third tile, the third tile being opaque to the light, the third tile having a third characteristic linear dimension that is 15% or less of the wavelength of the light.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: February 7, 2012
    Assignee: Intel Corporation
    Inventors: Bin Hu, Vivek Singh, Yan Borodovsky
  • Patent number: 8108924
    Abstract: Techniques are disclosed for providing connection data related to a firewall. In one aspect, computer-readable media provide a method that includes receiving a request for a set of connection parameters of a firewall related to data packets processed by at least one non-CPU device of the firewall. The method further includes identifying raw data of a session table that corresponds to the requested connection parameters. The method additionally includes calculating a result for the requested connection parameters from the raw data, and providing the result in a format detailing a number of connections for each connection parameter.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: January 31, 2012
    Assignee: Sprint Communications Company L.P.
    Inventor: Timothy L. Eberhard
  • Patent number: 8065634
    Abstract: A method for validating a nanotube logic network. The nanotube logic network is separated into regions based on a conductivity of the respective region. Potential paths through adjoining regions of the nanotube logic network are determined. Boolean path functions for each potential path are determined. If the Boolean path functions of the potential paths are equivalent to the intended logic function, then the nanotube logic network is immune to misaligned carbon nanotubes.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: November 22, 2011
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Nishant Patil, Subhasish Mitra
  • Patent number: 8056027
    Abstract: A method for characterizing thermomechanical properties of an organic substrate includes the steps of: receiving an image of the substrate, the image including a geometric description of the circuit layers of the substrate; selecting a given one of the circuit layers for processing; converting the image to a 2-D FEM image of the given circuit layer; repeating the steps of selecting a given one of the circuit layers and converting the image to a 2-D FEM image of the selected layer until all of the layers have been processed; combining all of the 2-D FEM images corresponding to the layers to form a 3-D FEM image representing at least a portion of the substrate; determining a coefficient of thermal expansion (CTE), modulus and/or Poisson's ratio of the 3-D FEM image; and constructing a 3-D representation of the substrate as a function of the CTE, modulus and/or Poisson's ratio of the 3-D FEM image.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Hien Phu Dang, Vijaveshwar Das Khanna, Arun Sharma, Sri M. Sri-Jayantha
  • Patent number: 8001491
    Abstract: A method of fabricating an organic thin film transistor is provided. The method includes forming a source, a drain and a gate on a substrate and forming a dielectric layer to isolate the gate from the source and isolate the gate from the drain. An organic active material layer is formed on the substrate to fill a channel region between the source and the drain and cover the source and the drain. A barrier material layer is formed on the organic active material layer. Thereafter, the barrier material layer and the organic active material layer are patterned to form a barrier layer and an organic active layer and expose the source and the drain.
    Type: Grant
    Filed: December 25, 2008
    Date of Patent: August 16, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Chi-Jen Kao, Yu-Rung Peng, Tsung-Hua Yang, Yi-Kai Wang, Tarng-Shiang Hu
  • Publication number: 20110138341
    Abstract: A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity corresponds to the target band discontinuity.
    Type: Application
    Filed: December 4, 2010
    Publication date: June 9, 2011
    Inventors: Maxim S. Shatalov, Remigijus Gaska, Jinwei Yang, Michael Shur
  • Publication number: 20110133088
    Abstract: A light detection system which comprises an active region between a back contact layer and a front contact layer is disclosed. The active region comprises a quantum well structure having a quantum well between quantum barriers, wherein the quantum well comprises foreign atoms that induce an excited bound state at an energy level which is above an energy level characterizing the quantum barriers.
    Type: Application
    Filed: August 19, 2010
    Publication date: June 9, 2011
    Applicant: Technion Research & Development Foundation Ltd.
    Inventors: Asaf ALBO, Gad Bahir, Dan Fekete
  • Patent number: 7945868
    Abstract: The invention discloses a method for tuning nano-scale analog-circuit designs in order to reduce random-device mismatches and optimize said design, where nano-scale devices potentially have large-scale process variations. The method includes providing a tunable circuit topology, wherein each nano-scale device comprises a single component or comprises multiple parallel components. Each component is decomposed into multiple discrete sub-components, wherein each said sub-component either operates in parallel with other like components to effectively operate like one bigger component. The sub-components are subjected to a dynamic-programming process to adaptively select the sub-components to be kept operational, while configuring the nonselected sub-components to be nonoperational, based on the measurement of at least one operational parameter.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: May 17, 2011
    Assignee: Carnegie Mellon University
    Inventors: Lawrence T. Pileggi, Xin Li
  • Patent number: 7945867
    Abstract: A method for realizes electric connections in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: May 17, 2011
    Assignee: STMicroelectronics S.r.l.
    Inventors: Danilo Mascolo, Gianfranco Cerofolini
  • Patent number: 7921384
    Abstract: The invention describes apparatuses for nano-scale integrated circuits applied to nanorobotics. Using EDA techniques, the system develops fully functional nano ICs, including ASICs and microprocessors. Three dimensional nano ICs are disclosed for increased efficiency in nanorobotic apparatuses. Nano-scale FPGAs are disclosed. The nano-scale semiconductors have applications to nano-scale and micro-scale robots.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: April 5, 2011
    Inventor: Neal Solomon