Abstract: An imaging device includes a photoelectric converter, a charge holding section that is provided on a side of the photoelectric converter opposite to a light entrance side of the photoelectric converter and holds a signal charge generated by the photoelectric converter, and a light shielding section that has a first light shielding surface extending toward the charge holding section from between the charge holding section and the photoelectric converter.

Abstract: Metrology targets, production processes and optical systems are provided, which enable metrology of device-like targets. Supplementary structure(s) may be introduced in the target to interact optically with the bottom layer and/or with the top layer of the target and target cells configurations enable deriving measurements of device-characteristic features. For example, supplementary structure(s) may be designed to yield Moiré patterns with one or both layers, and metrology parameters may be derived from these patterns. Device production processes were adapted to enable production of corresponding targets, which may be measured by standard or by provided modified optical systems, configured to enable phase measurements of the Moiré patterns.

Abstract: Aspects of the subject disclosure may include, for example, applying a setting voltage across first and second electrodes, wherein a nanowire with a first electrical resistance is electrically connected between the first and second electrodes, wherein the applying of the setting voltage causes a migration of ions from the first and/or second electrodes to a surface of the nanowire, and wherein the migration of ions effectuates a reduction of electrical resistance of the nanowire from the first electrical resistance to a second electrical resistance that is lower than the first electrical resistance; and applying a reading voltage across the pair of electrodes, wherein the reading voltage is less than the setting voltage, and wherein the reading voltage is sufficiently small such that the applying of the reading voltage causes no more than an insignificant change of the electrical resistance of the nanowire from the second electrical resistance. Other embodiments are disclosed.

Abstract: A graphene semiconductor design method according to the present invention, designs a semiconductor of graphene material by adjusting w and an effective permittivity ?_eff of a plasmon medium by use of a resonator, and integrates graphene semiconductor by adjusting a feed direction of a plasmon medium to generate a meta substance and a surface plasmon resonance phenomenon.

Abstract: A method of developing a physical design layout of microfluidic system chip can include receiving a planarized graph of a netlist including vertices representing microfluidic components. The vertices can be expanded into components, where each component includes a first dimension and a second dimension. The components can be shifted to a position where the first and second dimension of each component do not overlap with the first dimension and the second dimension of any other component. A flow route can be determined based on the first and second dimension of each component and the position of each component, the flow route including channels connecting two or more of the components.

Abstract: The disclosure provides an approach for automatically determining task-specific robot model reductions. In one embodiment, a simplification application determines a smallest order statespace model whose stabilizing controller also stabilizes a full-order robot model. The simplification application may determine such a model via an iterative procedure in which the reduced order is initialized to the number of unstable poles of the open-loop full-order system and, while the closed loop full-order system with the balanced reduced order system's stabilizing controller is unstable, fractional balanced reduction is applied to generate a balanced reduced system. If one or more unstable closed-loop poles exist in the full-order system with the stabilizing controller of the newly-generated balanced reduced system, the reduced order is incremented by one, and fractional balanced reduction repeated, until no unstable closed-loop poles remain.

Abstract: A three dimensional multilayer circuit (600) includes a plurality of crossbar arrays (512) made up of intersecting crossbar segments (410, 420) and programmable crosspoint devices (514) interposed between the intersecting crossbar segments (410, 420). Shift pins (505, 510) are used to shift connection domains (430) of the intersecting crossbar segments (410, 420) between stacked crossbar arrays (512) such that the programmable crosspoint devices (514) are uniquely addressed. The shift pins (505, 510) make electrical connections between crossbar arrays (512) by passing vertically between crossbar segments (410, 510) in the first crossbar array (512) and crossbar segments in a second crossbar array. A method for transforming multilayer circuits is also described.

Abstract: Various processes or modules described herein enable the schematic design tools to obtain physical data of a physical design and to perform one or more simulations in the schematic domain with such physical data such that the schematic design tools are made electrically aware of the physical data. Various types of data in the physical domain may be transferred to the schematic domain for the performance of one or more schematic simulations with the transferred data. The schematic designs are thus made electrically aware of such data from the physical domain and may incorporate any layout induced effects early in the schematic design stage or even at the time a schematic instance of a physical module is to be created in the schematic domain.

Abstract: Some aspects are directed at methods and systems that directly specifies or uses standardized power data in standardized format(s) in various design tasks for implementing mixed-signal electronic designs by using native process(es) or module(s) of standardized power format framework(s) to evaluate legal signals or expressions to generate the first output and evaluation process(es) or module(s) to evaluate illegal signals or expressions to generate the second output for the design tasks, without using wrappers to encapsulate circuit blocks generating illegal signals and hence disrupt the original design hierarchical structures or using translators to translate illegal signals or expressions into corresponding legal signals or expressions for the standardized power format frameworks.

Abstract: A download method of media contents, and which includes receiving and storing, by an electronic book terminal, a DRM (Digital Right Management) code from a contents server, the DRM code being stored in a memory of the electronic book terminal; receiving a media contents list from the contents server by requesting the media contents list at the contents server; decoding the received media contents list with the DRM code stored in the memory; displaying the media contents list on a screen of the electronic book terminal; requesting at least one media contents at the contents server, the at least one media contents being selected in the media contents list in response to a user input; receiving the at least one media contents from the contents server; and decoding the received at least one media contents with the DRM code stored in the memory.

Abstract: Systems for integrated electronic and photonic design include a graphical user interface (GUI) configured to lay out electronic and photonic design components in a design environment; a design rule checking (DRC) module configured to check design rules for electronic and photonic components according to manufacturing requirements; and a processor configured to adjust photonic components according to photonic design requirements and to reconcile conflicts between electronic and photonic components.

Abstract: A method of designing a nanophotonic scattering structure can include establishing an initial design having an array of discrete pixels variable between at least two pixel height levels. A performance metric for the structure can be a function of the heights of the pixels. The height of a pixel can be varied, and then the performance metric can be calculated. The steps of varying the pixel height and calculating the performance metric can be repeated to increase the performance metric. The above steps can be repeated for each pixel within the array and then the method can be iterated until the performance metric reaches an optimized value. Nanophotonic scattering structures can be produced from designs obtained through this process.

Abstract: Systems and methods are provided for improving fidelity of a quantum operation on a quantum bit of interest. A controlled quantum gate operation, controlled by the quantum bit of interest, id performed on an ancillary quantum bit. An energy state of the ancillary quantum bit is measured to facilitate the improvement of the fidelity of the quantum operation.

Abstract: Methods for integrated electronic and photonic design include laying out electronic and photonic design components in a design environment; adjusting photonic components according to photonic design requirements using a processor; checking design rules for electronic and photonic components according to manufacturing requirements; and adjusting component positioning and size to reconcile conflicts between electronic and photonic components.

Abstract: An exemplary embodiment may provide a repository for containing representations that represent a model or a portion of the model. A user may store the representations in the repository, for example, as functions. The functions stored in the repository may be shared and used for processing another model that includes a pattern performing the same or similar function as the representations stored in the repository. A checksum may be compared to determine an equivalent function in the repository. In a different embodiment, the intermediate representation of the pattern may be compared to determine an equivalent function in the repository.

Abstract: According to one embodiment, a plurality of test drop recipes are first created based on design data on a semiconductor integrated circuit. Based on a defect inspection result of a pattern of a hardening resin material, which is formed by pressing a template on which patterns of the semiconductor integrated circuit are formed onto the hardening resin material applied to a substrate to be processed by use of the test drop recipes, a drop recipe with least defects is selected per press position on the substrate to be processed from the test drop recipes. The selected drop recipes for respective press positions are collected per functional circuit block configuring the semiconductor integrated circuit, thereby to generate a drop recipe creation assistant database.

Abstract: Optical image data of a mask is acquired. Reference image data associated with the optical images is created from design pattern data. Regional image data that includes pixel values denoted by multi-valued resolution based on importance level information of the patterns is created from region data including at least one portion of the patterns defined in the design pattern data. Defect determination is conducted on a pixel-by-pixel basis by comparing the optical image data with the reference image data, by means of either a plurality of threshold values determined by each pixel value within the regional image data or a plurality of defect determination methods. Image data of a section whose Mask Error Enhancement Factor (MEEF) is equal to or greater than a predetermined value is created from the region data including at least one portion of the patterns defined in the design pattern data.

Abstract: In general, the invention relates to a method for designing a biological circuit. The method includes obtaining a target circuit objective for the biological circuit, determining an objective function corresponding to the target circuit objective, obtaining a number of nodes for the biological circuit, obtaining a set of possible circuit subgraphs using the number of nodes, obtaining a specific dissipation energy (SDE) for each one of the set of possible circuit subgraphs by optimizing the objective function, selecting at least one circuit subgraph from the set of possible circuit subgraphs with the lowest SDE, and designing the biological circuit using the at least one selected one circuit subgraph.

Abstract: A nano-electromechanical switch and a method for designing a nano-electromechanical switch. The nano-electromechanical switch includes at least one actuator electrode and a curved cantilever beam. The curved cantilever beam is adapted to flex in response to an activation voltage applied between the actuator electrode and the curved cantilever beam to provide an electrical contact between the curved cantilever beam and an output electrode of the nano-electromechanical switch. Before, during and after the curved cantilever beam flex in response to the activation voltage, a remaining gap between the curved cantilever beam and the actuator electrode is uniform.

Abstract: A method for characterizing thermomechanical properties of an organic substrate is provided.

Abstract: The underlying dynamics (?t?=iH?) of quantum electrodynamics are symmetric with respect to time (T and CPT), but traditional calculations and design in electronics and electromagnetics impose an observer formalism or causality constraints which assume a gross asymmetry between forwards time and backwards time. My paper in the International Journal of Theoretical Physics (see http://arxiv.org/abs/0801.1234) describes how to construct physics based on the dynamics alone, without these extraneous assumptions. It showed that this changes certain predictions of physics, and that evidence from experiment favors the new and simpler theory. This disclosure follows up on that paper, by describing methods for circuit design based on the new physics.

Abstract: In general, the invention relates to a method for designing a biological circuit. The method includes obtaining a target circuit objective for the biological circuit, determining an objective function corresponding to the target circuit objective, obtaining a number of nodes for the biological circuit, obtaining a set of possible circuit subgraphs using the number of nodes, obtaining a specific dissipation energy (SDE) for each one of the set of possible circuit subgraphs by optimizing the objective function, selecting at least one circuit subgraph from the set of possible circuit subgraphs with the lowest SDE, and designing the biological circuit using the at least one selected one circuit subgraph.

Abstract: An exemplary embodiment may provide a repository for containing representations that represent a model or a portion of the model. A user may store the representations in the repository, for example, as functions. The functions stored in the repository may be shared and used for processing another model that includes a pattern performing the same or similar function as the representations stored in the repository. A checksum may be compared to determine an equivalent function in the repository. In a different embodiment, the intermediate representation of the pattern may be compared to determine an equivalent function in the repository.

Abstract: The present invention discloses a method of designing a set of two tiled masks, as well as, a mask including: a first tile, the first tile being transparent to a light, the first tile having a first characteristic linear dimension that is 15% or less of a wavelength of the light; a second tile, the second tile being transparent to the light, the second tile having a second characteristic linear dimension that is 15% or less of the wavelength of the light; and a third tile, the third tile being opaque to the light, the third tile having a third characteristic linear dimension that is 15% or less of the wavelength of the light.

Abstract: One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines to 2k or fewer nanowires, employing supplemental, internal address lines to map 2k nanowire addresses to a larger, internal, n-bit address space, where n>k. A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2k nanowires, with n>k, using 2k, well-distributed, n-bit external addresses to access the 2k nanowires.

Abstract: Techniques are disclosed for providing connection data related to a firewall. In one aspect, computer-readable media provide a method that includes receiving a request for a set of connection parameters of a firewall related to data packets processed by at least one non-CPU device of the firewall. The method further includes identifying raw data of a session table that corresponds to the requested connection parameters. The method additionally includes calculating a result for the requested connection parameters from the raw data, and providing the result in a format detailing a number of connections for each connection parameter.

Abstract: A method for validating a nanotube logic network. The nanotube logic network is separated into regions based on a conductivity of the respective region. Potential paths through adjoining regions of the nanotube logic network are determined. Boolean path functions for each potential path are determined. If the Boolean path functions of the potential paths are equivalent to the intended logic function, then the nanotube logic network is immune to misaligned carbon nanotubes.

Abstract: A method for characterizing thermomechanical properties of an organic substrate includes the steps of: receiving an image of the substrate, the image including a geometric description of the circuit layers of the substrate; selecting a given one of the circuit layers for processing; converting the image to a 2-D FEM image of the given circuit layer; repeating the steps of selecting a given one of the circuit layers and converting the image to a 2-D FEM image of the selected layer until all of the layers have been processed; combining all of the 2-D FEM images corresponding to the layers to form a 3-D FEM image representing at least a portion of the substrate; determining a coefficient of thermal expansion (CTE), modulus and/or Poisson's ratio of the 3-D FEM image; and constructing a 3-D representation of the substrate as a function of the CTE, modulus and/or Poisson's ratio of the 3-D FEM image.

Abstract: A method of fabricating an organic thin film transistor is provided. The method includes forming a source, a drain and a gate on a substrate and forming a dielectric layer to isolate the gate from the source and isolate the gate from the drain. An organic active material layer is formed on the substrate to fill a channel region between the source and the drain and cover the source and the drain. A barrier material layer is formed on the organic active material layer. Thereafter, the barrier material layer and the organic active material layer are patterned to form a barrier layer and an organic active layer and expose the source and the drain.

Abstract: A light detection system which comprises an active region between a back contact layer and a front contact layer is disclosed. The active region comprises a quantum well structure having a quantum well between quantum barriers, wherein the quantum well comprises foreign atoms that induce an excited bound state at an energy level which is above an energy level characterizing the quantum barriers.

Abstract: A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity corresponds to the target band discontinuity.

Abstract: The invention discloses a method for tuning nano-scale analog-circuit designs in order to reduce random-device mismatches and optimize said design, where nano-scale devices potentially have large-scale process variations. The method includes providing a tunable circuit topology, wherein each nano-scale device comprises a single component or comprises multiple parallel components. Each component is decomposed into multiple discrete sub-components, wherein each said sub-component either operates in parallel with other like components to effectively operate like one bigger component. The sub-components are subjected to a dynamic-programming process to adaptively select the sub-components to be kept operational, while configuring the nonselected sub-components to be nonoperational, based on the measurement of at least one operational parameter.

Abstract: A method for realizes electric connections in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components.

Abstract: The invention describes apparatuses for nano-scale integrated circuits applied to nanorobotics. Using EDA techniques, the system develops fully functional nano ICs, including ASICs and microprocessors. Three dimensional nano ICs are disclosed for increased efficiency in nanorobotic apparatuses. Nano-scale FPGAs are disclosed. The nano-scale semiconductors have applications to nano-scale and micro-scale robots.