Abstract: The present invention is related to systems and methods for adaptive parameter modification in a data processing system.

Abstract: Various approaches, methods, systems, circuits and devices for channel bit density estimation.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: an analog to digital converter circuit, and a magneto-resistive adjustment circuit. The analog to digital converter circuit is operable to convert an input signal into corresponding digital samples. The magneto-resistive adjustment circuit is operable to reduce signal asymmetry in the digital samples due to sensing by a magneto-resistive head to yield a corrected output.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for adaptively modifying a scaling factor in a data processing system.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: an equalizer circuit, a signal to noise ratio calculation circuit, and a parameter adjustment circuit. The equalizer circuit is operable to equalize a data input to yield an equalized output. The signal to noise ratio calculation circuit is operable to calculate a signal to noise ratio of the equalized output based at least in part on a noise power derived from the equalized output. The parameter adjustment circuit is operable to adjust a parameter based at least in part on the signal to noise ratio.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a combination data decoder circuit. The combination data decoder circuit includes: a non-binary data decoder circuit and a binary data decoder circuit.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit and a bias calculation circuit. The data detector circuit is operable to apply a data detection algorithm to a first data set to yield a first series of soft decision data, and to apply the data detection algorithm to a second data set to yield a second series of soft decision data. The bias calculation circuit operable to calculate a series of bias values based at least in part on the first series of soft decision data and the second series of soft decision data. The series of bias values correspond to a conversion between the first series of soft decision data and the second series of soft decision data.

Abstract: A magnetic media tester comprising a Laser Doppler Vibrometer (LDV) head; and a magnetic read head; the LDV head and the magnetic read head being configured for obtaining correlatable data of a region on a magnetic disk.

Abstract: Disclosed is a magnetic recording/reproduction device 2 including: a recording/reproduction head 7; and a recording/reproduction head 7 for detecting a leakage magnetic field of each of the plurality of magnetic recording cells 1 so as to reproduce information, the recording/reproduction head 7 carrying out the recording on the magnetic recording medium 4 so that the magnetic recording medium 4 includes continuous recording regions that (i) satisfy Nmin?2 and that (ii) include a continuous recording region that satisfies N?n×Nmin, where N represents a number of magnetic recording cells 1 in a continuous recording region; Nmin represents a minimum value for N; and n represents a positive integer, the continuous recording regions each being a region on a reproduction track in which region magnetic recording cells 1 sharing an identical magnetization direction are sequentially arranged in a circumferential direction of the magnetic recording medium 4.

Abstract: Signal correction is performed by determining an offset error based at least in part on a first portion of a signal within a first amplitude range. The offset error is associated with error due to offset in the signal. An signal error, associated with error due to offset and magneto-resistive asymmetry (MRA) in the signal, is determined based at least in part on a second portion of the signal within a second amplitude range; the second amplitude range does not overlap with the first amplitude range. An MRA error is determined by removing the offset error from the signal error and the MRA error is removed from the signal.

Abstract: A method according to one embodiment includes generating a first gain error, comprising: receiving an output of an equalizer; and comparing a magnitude of the output to a saturation threshold level; if the output is higher than the saturation threshold level, generating a first gain error. The method further including generating at least one of a second and a third gain error, wherein generating the second gain error comprises: using either a slicer or a trellis for generating the second gain error, wherein the slicer generates a gain error based on an output of an interpolator, wherein the trellis generates a gain error based on an output of a maximum likelihood detector; wherein generating the third gain error comprises: receiving an output of an equalizer; generating a threshold qualified peak from the equalizer output and a tracking threshold level; comparing the threshold qualified peak to a second threshold; and generating a third gain error based on the comparison.

Abstract: According to one embodiment, a signal reproducing circuit reproduces a signal read from a recording medium on which the signal has been recorded by perpendicular magnetic recording. The signal reproducing circuit includes a waveform equalizer that equalizes the waveform of the signal based on a waveform equalization target, where D is a one-bit delay operator, previously stored in a storage module. The waveform equalization target is any one of a[1+3D+2D2] [1?D], a[2+5D+2D2] [1?D], and a[1+4D+2D2] [1?D] where a is an integer.

Abstract: Various embodiments of the present invention provide systems and methods for using data equalization. For example, various embodiments of the present invention provide storage devices that include a semiconductor device having an equalization unit and a digital-to-analog converter, a read/write head assembly located in close proximity to the semiconductor device, and a control unit located less proximate to the read/write head assembly than the semiconductor device.

Abstract: A magnetic recording device write channel includes a write equalization encoder for generating a write equalization level signal and a digital to analog converter for converting the write data signal to analog signals for recording. The write equalization level signal from the write equalization encoding device controls an impedance value at an output of said digital-to-analog converter. The output of the digital-to-analog converter is connected to an input of the data transmission line which transmits the write data signal to a write head of the magnetic recording device. Variation in the output impedance of the digital-to-analog converter by comparison to the input impedance of the transmission line controls the level of the equalization transmitted to the write head of the magnetic recording device.

Abstract: A read channel and method using that read channel are disclosed. The read channel comprises an analog to digital converter which asynchronously samples at a fixed rate an analog signal formed by reading a data track, where that data track was written to a data storage medium at a symbol rate and an interpolator interconnected with the analog to digital converter. The read channel further comprises a fractionally-spaced equalizer, where the interpolator provides an interpolated signal to the fractionally-spaced equalizer at an interpolation rate, where that interpolation rate is greater than the symbol rate. The fractionally-spaced equalizer forms a synchronous equalized signal. The read channel further comprises a gain control module interconnected with the fractionally-spaced equalizer, and a sequence detector interconnected with the gain control module.

Abstract: A signal processing circuit performs processing for an analog signal output from a head. The signal processing circuit includes: a conversion section that generates a digital signal based on the analog signal; a first filter that equalizes the output of the conversion section; a demodulation section that demodulates data from the output of the first filter; a modulation section that modulates a waveform based on the data demodulated by the demodulation section; a second filter that equalizes the output of the modulation section; and an adaptation section that adapts the response of the second filter such that the output of the second filter becomes equal to the output of the conversion section.

Abstract: Provided is a method for receiving a DSS sequence and a DSS readback sequence, which is a function of a channel processing of the DSS sequence by a read channel. A coefficient cyclic equalizer vector is generated as a function of the DSS sequence and the DSS readback sequence. An error signal is generated as a function of a comparison of the DSS sequence and an equalization of the DSS readback sequence based on the coefficient cyclic equalizer vector. An unacceptable error signal indicates a need to adjust the coefficient cyclic equalizer vector to yield an acceptable comparison of the DSS sequence and an equalization of the DSS readback sequence based on the coefficient cyclic equalizer vector.