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  • Low temperature process for fabricating layered superlattice materials and making electronic devices including same
    Patent number: 6133092
    Abstract: A liquid precursor containing thallium is applied to a first electrode, RTP baked at a temperature lower than 725.degree. C., and annealed at the same temperature for a time period from one to five hours to yield a ferroelectric layered superlattice material. A second electrode is formed to form a capacitor, and a second anneal is performed at a temperature lower than 725.degree. C. If the material is strontium bismuth thallium tantalate, the precursor contains (m-1) mole-equivalents of strontium for each of (2.2-x) mole-equivalents of bismuth, x mole-equivalents of thallium, and m mole-equivalents of tantalum, where m=2 and 0.0<x.ltoreq.2.2.
    Type: Grant
    Filed: July 24, 1998
    Date of Patent: October 17, 2000
    Assignees: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Shinichiro Hayashi, Carlos A. Paz de Araujo
  • Ferroelectric and high dielectric constant integrated circuit capacitors with three-dimensional orientation for high-density memories, and method of making the same
    Patent number: 7075134
    Abstract: A three-dimensional (“3-D”) memory capacitor comprises a bottom electrode, a ferroelectric thin film, and a top electrode that conform to a 3-D surface of an insulator layer. The capacitance area is greater than the horizontal footprint area of the capacitor. Preferably, the footprint of the capacitor is less than 0.2 nm2, and the corresponding capacitance area is typically in a range of from 0.4 nm2 to 1.0 nm2 The ferroelectric thin film preferably has a thickness not exceeding 60 nm. A capacitor laminate including the bottom electrode, ferroelectric thin film, and the top electrode preferably has a thickness not exceeding 200 nm. A low-thermal-budget MOCVD method for depositing a ferroelectric thin film having a thickness in a range of from 30 nm to 90 nm includes an RTP treatment before depositing the top electrode and an RTP treatment after depositing the top electrode and etching the ferroelectric layer.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: July 11, 2006
    Assignee: Symetrix Corporation
    Inventors: Carlos A. Paz de Araujo, Larry D. McMillan, Narayan Solayappan, Vikram Joshi
  • Ferroelectric and high dielectric constant integrated circuit capacitors with three-dimensional orientation for high-density memories, and method of making the same
    Patent number: 7459318
    Abstract: A three-dimensional (“3-D”) memory capacitor comprises a bottom electrode, a ferroelectric thin film, and a top electrode that conform to a 3-D surface of an insulator layer. The capacitance area is greater than the horizontal footprint area of the capacitor. Preferably, the footprint of the capacitor is less than 0.2 nm2, and the corresponding capacitance area is typically in a range of from 0.4 nm2 to 1.0 nm2 The ferroelectric thin film preferably has a thickness not exceeding 60 nm. A capacitor laminate including the bottom electrode, ferroelectric thin film, and the top electrode preferably has a thickness not exceeding 200 nm. A low-thermal-budget MOCVD method for depositing a ferroelectric thin film having a thickness in a range of from 30 nm to 90 nm includes an RTP treatment before depositing the top electrode and an RTP treatment after depositing the top electrode and etching the ferroelectric layer.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: December 2, 2008
    Assignee: Symetrix Corporation
    Inventors: Carlos A. Paz de Araujo, Larry D. McMillan, Narayan Solayappan, Vikram Joshi
  • Method and apparatus for misted liquid source deposition of thin film with reduced mist particle size
    Patent number: 6258733
    Abstract: A mass flow controller controls the delivery of a precursor to a mist generator. The precursor is misted utilizing a venturi in which a combination of oxygen and nitrogen gas is charged by a corona wire and passes over a precursor-filled throat. The mist is refined using a particle inertial separator, electrically filtered so that it comprises predominantly negative ions, passes into a velocity reduction chamber, and then flows into a deposition chamber through inlet ports in an inlet plate that is both a partition between the chambers and a grounded electrode. The inlet plate is located above and substantially parallel to the plane of the substrate on which the mist is to be deposited. The substrate is positively charged to a voltage of about 5000 volts. There are 440 inlet ports per square inch in an 39 square inch inlet port area of the inlet plate directly above the substrate. The inlet port area is approximately equal to the substrate area.
    Type: Grant
    Filed: July 21, 2000
    Date of Patent: July 10, 2001
    Assignee: Sand hill Capital II, LP
    Inventors: Narayan Solayappan, Robert W. Grant, Larry D. McMillan, Carlos A. Paz de Araujo
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