Abstract: Provided is an artificial neural network device including pre-synaptic neurons configured to generate a plurality of input spike signals, and a post-synaptic neuron configured to receive the plurality of input spike signals and to generate an output spike signal during a plurality of time periods, wherein the post-synaptic neuron respectively applies different weights in the plurality of time periods according to contiguousness with a reference time period in which input spike signals, which lead generation of the output spike signal from among the plurality of input spike signals, are received.
Type:
Application
Filed:
January 11, 2018
Publication date:
August 9, 2018
Inventors:
Ju-Yeob KIM, Byung Jo KIM, Jin Kyu KIM, Mi Young LEE, Seong Min KIM, Joo Hyun LEE
Abstract: This invention solves the long-standing problem in Machine Learning of training a neural network on a spike-based neuromorphic computer. The preferred embodiment of the invention describes an algorithm for training a Restricted Boltzmann Machine (RBM) neural network, but the invention applies equally to training neural networks in the general class of Markov Random Fields. The standard CD algorithm for training an RBM on a general-purpose computer is unsuitable for implementation on a neuromorphic computer, as it requires the communication of real-valued parameter values between neurons, and/or shared memory access by neurons to stored parameter values. By employing the invention described, these requirements are eliminated, thus providing a training algorithm which can be implemented efficiently on a spike-based, distributed processor and memory, neuromorphic computer system.
Abstract: An event-driven neural network includes a plurality of interconnected core circuits is provided. Each core circuit includes an electronic synapse array has multiple digital synapses interconnecting a plurality of digital electronic neurons. A synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron. A neuron integrates input spikes and generates a spike event in response to the integrated input spikes exceeding a threshold. Each core circuit also has a scheduler that receives a spike event and delivers the spike event to a selected axon in the synapse array based on a schedule for deterministic event delivery.
Type:
Application
Filed:
September 16, 2011
Publication date:
March 21, 2013
Applicants:
Cornell University, INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventors:
Filipp Akopyan, John V. Arthur, Rajit Manohar, Paul A. Merolla, Dharmendra S. Modha, Alyosha Molnar, William P. Risk, III
Abstract: Spiking events in a spiking neural network may be processed via a memory system. A memory system may store data corresponding to a group of destination neurons. The memory system may, at each time interval of a SNN, pass through data corresponding to a group of pre-synaptic spike events from respective source neurons. The data corresponding to the group of pre-synaptic spike events may be subsequently stored in the memory system.
Type:
Application
Filed:
April 22, 2024
Publication date:
August 15, 2024
Inventors:
Dmitri Yudanov, Sean S. Eilert, Hernan A. Castro, Ameen D. Akel
Abstract: The present disclosure relates to a neuron circuit of a spiking neural network comprising: a first resistive switching memory device having a conductance that decays over time; and a programming circuit configured to reset the resistive state of the first resistive switching element in response to a spike in an output voltage of the neuron circuit.
Abstract: Spiking events in a spiking neural network may be processed via a memory system. A memory system may store data corresponding to a group of destination neurons. The memory system may, at each time interval of a SNN, pass through data corresponding to a group of pre-synaptic spike events from respective source neurons. The data corresponding to the group of pre-synaptic spike events may be subsequently stored in the memory system.
Type:
Grant
Filed:
August 31, 2020
Date of Patent:
June 11, 2024
Assignee:
Micron Technology, Inc.
Inventors:
Dmitri Yudanov, Sean S. Eilert, Hernan A. Castro, Ameen D. Akel
Abstract: An event-driven neural network includes a plurality of interconnected core circuits is provided. Each core circuit includes an electronic synapse array has multiple digital synapses interconnecting a plurality of digital electronic neurons. A synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron. A neuron integrates input spikes and generates a spike event in response to the integrated input spikes exceeding a threshold. Each core circuit also has a scheduler that receives a spike event and delivers the spike event to a selected axon in the synapse array based on a schedule for deterministic event delivery.
Type:
Application
Filed:
January 6, 2016
Publication date:
August 4, 2016
Inventors:
Filipp Akopyan, John V. Arthur, Paul A. Merolla, Dharmendra S. Modha, William P. Risk
Abstract: Neural network apparatus and methods for implementing reinforcement learning. In one implementation, the neural network is a spiking neural network, and the apparatus and methods may be used for example to enable an adaptive signal processing system to effect focused exploration by associative adaptation, including providing a negative reward signal to the network, which may increase excitability of the neurons in combination with decrease in excitability of active neurons. In certain implementations, the increase is gradual and of smaller magnitude, compared to the excitability decrease. In some implementations, the increase/decrease of the neuron excitability is effectuated by increasing/decreasing an efficacy of the respective synaptic connections delivering presynaptic inputs into the neuron. The focused exploration may be achieved for instance by non-associative potentiation configured based at least on the input spike rate.
Abstract: Neural network apparatus and methods for implementing reinforcement learning. In one implementation, the neural network is a spiking neural network, and the apparatus and methods may be used for example to enable an adaptive signal processing system to effect focused exploration by associative adaptation, including providing a negative reward signal to the network, which may increase excitability of the neurons in combination with decrease in excitability of active neurons. In certain implementations, the increase is gradual and of smaller magnitude, compared to the excitability decrease. In some implementations, the increase/decrease of the neuron excitability is effectuated by increasing/decreasing an efficacy of the respective synaptic connections delivering presynaptic inputs into the neuron. The focused exploration may be achieved for instance by non-associative potentiation configured based at least on the input spike rate.
Abstract: Disclosed is a spiking neural network circuit, which includes an axon circuit that generates an input spike signal, a synapse circuit that outputs a current based on the input spike signal and a weight, a capacitor that forms a membrane voltage based on the current, and a neuron circuit that generates an output spike signal based on the membrane voltage, and the neuron circuit includes a first comparator that generates an intermediate spike signal based on the membrane voltage and a first reference voltage, and a second comparator that generates the output spike signal based on the intermediate spike signal, the membrane voltage, and a second reference voltage that is different from the first reference voltage.
Type:
Application
Filed:
January 8, 2024
Publication date:
November 14, 2024
Inventors:
Kwang IL OH, Tae Wook KANG, Hyuk KIM, Jae-Jin LEE
Abstract: Certain aspects of the present disclosure provide methods and apparatus for a continuous-time neural network event-based simulation that includes a multi-dimensional multi-schedule architecture with ordered and unordered schedules and accelerators to provide for faster event sorting; and a formulation of modeling event operations as anticipating (the future) and advancing (update/jump ahead/catch up) rules or methods to provide a continuous-time neural network model. In this manner, the advantages include faster simulation of spiking neural networks (order(s) of magnitude); and a method for describing and modeling continuous time neurons, synapses, and general neural network behaviors.
Abstract: In one embodiment, a processor comprises a first neuromorphic core to implement a plurality of neural units of a neural network, the first neuromorphic core comprising a memory to store a current time-step of the first neuromorphic core; and a controller to track current time-steps of neighboring neuromorphic cores that receive spikes from or provide spikes to the first neuromorphic core; and control the current time-step of the first neuromorphic core based on the current time-steps of the neighboring neuromorphic cores.
Type:
Application
Filed:
September 29, 2017
Publication date:
April 4, 2019
Inventors:
Gregory K. Chen, Kshitij Bhardwaj, Raghavan Kumar, Huseyin E. Sumbul, Phil Knag, Ram K. Krishnamurthy, Himanshu Kaul
Abstract: Provided is an electronic circuit for implementing a generative adversarial neural network. The electronic circuit includes a spike converter, a spike image generator, a spike image converter, and an image discriminator. The spike converter generates a first signal including spike signals. The number of the spike signals is determined based on first data associated with second data within a reference time interval. The spike image generator generates a second signal including spike signals being selected based on a weight among the spike signals of the first signal. The image converter converts the spike signals of the second signal to generate third data being represented in an analog domain. The image discriminator provides the spike image generator with result data being associated with a difference between a value of the third data and a value of the second data. The image generator determines the weight based on the result data.
Type:
Application
Filed:
June 19, 2019
Publication date:
December 26, 2019
Applicant:
Electronics and Telecommunications Research Institute
Inventors:
Seong Mo PARK, Jae-Jin LEE, Sung Eun KIM, Kyung Hwan PARK, Mi Jeong PARK, Young Hwan BAE, Kwang IL OH, Byounggun CHOI
Abstract: Certain aspects of the present disclosure provide methods and apparatus for a continuous-time neural network event-based simulation that includes a multi-dimensional multi-schedule architecture with ordered and unordered schedules and accelerators to provide for faster event sorting; and a formulation of modeling event operations as anticipating (the future) and advancing (update/jump ahead/catch up) rules or methods to provide a continuous-time neural network model. In this manner, the advantages include faster simulation of spiking neural networks (order(s) of magnitude); and a method for describing and modeling continuous time neurons, synapses, and general neural network behaviors.
Abstract: Various implementations are related to an apparatus with memory cells arranged in columns and rows, and the memory cells are accessible with a column control voltage for accessing the memory cells via the columns and a row control voltage for accessing the memory cells via the rows. The apparatus may include neural network circuitry having neuronal junctions that are configured to receive, record, and provide information related to incoming voltage spikes associated with input signals based on resistance through the neuronal junctions. The apparatus may include stochastic re-programmer circuitry that receives the incoming voltage spikes, receives the information provided by the neuronal junctions, and reconfigure the information recorded in the neuronal junctions based on the incoming voltage spikes associated with the input signals along with a programming control signal provided by the memory circuitry.
Type:
Grant
Filed:
May 20, 2020
Date of Patent:
November 15, 2022
Assignee:
Arm Limited
Inventors:
Mbou Eyole, Shidhartha Das, Fernando Garcia Redondo
Abstract: Various implementations are related to an apparatus with memory cells arranged in columns and rows, and the memory cells are accessible with a column control voltage for accessing the memory cells via the columns and a row control voltage for accessing the memory cells via the rows. The apparatus may include neural network circuitry having neuronal junctions that are configured to receive, record, and provide information related to incoming voltage spikes associated with input signals based on resistance through the neuronal junctions. The apparatus may include stochastic re-programmer circuitry that receives the incoming voltage spikes, receives the information provided by the neuronal junctions, and reconfigure the information recorded in the neuronal junctions based on the incoming voltage spikes associated with the input signals along with a programming control signal provided by the memory circuitry.
Abstract: A system is described that comprises a memory for storing data representative of at least one kernel, a plurality of spiking neuron circuits, and an input module for receiving spikes related to digital data. Each spike is relevant to a spiking neuron circuit and each spike has an associated spatial coordinate corresponding to a location in an input spike array. The system also comprises a transformation module configured to transform a kernel to produce a transformed kernel having an increased resolution relative to the kernel, and/or transform the input spike array to produce a transformed input spike array having an increased resolution relative to the input spike array.
Type:
Grant
Filed:
January 25, 2022
Date of Patent:
May 21, 2024
Assignee:
BrainChip, Inc.
Inventors:
Douglas McLelland, Kristofor D. Carlson, Harshil K. Patel, Anup A. Vanarse, Milind Joshi
Abstract: A target tracking method and a target tracking system of a spiking neural network based on an event camera are provided. The method includes: acquiring a data stream of asynchronous events in a high dynamic scene of a target by an event camera as input data; dividing the data stream of the asynchronous events into synchronous event frames with millisecond time resolution; training a twin network based on a spiking neural network by a gradient substitution algorithm with a target image as a template image and a complete image as a searched image; and tracking the target by a trained twin network with interpolating a result of feature mapping to up-sample and obtaining the position of the target in an original image. The twin network includes a feature extractor and a cross-correlation calculator.
Type:
Application
Filed:
August 31, 2023
Publication date:
December 21, 2023
Inventors:
Wenyi ZHAO, Huajin TANG, Chaofei HONG, Xiao WANG, Mengwen YUAN, Yujing LU, Mengxiao ZHANG, Gang PAN
Abstract: Conventional gesture detection approaches demand large memory and computation power to run efficiently, thus limiting their use in power and memory constrained edge devices. Present application/disclosure provides a Spiking Neural Network based system which is a robust low power edge compatible ultrasound-based gesture detection system. The system uses a plurality of speakers and microphones that mimics a Multi Input Multi Output (MIMO) setup thus providing requisite diversity to effectively address fading. The system also makes use of distinctive Channel Impulse Response (CIR) estimated by imposing sparsity prior for robust gesture detection. A multi-layer Convolutional Neural Network (CNN) has been trained on these distinctive CIR images and the trained CNN model is converted into an equivalent Spiking Neural Network (SNN) via an ANN (Artificial Neural Network)-to-SNN conversion mechanism. The SNN is further configured to detect/classify gestures performed by user(s).
Type:
Application
Filed:
December 14, 2022
Publication date:
October 12, 2023
Applicant:
Tata Consultancy Services Limited
Inventors:
ANDREW GIGIE, ARUN GEORGE, ACHANNA ANIL KUMAR, SOUNAK DEY, ARPAN PAL