Search Patents
  • ENHANCING DEPOSITION UNIFORMITY OF A CHANNEL SEMICONDUCTOR ALLOY BY FORMING A RECESS PRIOR TO THE WELL IMPLANTATION
    Publication number: 20110156172
    Abstract: When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Moreover, the well dopant species is implanted after the recessing, thereby avoiding undue dopant loss. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.
    Type: Application
    Filed: October 20, 2010
    Publication date: June 30, 2011
    Inventors: Stephan Kronholz, Maciej Wiatr, Roman Boschke, Peter Javorka
  • Method for differential spacer removal by wet chemical etch process and device with differential spacer structure
    Patent number: 8298924
    Abstract: By removing an outer spacer of a transistor element, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, employing a wet chemical etch process, it is possible to position a stressed contact liner layer more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region, without affecting circuit elements in the P-type regions.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: October 30, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Maciej Wiatr, Frank Wirbeleit, Andy Wei, Andreas Gehring
  • METHOD INCLUDING A REPLACEMENT OF A DUMMY GATE STRUCTURE WITH A GATE STRUCTURE INCLUDING A FERROELECTRIC MATERIAL
    Publication number: 20160071947
    Abstract: A method disclosed herein includes providing a substrate including a semiconductor material. A first area of the substrate is recessed relative to a second area of the substrate, and an active region of a first transistor is formed in the recessed area. An active region of a second transistor is formed in the second area of the substrate. First and second dummy gate structures are formed over the active regions of the first transistor and the second transistor, respectively. At least a portion of the first and second dummy gate structures is replaced with at least a portion of a gate structure of the first transistor and the second transistor, respectively. The gate structure of the first transistor includes a ferroelectric material, and the gate structure of the second transistor does not include a ferroelectric material.
    Type: Application
    Filed: September 10, 2014
    Publication date: March 10, 2016
    Inventors: Maciej Wiatr, Stefan Flachowsky
  • Differential threshold voltage adjustment in PMOS transistors by differential formation of a channel semiconductor material
    Patent number: 8536009
    Abstract: In sophisticated semiconductor devices, high-k metal gate electrode structures may be provided in an early manufacturing stage wherein the threshold voltage adjustment for P-channel transistors may be accomplished on the basis of a threshold voltage adjusting semiconductor alloy, such as a silicon/germanium alloy, for long channel devices, while short channel devices may be masked during the selective epitaxial growth of the silicon/germanium alloy. In some illustrative embodiments, the threshold voltage adjustment may be accomplished without any halo implantation processes for the P-channel transistors, while the threshold voltage may be tuned by halo implantations for the N-channel transistors.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: September 17, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Javorka, Maciej Wiatr, Stephan-Detlef Kronholz
  • Test Structure for Controlling the Incorporation of Semiconductor Alloys in Transistors Comprising High-K Metal Gate Electrode Structures
    Publication number: 20120001174
    Abstract: When forming critical threshold adjusting semiconductor alloys and/or strain-inducing embedded semiconductor materials in sophisticated semiconductor devices, at least the corresponding etch processes may be monitored efficiently on the basis of mechanically gathered profile measurement data by providing an appropriately designed test structure. Consequently, sophisticated process sequences performed on bulk semiconductor devices may be efficiently monitored and/or controlled by means of the mechanically obtained profile measurement data without significant delay. For example, superior uniformity upon providing a threshold adjusting semiconductor alloy in sophisticated high-k metal gate electrode structures for non-SOI devices may be achieved.
    Type: Application
    Filed: December 10, 2010
    Publication date: January 5, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stephan Kronholz, Maciej Wiatr, Rainer Giedigkeit
  • NOVEL E-FUSE DESIGN FOR HIGH-K METAL-GATE TECHNOLOGY
    Publication number: 20150179753
    Abstract: E-fuses are used in integrated circuits in order to permit real-time dynamic reprogramming of the circuit after manufacturing. An e-fuse is hereby proposed wherein the metal element adapted to be blown upon passage of a current is not comprised of a silicide layer but is rather a metal layer above which a semiconductor layer is formed. A dielectric layer is then formed on the semiconductor layer, in order to prevent metal silicide from forming over the metal layer. The process of manufacturing the e-fuse can be easily integrated in an HKMG manufacturing flow. In particular, fully silicided metal gates may be manufactured in conjunction with the e-fuse, without jeopardizing the correct functioning of the e-fuse.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 25, 2015
    Applicant: Globalfoundries Inc.
    Inventors: Roman Boschke, Stefan Flachowsky, Maciej Wiatr, Christian Schippel
  • Method for forming a transistor comprising high-k metal gate electrode structures including a polycrystalline semiconductor material and embedded strain-inducing semiconductor alloys
    Patent number: 8343826
    Abstract: When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage on the basis of a silicon/germanium semiconductor alloy for adjusting appropriate electronic conditions in the channel region, the efficiency of a strain-inducing embedded semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by initiating a crystal growth in the silicon material of the gate electrode structure after the gate patterning process. In this manner, the negative strain of the threshold voltage adjusting silicon/germanium alloy may be reduced or compensated for.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: January 1, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan-Detlef Kronholz, Peter Javorka, Maciej Wiatr
  • Buried etch stop layer in trench isolation structures for superior surface planarity in densely packed semiconductor devices
    Patent number: 8334573
    Abstract: Material erosion of trench isolation structures in advanced semiconductor devices may be reduced by incorporating an appropriate mask layer stack in an early manufacturing stage. For example, a silicon nitride material may be incorporated as a buried etch stop layer prior to a sequence for patterning active regions and forming a strain-inducing semiconductor alloy therein, wherein, in particular, the corresponding cleaning process prior to the selective epitaxial growth process has been identified as a major source for causing deposition-related irregularities upon depositing the interlayer dielectric material.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: December 18, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Maciej Wiatr, Markus Forsberg, Stephan Kronholz, Roman Boschke
  • Reduction of defect rates in PFET transistors comprising a Si/Ge semiconductor material formed by epitaxial growth
    Patent number: 8939765
    Abstract: In sophisticated semiconductor devices, the defect rate that may typically be associated with the provision of a silicon/germanium material in the active region of P-channel transistors may be significantly decreased by incorporating a carbon species prior to or during the selective epitaxial growth of the silicon/germanium material. In some embodiments, the carbon species may be incorporated during the selective growth process, while in other cases an ion implantation process may be used. In this case, superior strain conditions may also be obtained in N-channel transistors.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: January 27, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Peter Javorka, Maciej Wiatr, Roman Boschke, Christian Krueger
  • Differential Threshold Voltage Adjustment in PMOS Transistors by Differential Formation of a Channel Semiconductor Material
    Publication number: 20120153401
    Abstract: In sophisticated semiconductor devices, high-k metal gate electrode structures may be provided in an early manufacturing stage wherein the threshold voltage adjustment for P-channel transistors may be accomplished on the basis of a threshold voltage adjusting semiconductor alloy, such as a silicon/germanium alloy, for long channel devices, while short channel devices may be masked during the selective epitaxial growth of the silicon/germanium alloy. In some illustrative embodiments, the threshold voltage adjustment may be accomplished without any halo implantation processes for the P-channel transistors, while the threshold voltage may be tuned by halo implantations for the N-channel transistors.
    Type: Application
    Filed: August 3, 2011
    Publication date: June 21, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Peter JAVORKA, Maciej WIATR, Stephan-Detlef KRONHOLZ
  • TRANSISTOR COMPRISING AN EMBEDDED SEMICONDUCTOR ALLOY IN DRAIN AND SOURCE REGIONS EXTENDING UNDER THE GATE ELECTRODE
    Publication number: 20100219474
    Abstract: A strain-inducing semiconductor alloy may be formed on the basis of cavities that may extend deeply below the gate electrode structure, which may be accomplished by using a sequence of two etch processes. In a first etch process, the cavity may be formed on the basis of a well-defined lateral offset to ensure integrity of the gate electrode structure and, in a subsequent etch process, the cavity may be increased in a lateral direction while nevertheless reliably preserving a portion of the channel region. Consequently, the strain-inducing efficiency may be increased by appropriately positioning the strain-inducing material immediately below the channel region without compromising integrity of the gate electrode structure.
    Type: Application
    Filed: February 22, 2010
    Publication date: September 2, 2010
    Inventors: Stephan Kronholz, Maciej Wiatr, Matthias Kessler
  • Enhancing deposition uniformity of a channel semiconductor alloy by forming a recess prior to the well implantation
    Patent number: 8722486
    Abstract: When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Moreover, the well dopant species is implanted after the recessing, thereby avoiding undue dopant loss. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: May 13, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Maciej Wiatr, Roman Boschke, Peter Javorka
  • STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CORNER ROUNDING AT THE TOP OF THE GATE ELECTRODE
    Publication number: 20110101469
    Abstract: In MOS transistor elements, a strain-inducing semiconductor alloy may be embedded in the active region with a reduced offset from the channel region by applying a spacer structure of reduced width. In order to reduce the probability of creating semiconductor residues at the top area of the gate electrode structure, a certain degree of corner rounding of the semiconductor material may be introduced, which may be accomplished by ion implantation prior to epitaxially growing the strain-inducing semiconductor material. This concept may be advantageously combined with the provision of sophisticated high-k metal gate electrodes that are provided in an early manufacturing stage.
    Type: Application
    Filed: September 29, 2010
    Publication date: May 5, 2011
    Inventors: Stephan Kronholz, Roman Boschke, Maciej Wiatr, Peter Javorka
  • Transistor comprising an embedded semiconductor alloy in drain and source regions extending under the gate electrode
    Patent number: 8460980
    Abstract: A strain-inducing semiconductor alloy may be formed on the basis of cavities that may extend deeply below the gate electrode structure, which may be accomplished by using a sequence of two etch processes. In a first etch process, the cavity may be formed on the basis of a well-defined lateral offset to ensure integrity of the gate electrode structure and, in a subsequent etch process, the cavity may be increased in a lateral direction while nevertheless reliably preserving a portion of the channel region. Consequently, the strain-inducing efficiency may be increased by appropriately positioning the strain-inducing material immediately below the channel region without compromising integrity of the gate electrode structure.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: June 11, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Maciej Wiatr, Matthias Kessler
  • Test structure for controlling the incorporation of semiconductor alloys in transistors comprising high-k metal gate electrode structures
    Patent number: 8673668
    Abstract: When forming critical threshold adjusting semiconductor alloys and/or strain-inducing embedded semiconductor materials in sophisticated semiconductor devices, at least the corresponding etch processes may be monitored efficiently on the basis of mechanically gathered profile measurement data by providing an appropriately designed test structure. Consequently, sophisticated process sequences performed on bulk semiconductor devices may be efficiently monitored and/or controlled by means of the mechanically obtained profile measurement data without significant delay. For example, superior uniformity upon providing a threshold adjusting semiconductor alloy in sophisticated high-k metal gate electrode structures for non-SOI devices may be achieved.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: March 18, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Maciej Wiatr, Rainer Giedigkeit
  • E-fuse design for high-K metal-gate technology
    Patent number: 9515155
    Abstract: E-fuses are used in integrated circuits in order to permit real-time dynamic reprogramming of the circuit after manufacturing. An e-fuse is hereby proposed wherein the metal element adapted to be blown upon passage of a current is not comprised of a silicide layer but is rather a metal layer above which a semiconductor layer is formed. A dielectric layer is then formed on the semiconductor layer, in order to prevent metal silicide from forming over the metal layer. The process of manufacturing the e-fuse can be easily integrated in an HKMG manufacturing flow. In particular, fully silicided metal gates may be manufactured in conjunction with the e-fuse, without jeopardizing the correct functioning of the e-fuse.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: December 6, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Roman Boschke, Stefan Flachowsky, Maciej Wiatr, Christian Schippel
  • Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by corner rounding at the top of the gate electrode
    Patent number: 8338892
    Abstract: In MOS transistor elements, a strain-inducing semiconductor alloy may be embedded in the active region with a reduced offset from the channel region by applying a spacer structure of reduced width. In order to reduce the probability of creating semiconductor residues at the top area of the gate electrode structure, a certain degree of corner rounding of the semiconductor material may be introduced, which may be accomplished by ion implantation prior to epitaxially growing the strain-inducing semiconductor material. This concept may be advantageously combined with the provision of sophisticated high-k metal gate electrodes that are provided in an early manufacturing stage.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: December 25, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Roman Boschke, Maciej Wiatr, Peter Javorka
  • Method of Forming Transistor with Increased Gate Width
    Publication number: 20130178045
    Abstract: Methods of forming transistor devices having an increased gate width dimension are disclosed. In one example, the method includes forming an isolation structure in a semiconducting substrate, wherein the isolation structure defines an active region in the substrate, performing an ion implantation process on the isolation structure to create a damaged region in the isolation structure and, after performing the implantation process, performing an etching process to remove at least a portion of the damaged region to define a recess in the isolation structure, wherein a portion of the recess extends below an upper surface of the substrate and exposes a sidewall of the active region. The method further includes forming a gate insulation layer above the active region, wherein a portion of the insulation layer extends into the recess, and forming a gate electrode above the insulation layer, wherein a portion of the gate electrode extends into the recess.
    Type: Application
    Filed: January 11, 2012
    Publication date: July 11, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Chung Foong Tan, Maciej Wiatr, Peter Javorka, Falong Zhou
  • SEMICONDUCTOR STRUCTURE INCLUDING A TRANSISTOR HAVING STRESS CREATING REGIONS AND METHOD FOR THE FORMATION THEREOF
    Publication number: 20170330970
    Abstract: A method includes providing a semiconductor structure including a substrate, a gate structure over the substrate and a sidewall spacer adjacent the gate structure. The substrate includes a first semiconductor material. A substantially isotropic first etch process removing the first semiconductor material is performed. The first etch process forms an undercut below the sidewall spacer. An anisotropic second etch process removing the first semiconductor material is performed, wherein an etch rate in a thickness direction of the substrate is greater than an etch rate in a horizontal direction that is perpendicular to the thickness direction. A crystallographic third etch process removing the first semiconductor material is performed, wherein an etch rate in a first crystal direction is greater than an etch rate in a second crystal direction. The first, second and third etch processes form a source-side recess and a drain-side recess adjacent the gate structure.
    Type: Application
    Filed: May 13, 2016
    Publication date: November 16, 2017
    Inventors: Arkadiusz Malinowski, Chung Foong Tan, Nicolas Sassiat, Maciej Wiatr
  • Methods of Forming Faceted Stress-Inducing Stressors Proximate the Gate Structure of a Transistor
    Publication number: 20130175585
    Abstract: Disclosed herein are various methods of forming faceted stress-inducing stressors proximate the gate structure of a transistor. In one example, a method includes forming a first recess in an active region of a semiconducting substrate, forming a first semiconductor material in the first recess and forming a gate structure above the first semiconductor material. In this example, the method includes the additional steps of performing a crystalline orientation-dependent etching process on the first semiconductor material to define a plurality of second recesses proximate the gate structure, wherein each of the second recesses has a faceted edge, and forming a first region of stress-inducing semiconductor material in each of the second recesses, wherein each of the first regions of stress-inducing semiconductor material has a faceted edge that engages a corresponding faceted edge in one of the second recesses.
    Type: Application
    Filed: January 11, 2012
    Publication date: July 11, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Chung Foong Tan, Maciej Wiatr, Stephan Kronholz, Falong Zhou, Ying Hao Hsieh
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