Search Patents
  • Patent number: 7155757
    Abstract: Various embodiments of the invention relate to a seat mounted on wheels for rolling along wheel tracks of parallel longitudinal members of a frame having end members connecting the longitudinal members. The frame may be placed on an upper surface of a bath enclosure such as a bathtub or shower unit and turnbuckles in the longitudinal members may be used to friction fit the longitudinal members to vertical surfaces at the end of the bathtub or shower unit. Moreover, the seat may have a bottom portion hingedly attached to a seat back portion so that the seat can be stowed at one end of the bath enclosure by folding the bottom portion towards the back portion.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: January 2, 2007
    Inventor: Pedro Zamora, Jr.
  • Patent number: 7157950
    Abstract: Some microprocessors are designed such that the microprocessor core clock has a duty cycle of approximately fifty percent. When a clock signal propagates across power domains the clock signal pulse shape will change. The rising edges and falling edges of the clock signal will become asymmetrical (e.g., the duty cycle is no longer fifty percent). According to embodiments of the present invention, a parallel divide function is applied to a clock signal having a frequency f and its complement. The resulting four signals (i.e., f/2, its complement, f/2 at ninety degrees out of phase from f/2 and its complement) are applied to an XOR gate that combines them to generate a clock signal that has a duty cycle of approximately fifty percent and a frequency f, which is the same as the input clock signal.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: January 2, 2007
    Assignee: Intel Corporation
    Inventors: Hon-Mo Raymond Law, Rachael J. Parker
  • Patent number: 7158571
    Abstract: System and method for balancing video encoding tasks between multiple processors. The method may include receiving a real time video stream, performing picture level and upper processing on a main processor, executing a macroblock loop in parallel on a main processor and a co-processor, wherein executing includes processing a first group of video encoding tasks on the main processor and processing a second group of video encoding tasks on the co-processor, and outputting an encoded version of the real time broadcast. The method may be implemented on a system that includes a main processor, a co-processor, and an interface to receive the real time video stream, each coupled to one or more buses. The encoding may be performed according to the well known Moving Pictures Experts Group (MPEG) standards.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: January 2, 2007
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventors: Jason Naxin Wang, Masahito Yamane, Ikuo Tsukagoshi
  • Patent number: 7157230
    Abstract: An apparatus, compositions and related methods for sequencing a target nucleic acid are described. In certain embodiments, the apparatus is a microfluidic apparatus comprising an input chamber, microchannel, output chamber and a detection unit that is operatively connected to the microchannel. In preferred embodiments, the methods include hybridizing a target nucleic acid to one or more probe libraries, moving the hybridized target nucleic acid past the detector, and detecting bound probes. Probe libraries may comprise oligonucleotides or oligonucleotide analogs, preferably with each probe uniquely labeled. A linear order of labeled probes hybridized to the target nucleic acid can be detected and the target nucleic acid sequence deduced. In preferred embodiments, probe labels are detected by analysis of electron-induced fluorescence of probes labeled with conductive polymers.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: January 2, 2007
    Assignee: Intel Corporation
    Inventor: Eric C. Hannah
  • Patent number: 7159133
    Abstract: A system and corresponding method use a PAUSE instruction as a low power hint in a single threaded or multithreaded environment using “processor slow mode.” One embodiment actually lowers the frequency of the processor clock. Another embodiment virtually lowers the frequency of the processor clock by gating M clock cycles out of every N clock cycles. When all threads have issued a PAUSE instruction, the processor enters slow mode and remains there for a while. After this while, the processor returns to normal mode. Alternatively, an event, such as an interrupt or an exception, can cause the processor to return to normal mode from slow mode.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: January 2, 2007
    Assignee: Intel Corporation
    Inventors: Doron Orenstien, Ronny Ronen
  • Patent number: 7159220
    Abstract: A method and machine-readable medium measure requests by threads requesting a lock to differentiate “hot” and “cold” locks in accordance with the level of contention for the locks. A hardware accelerator manages access to hot locks to improve performance.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: January 2, 2007
    Assignee: Intel Corporation
    Inventor: Deep K. Buch
  • Patent number: 7159120
    Abstract: A system and method for protecting data within a portable electronic device to prevent unauthorized access to that data. Encryption of data within the portable electronic device and automatic erasure of data upon unauthorized attempted access is provided. A limited number of attempts to access the portable electronic device are allowed, and if exceeded, the data is automatically erased without notification. Data transfer functions of the portable electronic device are also disabled when the device is locked. Erasing of data is also provided if the portable electronic device is not synced with another device during a predetermined time period.
    Type: Grant
    Filed: November 19, 2001
    Date of Patent: January 2, 2007
    Assignee: Good Technology, Inc.
    Inventors: Alexander Victorovitch Muratov, Ronald Eugene Foley
  • Patent number: 7158479
    Abstract: A method that limits data flow between two network nodes to an amount within a window where a first portion of data within a first segment of the window is separated from a second portion of data within a second segment of the window by a third portion of data not within the window.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: January 2, 2007
    Assignee: Data Expedition, Inc.
    Inventor: Seth Bradley Noble
  • Patent number: 7158493
    Abstract: In one embodiment, the present invention comprises transmitting a broadcast burst in a broadcast channel from a base station of a radio communications system. The invention further comprises receiving a request burst from a user terminal, and transmitting a message burst from the base station to the user terminal from which the request was received. The message burst includes a description of the channels available on the radio communications system for receiving messages from user terminals.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: January 2, 2007
    Assignee: ArrayComm, LLC
    Inventors: Christopher Richard Uhlik, Michael Youssefmir, Mitchell D. Trott, Craig H. Barratt
  • Patent number: 7158158
    Abstract: Methods and apparatuses for nonlinear scaling of video images. To match the aspect ratios of a video image and the target display area, at least one embodiment of the present invention scales the video image according to one or more nonlinear functions along the horizontal direction and/or the vertical direction. In one embodiment, the nonlinear functions are such that the original aspect ratio of the video image is preserved near the center region (or strip) of the image and the image is gradually stretched (or compressed) as it is mapped to the edges. In one example, the scaling is implemented by the texture mapping functionality of OpenGL using graphics hardware. In one embodiment of the present invention, the nonlinear mapping is constructed according to a polynomial mapping; and, the coefficients of the polynomial are adjustable by a user to trade off distortion between the image center and the image edges, giving the user control over the location and the amount of distortion.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: January 2, 2007
    Assignee: Apple Computer, Inc.
    Inventors: Charles G. Fleming, Ralph T. Brunner
  • Patent number: 7157924
    Abstract: An on-die device is provided to measure/detect voltage fluctuations. This may include a control unit to generate differential reference signals (such as differential current signals), a first detector unit and a second detector unit. The differential reference signals may be generated based on a Vcc reference signal and a Vss reference signal. The first detector unit may receive the differential reference signals from the control unit and may receive first voltage signals (also called monitored signals) from a first device under test (DUT) located on the die or from a first area on the die. The first detector unit may provide (or output) a first signal indicative of a voltage fluctuation (voltage droop or overshoot) of the first voltage signals. The second detector unit may receive the differential reference signals from the control unit and may receive second voltage signals (also called monitored signals) from a second device under test (DUT) located on the die.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: January 2, 2007
    Assignee: Intel Corporation
    Inventors: Ali Muhtaroglu, Kent Callahan, Tawfik Arabi, Greg F. Taylor
  • Patent number: 7154170
    Abstract: Numerous embodiments of an apparatus and method for generating an identification feature are described. In one embodiment of the present invention, portions of an identification character printed with thermochromatic ink are distributed within a three-dimensional matrix of a multi-layer patch. The multi-layer patch may be disposed above a substrate.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: December 26, 2006
    Assignee: Intel Corporation
    Inventor: Patrick D. Boyd
  • Patent number: 7155716
    Abstract: In one embodiment, a method, system, and apparatus provide prioritized, fair, and weighted task scheduling for a shared execution queue. New tasks are prioritized according to their processing requirements and held in one or more queues according to their priority levels. Tasks are retrieved from each queue in a fair and weighted manner according to the priority level of each queue. In one embodiment, tasks of approximately equal total processing requirements/time are retrieved from each storage queue in a given task retrieval cycle.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: December 26, 2006
    Assignee: Intel Corporation
    Inventors: Honary Hooman, Dianne L. Steiger
  • Patent number: 7154854
    Abstract: In a wireless network system comprising a wired backbone network, an access point, and one or more associated wireless unit data coupled to the access point by way of a wireless transmission medium, a method of enabling fragmentation of data packet above a fragmentation threshold in one or more wireless units, comprising transmitting a message to the one or more wireless unit having a first control data that causes the one or more wireless units to implement fragmentation threshold in transmitting data packets to the access point. The message is preferably a multicast data packet intended for the one or more associated wireless units. The message may further include a specified fragmentation to be used, and also another control signal for enabling request to send (RTS) and clear to send (CTS) transmission by the one or more wireless units.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: December 26, 2006
    Assignee: Nortel Networks Limited
    Inventors: Jonathan M. Zweig, Darwin A. Engwer
  • Patent number: 7155487
    Abstract: A data distribution network includes a distribution-coordinating server and a plurality of client nodes. Each of the client nodes is configured to pull or push data from other clients or servers. The distribution-coordinating server monitors the locations of data sources and the statuses of data transfers between clients. By tracking the locations of data on the network and client data requests, the distribution-coordinating server can instruct the clients to perform data pushes and/or pulls to coordinate large-scale distributions of data among a multitude of clients. Metadata describing the data and clients can be exchanged between the clients and the distribution-coordinating server to coordinate the data distributions. Also, the distribution-coordinating server can be configured to coordinate data distributions through network security firewalls.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: December 26, 2006
    Assignee: Intel Corporation
    Inventors: Cedric Tan Yau, Mikhail Voloshin
  • Patent number: 7155483
    Abstract: A system is described in which, under certain conditions, a wireless data processing apparatus and/or the service to which the apparatus communicates, will enter a batch processing mode. Under the batch processing mode, the apparatus and/or service will combine a series of message transactions (e.g., message viewings, message deletions, . . . etc) before synchronizing with the service and/or apparatus, respectively. Various types of batch processing parameters may be set to determine whether the system should enter batch processing mode and/or how batch processing should be performed once batch processing mode has been entered.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: December 26, 2006
    Assignee: Good Technology, Inc.
    Inventors: John Friend, Roger Collins, Mike Bennett
  • Patent number: 7154621
    Abstract: An improved Internet delivery system for digitized photographs is described. The system embodies methodologies that speed the delivery of digitized images from photographic film scan centers to consumers across the Internet with high reliability. By delivering all the digital images to a more powerful centralized server infrastructure prior to the consumer's earliest opportunity to view them on-line, these images or pictures can be downloaded to a viewer of interest (e.g., user or family member) quickly enough to provide an appropriate Web response. Optimizations are also described that streamline the throughput with load balancing and provide virtually guaranteed uniform service with fail-over. In this manner, the system provides improved access, storage, and on-line availability of digital images.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: December 26, 2006
    Assignee: Lightsurf Technologies, Inc.
    Inventors: John Rodriguez, Brian Bodmer, Bryan Dube, Mark Tarantino, Jonah Kaj Fleming, Shekhar Kirani
  • Patent number: 7154118
    Abstract: A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed on a semiconductor substrate wherein the semiconductor body has a top surface on laterally opposite sidewalls. A semiconductor capping layer is formed on the top surface and on the sidewalls of the semiconductor body. A gate dielectric layer is formed on the semiconductor capping layer on the top surface of a semiconductor body and is formed on the capping layer on the sidewalls of the semiconductor body. A gate electrode having a pair of laterally opposite sidewalls is formed on and around the gate dielectric layer. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: December 26, 2006
    Assignee: Intel Corporation
    Inventors: Nick Lindert, Stephen M. Cea
  • Patent number: 7155575
    Abstract: A computer program product determines whether a loop has a high usage count. If the computer program product determines the loop has a high usage count, the computer program product determines whether the loop has an irregularly accessed load. If the loop has an irregularly accessed load, the computer program product inserts pattern recognition code to calculate whether successive iterations of the irregular memory load in the loop have a predictable access pattern. The computer program product implants conditional adaptive prefetch code including a prefetch instruction into the output code.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: December 26, 2006
    Assignee: Intel Corporation
    Inventors: Rakesh Krishnaiyer, Wei Li
  • Patent number: D534474
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: January 2, 2007
    Assignee: Lion's Wheel Industrial Corp.
    Inventor: Gi Beom Kim