Abstract: A method and apparatus for appliance host supported network-based application delivery is described. In one embodiment, a local client device requests access to a network-based application for use with data stored locally by the client. In one embodiment, an appliance host retrieves the network-based application from a remote server based upon the client request and negotiated access terms. In one embodiment, the appliance host operates much like a cache in that rather than automatically retrieving the client-requested network-based application from a remote server, the appliance host first determines if a local copy of the application is stored on the appliance host. If the network-based application is stored on the appliance host, whether pre-installed by the vendor or remaining from a previous client request, then the appliance host executes the locally stored version of the application rather than retrieving a copy from the remote server.

Abstract: A registry architecture for securely sharing personal devices among different users is disclosed. The registry architecture is a distributed architecture that includes at least one registry server communicating over a network with at least one personal device. The architecture provides verification and authorization of users and applications on personal devices registered with the registry server. In addition, secure migration of applications between a first personal device and at least one second personal device may be performed as a function of the registry architecture. Further, the ability to securely share a personal device among different users is provided by identification of potential users of the personal device within the registry architecture.

Abstract: An optical backplane system is described herein. In one embodiment, an exemplary system includes a backplane to interconnect multiple optical modules, multiple fiber interface modules (FIMs) having a back end inserted into multiple slots of the backplane respectively, each FIM having a front end to receive an incoming fiber carrying incoming optical signals and an outgoing fiber carrying outgoing optical signals from and to an optical network. The back end of the FIM extends the incoming and outgoing fibers to at least one of the multiple optical modules mounted via the backplane without significantly processing of the incoming and outgoing optical signals. Each of the fibers is capable of carrying multiple wavelengths of optical signals. Other methods and apparatuses are also described.

Abstract: A processing system for retrieving interrelated documents is described. The system comprises a document repository for storing a plurality of documents, a metadata repository for storing a plurality of metadata elements to represent relations between the documents, and a sociological analysis engine to identify relationships between the documents using the metadata elements from the metadata repository.

Abstract: A computer system includes a central processing unit (CPU) and a cache memory coupled to the CPU. The cache memory includes a plurality of compressible cache lines to store additional data.

Abstract: Resonance reduction arrangements to reduce the impact of power supply resonance on circuits, comprising a resonance sensor and a charge dumper, wherein upon the detection of the predetermined resonance by the resonance sensor at a circuit location, the charge dumper dumps charges at least one of from and to the circuit location, wherein the charge dumper comprises at least one gating transistor to dump the charges, the at least one gating transistor is directly connected to a first power supply line having a first potential and a second power supply line having a second potential of a different potential than the first potential.

Abstract: The specification discloses an apparatus comprising a die mounted on a substrate, the die being connected to the substrate by a plurality of wires, and a mold cap encapsulating the die and the plurality of wires, the mold cap comprising an electrically insulating portion encapsulating the wires and at least a portion of the die and a thermally conductive portion overmolded on the die and the electrically insulating portion. Also disclosed is a process comprising providing a die connected to a substrate by a plurality of wires, encapsulating the wires and at least a portion of the die in an electrically insulating material, and encapsulating the die, the wires and the electrically insulating material in a thermally conductive material. Other embodiments are disclosed and claimed.

Abstract: The present invention is a computer controlled display device. In one embodiment, the display device includes a flat panel display having an input for receiving display data. Additionally, a moveable assembly may be coupled to the display. The moveable assembly may provide at least three degrees of freedom of movement for the flat panel display device. Additionally, the moveable assembly may have a cross-sectional area, which is substantially less than a cross-sectional area of a display structure of the flat panel display.

Abstract: A voltage sense circuit and power supply regulation technique. In one aspect, a voltage sense circuit utilized in a power supply regulator includes a transformer including a sense winding and an output winding. A first diode is coupled to the sense winding, a first resistor is coupled to the first diode and a first capacitor coupled to the first resistor and the first diode. A second diode coupled to the first capacitor, the first resistor and the first diode. A second capacitor coupled to the second diode such that a voltage across the second capacitor is representative of a voltage across the output winding.

Abstract: In one embodiment, a method is provided. The method of this embodiment may include receiving an indication that a first device has been granted access to a bus. In response, at least in part, to the indication, a signal may be provided that may result in the coupling of a signal line of a second device to the bus. After the provision of the signal, the first device may configure the second device. Of course, many modifications, variations, and alternatives are possible without departing from this embodiment.

Abstract: Methods and apparatuses for assembling elements onto a substrate. The surfaces of the elements and/or the substrate are treated and the elements are dispensed over the substrate in a slurry. In one example of the invention, the substrate is exposed to a surface treatment fluid to create a surface on the substrate which has a selected one of a hydrophilic or a hydrophobic nature, and a slurry is dispensed over the substrate. The slurry includes a fluid and a plurality of elements (each of which includes a functional component). Each of the plurality of elements is designed to be received by a receptor region on the substrate. The dispensing of the slurry with the fluid occurs after the substrate is exposed to the surface treatment fluid, and the fluid is the selected one of a hydrophilic or a hydrophobic nature. In another example of the invention, a plurality of elements is exposed to a surface treatment fluid to create surfaces on the elements having a selected one of a hydrophilic or a hydrophobic nature.

Abstract: A system having a first device and a second device coupled to a single wire bus is described. The second device is operable to receive power from the single wire bus that is due to the first device driving the bus. The second device also communicates with the first device using the single wire bus.

Abstract: An apparatus and method for performing data access in accordance with memory access patterns are described. In one embodiment, the method includes the determination, in response to a memory access instruction, of a memory access pattern of data requested by the memory access instruction. Once the memory access pattern is determined, the data requested by the memory access instruction is accessed according to the determined memory access pattern. Finally, once the data is accessed, the data is processed according to the memory access instruction. Accordingly, in this embodiment of the present invention, data is accessed according to memory access patterns including zig-zag patterns scan, Zerotree scan, bit plane extraction, fine granularity scalability or the like.

Abstract: A method and apparatus for queuing control of variable bandwidth communications channels. The apparatus detects a change from a first bandwidth to a second bandwidth of a communication channel. Finally a quality of service controller is adjusted to compensate for the change from a first bandwidth to a second bandwidth.

Abstract: Transmission line impedance matching is described for matching an impedance discontinuity on a transmission signal trace. The apparatus includes a transmission signal trace and a non-transmission trace. The transmission signal trace has an impedance discontinuity, a first length, and a predetermined first width. The non-transmission trace is disposed near the transmission signal trace at a region corresponding to the impedance discontinuity. The non-transmission trace has a second length that is substantially less than the first length of the transmission signal trace. Additionally, the non-transmission trace is configured to be electromagnetically coupled to the transmission signal trace in the presence of a current on the transmission signal trace to provide a matched impedance on the transmission signal trace.

Abstract: A method and apparatus for hierarchical circuits with different switching decisions is described. In one embodiment, a computer implemented method provides for receiving a first and second packet on a virtual connection that traverses said network element, the first packet and the second packet being of a first traffic type that corresponds to the virtual connection, the first packet's payload being a third packet of a second traffic type and the second packet's payload being a fourth packet of a third traffic type, processing the first and the second packet with a first traffic type function, separating the third packet and the fourth packet into different traffic flows based on their traffic types, applying a first set of one or more features to the third packet, and applying a second set of one or more features to the fourth packet.

Abstract: A method and system for storing secure data in a multi-time programmable, non-volatile electrically-alterable memory device are disclosed. Accordingly, in an embodiment, a memory device may include a data register with a fixed N-bit pattern, comparator logic, control logic, and an array of non-volatile electrically-alterable memory cells. Each memory cell includes a floating gate to store an electronic charge representing the logical state of the memory cell. The plurality of memory cells may be logically partitioned to include an N-bit secure lock and a plurality of memory cells for storing secure data. The random bit values stored in the N-bit secure lock are read, and compared with the fixed N-bit pattern stored in the data register. If the N-bit patterns do not match, the control logic allows the plurality of memory cells for storing secure data to be programmed with secure data.

Abstract: A method and apparatus for supporting heterogeneous agents in on-chip busses. In one embodiment, the method includes the detection of a bus arbitration event between at least a first bus agent and a second bus agent. In one embodiment, a bus arbitration event is detected when at least the first bus agent and the second bus agent assert their respective bus request signals in a single clock cycle. Once a bus arbitration event is detected, bus ownership may be granted to both the first bus agent and the second bus agent, when the first bus agent and the second bus agent have different grant-to-valid latencies. In the embodiment, heterogeneous bus agents may coexist on a bus without requiring wasted or unused bus cycles following establishment of bus ownership. Other embodiments are described and claimed.

Abstract: An architecture having a distributed and replicated hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is composed of a number of cells that perform logical functions on input signals. A set of block connectors are used to provide connectability between cells and accessibility to a hierarchical routing network. Uniformly distributed layers of routing network lines are used to provide connections. Switching networks provide connectability between the routing network lines. Additional uniformly distributed layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. Programmable bi-directional passgates are used as switches to control which of the routing network lines are to be connected.