Search Patents
  • Patent number: 7133287
    Abstract: An integrated heatsink and core power distribution mechanism. First and second power rails are disposed on opposite sides of one of more integrated circuits on a printed circuit board (PCB). The power rails are electrically coupled to a power supply and the integrated circuits. At the same time, the power rails are used to thermally couple one or more heatsinks to the integrated circuit(s). Each power rails includes at least one slot configured to receive a flange on the heatsink(s). In situations under which different voltages are supplied via the power rails, means are provided to electrically insulate at least one power rail from the heatsink(s) while maintaining thermal coupling to the power rails. In one embodiment, a split-rail configuration is used, wherein the power rail includes multiple conductive sections separated by one or more insulator sections. The scheme is well-suited for modular board/blade architectures, such as the Advanced Telecommunications Architecture (ATCA).
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: November 7, 2006
    Assignee: Intel Corporation
    Inventors: Edoardo Campini, William F. Handley, Mark D. Summers, Javier Leija
  • Patent number: 7132739
    Abstract: Systems and methods for encapsulating a stack of semiconductor dice are described. A stack of semiconductor dice may be formed, for example by attaching die to flexible printed circuit supports attached to frames and stacking the supports, and then encapsulated by flowing a liquid encapsulant around the stack of dice and solidifying the liquid encapsulant. The die supports may contain encapsulant flow openings, such as rectangular slits, that allow the liquid encapsulant to flow around the stack of dice.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: November 7, 2006
    Assignee: Intel Corporation
    Inventors: Masayuki Akiba, Kinya Ichikawa, Jiro Kubota, Takashi Kumamoto
  • Patent number: 7131963
    Abstract: A catheter device and method, in which a first lumen coupled to a balloon, a second lumen coupled to the first lumen, the second lumen having a distal opening to dispense an oxygenated infusate, and a third lumen coupled to the second lumen and coupled to a second balloon. The second balloon restricts the flow of the oxygenated infusate, and the oxygenated infusate provides oxygen to tissue at a distal end of said catheter device.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: November 7, 2006
    Assignee: Advanced Cardiovascular Systems, Inc.
    Inventor: Gregory Matthew Hyde
  • Patent number: 7132222
    Abstract: Process for writing on a material, in which said material is irradiated by means of a beam of light ions, such as for example He+ ions, said beam of light ions having an energy of the order of or less than a hundred keV, wherein this material comprises a plurality of superposed thin-layers, at least one of said thin layers being magnetic and in that one or more regions having sizes of the order of 1 micrometer or less are irradiated, the irradiation dose being controlled so as to be a few 1016 ions/cm2 or less, the irradiation modifying the composition of atomic planes in the material at one or more interfaces between two layers of the latter.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: November 7, 2006
    Assignee: Centre National de la Recherche Scientifique (CNRS)
    Inventors: Claude Chappert, Harry Bernas, Jacques Ferre
  • Patent number: 7131843
    Abstract: An apparatus for movably joining structures is disclosed. In one embodiment of the invention, the apparatus provides at least one rotational degree of freedom of movement, while providing electrical coupling. In another embodiment of the invention, the apparatus provides at least two rotational degrees of freedom of movement.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: November 7, 2006
    Assignee: Lucesco Lighting, Inc.
    Inventor: John Gee Tang
  • Patent number: 7134070
    Abstract: One embodiment of a method may include partitioning data into segments of the data, storing in memory a set of checksums of the segments of the data, selecting a portion of the data, and determining a checksum of the portion of the data. The portion of the data may comprise a subset of the segments of the data and/or at least one part of at least one segment of the data. The checksum of the portion of the data may be determined, based, at least in part, upon a checksum of the subset of the segments and/or a checksum of the at least one part of the at least one segment. The checksum of the subset of the segments may be based, at least in part, upon respective checksums, read from the checksums stored in the memory, of segments of the data comprised in the subset of the segments.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: November 7, 2006
    Assignee: Intel Corporation
    Inventors: Anshuman Thakur, Roy Callum
  • Patent number: 7133301
    Abstract: A circuit that provides a method and apparatus to actively balance capacitor leakage current from series stacked capacitors and disconnects itself when stacked capacitors are configured for doubler operation. In one embodiment, the active circuit includes high voltage low current transistors, such as for example a PNP bipolar transistor and an NPN bipolar transistor, that are configured in a sink-source voltage follower arrangement with the bases of the transistors connected to a voltage divider network and referenced to a fraction of a DC input voltage with a very high impedance, low dissipative resistor divider network. In one embodiment, the emitters of the PNP and NPN transistors are both tied to the connection point between capacitors in the stack and provide an active sink-source drive, which maintains the voltage at this point to be bounded by the input reference voltages of sink-source followers.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: November 7, 2006
    Assignee: Power Integrations, Inc.
    Inventor: Arthur B. Odell
  • Patent number: 7133040
    Abstract: An apparatus and method for performing an insert-extract operation on packed data using computer-implemented steps is described. In one embodiment, a first data operand having a data element is accessed. A second packed data operand having at least two data elements is then accessed. The data element in the first data operand is inserted into any destination field of a destination register, or alternatively, a data element is extracted from any field of the source register.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: November 7, 2006
    Assignee: Intel Corporation
    Inventors: Mohammad Abdallah, Srinivas Chennupaty, Robert S. Dreyer, Michael A. Julier, Katherine Kong, Larry Mennemeier, Ticky S. Thakkar
  • Patent number: 7134125
    Abstract: A method of system resource management. The method including: determining a class of a device agent and determining whether the device agent is requesting a controlled system resource or a non-controlled system resource. If a controlled system resource is requested by the device agent, then the method further includes determining whether a first amount of the controlled system resource requested by the device agent plus a second amount of the controlled system resource currently consumed by the class of the device agent, if any, together exceed a class allocation amount for the controlled system resource that is permissible for the class of the device agent to consume.
    Type: Grant
    Filed: February 7, 2003
    Date of Patent: November 7, 2006
    Assignee: Intel Corporation
    Inventors: Michael A. Rothman, Vincent J. Zimmer
  • Patent number: 7133047
    Abstract: A system, method and apparatus to provide flexible texture filtering. A programmable texture filtering module is introduced into the graphics processing pipeline of a graphic coprocessor and graphic processor integrated with the host. A program from a defined instruction set may then be loaded into texture processing cores to process texture data consistent with the program.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: November 7, 2006
    Assignee: Intel Corporation
    Inventor: Kim Pallister
  • Patent number: 7133417
    Abstract: A switch apparatus and method according to the invention provides a carrier-class switching platform with a highly optimized data path and distributed signaling stacks to achieve high-density differential voice services. Incoming voice calls of any media type (TDM voice/fax, VoIP, VoATM, VoFR) are packetized and adapted for egress transmission of the same or another media type according to the service plan profile of the parties, and/or the instantaneous availability or cost of bandwidth resources. All calls are switched in an ATM switching core with QoS characteristics that can also be determined based on service plan profile. A call server handles call setup and management functions, as well as call signaling. Advantageously, the call server provides signaling relay functions to further support and enable the media conversion of voice calls.
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: November 7, 2006
    Assignee: Cisco Technology, Inc.
    Inventors: Ruey Kao, Venkat Kalkunte, Anant Kumar, Hy Quoc Pham
  • Patent number: 7133497
    Abstract: Lower bandwidth technology is used to determine whether a communication channel can support higher bandwidth technology. A signal generator generates a series of test signals that are associated with the higher bandwidth technology. The test signals are sampled to produce aliases that can be analyzed with lower bandwidth technology. Modem parameters are accessed from a modem's memory. The modem parameters are compared with a database containing information about whether a set of modem parameters indicates that a telephone local can support broadband devices.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: November 7, 2006
    Assignee: Intel Corporation
    Inventors: Karl I. Nordling, Vedavalli G. Krishnan, Mandayam G. Krishnan, Fred Schuckert, Wesley H. Smith, Don Carmon
  • Patent number: 7132311
    Abstract: Systems and methods for encapsulating a stack of semiconductor dice are described. A stack of semiconductor dice may be formed, for example by attaching die to flexible printed circuit supports attached to frames and stacking the supports, and then encapsulated by flowing a liquid encapsulant around the stack of dice and solidifying the liquid encapsulant. The die supports may contain encapsulant flow openings, such as rectangular slits, that allow the liquid encapsulant to flow around the stack of dice.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: November 7, 2006
    Assignee: Intel Corporation
    Inventors: Masayuki Akiba, Kinya Ichikawa, Jiro Kubota, Takashi Kumamoto
  • Patent number: 7131037
    Abstract: A system is provided to monitor network performances. The system maintains a database of performance abnormalities, alarms and events from a system of monitored elements. The system automatically identifies a possible cause of a specific alarm by correlating the specific alarm with a plurality of events using the database. The system displays the cause of the specific alarm. The database includes alarms and events of network devices, network systems, and network applications. The specific alarm consists of a notification of an occurrence of the plurality of events.
    Type: Grant
    Filed: June 5, 2002
    Date of Patent: October 31, 2006
    Assignee: Proactivenet, Inc.
    Inventors: Ronald Alexander LeFaive, Sridhar Sodem, Joe Scarpelli, Daniel Ketcham, Atul Garg
  • Patent number: 7130992
    Abstract: The present invention is a method and system to automatic loading program on a medium into memory for execution. In one embodiment, a mode word is configured. The insertion of the medium into a drive is detected based on the mode word. A program on the medium is started when insertion is detected. In another embodiment, a polling circuit in a chipset detects the insertion of the medium into the drive. A status bit is checked in response to an interrupt generated by the polling circuit. A flag in a memory is updated based on the status bit. A poll request by an operating system is responded.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: October 31, 2006
    Assignee: Intel Corporation
    Inventors: David I. Poisner, Joseph A. Bennett
  • Patent number: 7130911
    Abstract: According to one embodiment, a method is disclosed. The method includes receiving video data at an application program, receiving the video data to one or more memory buffers, decrypting the video data, and monitoring page table entries corresponding to the memory buffers to determine whether a second application program has accessed the memory buffers.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: October 31, 2006
    Assignee: Intel Corporation
    Inventor: Richard P. Mangold
  • Patent number: 7129729
    Abstract: Test modules, systems, and methods employing capacitors for the testing of the solder joint connections between a printed circuit board (PCB) and a socket of a device are presented in embodiments of the current invention. A test module having capacitors in parallel, and in particular embedded capacitors, can be used to test tied traces and their solder joint connections by measuring the total capacitance of the capacitors. Embodiments of the current invention present no-power tests that can be used with a variety of testing platforms and test fixtures, such as in-circuit testing (ICT) and manufacturing defect analysis (MDA.) Additionally, the test module can be used with a variety of sockets, such as a ball grid array, a pinned grid array, and a land grid array.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: October 31, 2006
    Assignee: Intel Corporation
    Inventors: Swee Cheng Ho, Teik Sean Toh, Tzyy Haw Tan
  • Patent number: 7129770
    Abstract: Methods and apparatuses associated with providing a bias voltage for an n-type and a p-type device. A high voltage may be received and used to derive a bias voltage that would reduce a risk of gate-aided breakdown of the drain-to-substrate channel-side pn-junction in an n-type device. The high voltage may be used to derive a bias voltage that would reduce the risk of gate-aided breakdown of the drain-to-substrate channel-side pn-junction in a p-type device.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: October 31, 2006
    Assignee: Intel Corporation
    Inventors: Gerald J. Barkley, Mase J. Taub
  • Patent number: 7130815
    Abstract: A system of performing reserve price reverse auctions is disclosed. In one embodiment, the reverse auction immediately ends if an offer below the reserve price is received. In another embodiment, the reverse auction continues until the buyer accepts an offer such that transaction with the accepted offer is consummated or a time period expires. If the time period expires and no offer is below the reserve price, then the user select from the received offers. If there is at least one offer below the reserve price and at least one other offer, then the system presents the user with the received offers and gives the user a time period to select one. If the user selects an offer, a transaction with the select offer is consummated. If no offer is selected, then a transaction with the lowest received offer is consummated.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: October 31, 2006
    Assignee: Softface, Inc. (a Subsidiary of Ariba, Inc.)
    Inventor: Piyush Gupta
  • Patent number: D531566
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: November 7, 2006
    Assignee: Lion's Wheel Industrial Corp.
    Inventor: Gi Beom Kim