Search Patents
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Patent number: 6346742Abstract: A chip-scale sensor package is described. In one embodiment, the chip-scale sensor package includes a semiconductor substrate having a sensor region, and a semiconductor cap having a recess. The semiconductor cap is bonded to the semiconductor substrate with a thermocompression bond to form a cavity therebetween. The semiconductor substrate is bonded to the semiconductor cap using different types of materials. The semiconductor substrate and/or the semiconductor cap may optionally include a semiconductor device such as an electronically trimmable integrated circuit fabricated thereon. In addition, the semiconductor substrate may optionally include an integral stress isolation flexible region for isolation of the sensor region.Type: GrantFiled: November 12, 1998Date of Patent: February 12, 2002Assignee: Maxim Integrated Products, Inc.Inventors: Janusz Bryzek, David W. Burns, Sean S. Cahill, Steven S. Nasiri
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Patent number: 6346842Abstract: A variable delay path circuit having delay paths of different lengths is disclosed. Any of the delay paths can be selected to match the operating conditions of the system. In one embodiment of the invention, a delay path circuit having two delay paths connects a driver and receiver. Each of the two delay paths contains sites at both ends for placing zero ohm resistors, solder or copper slugs. To select one of the two delay paths, zero ohm resistors, solder or copper slugs are placed in the sites at the ends of the desired delay path. The delay is then dictated by the time it takes for a clocking signal to travel the length of selected delay path.Type: GrantFiled: December 12, 1997Date of Patent: February 12, 2002Assignee: Intel CorporationInventors: Stephen H. Hall, Jr., Maynard C. Falconer
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Method and apparatus for distributing power in high frequency alternating current and direct current
Patent number: 6344987Abstract: A method for distributing power in an electronic system comprising of receiving power in a first domain at a connector of a peripheral device and converting the power to a second domain at the connector of the peripheral device is disclosed.Type: GrantFiled: March 16, 2000Date of Patent: February 5, 2002Assignee: Intel CorporationInventor: Josef C. Drobnik -
Patent number: 6345387Abstract: A method and apparatus are provided for controlling the execution of a software program. According to one embodiment, control flow information including multiple states associated with a software program is made accessible. Each of the states includes information indicative of desired control flow of the software program and information indicative of desired behavior of the software program. A determination is made if a current status of the software program has a predetermined relationship with an expected state of execution of the software program. Based upon the result of the determination and the information indicative of desired behavior, the software program is caused to perform an action and caused to transition from the current state to a next state. According to another embodiment, specification of a control flow architecture associated with a software program is simplified to the provision of certain control flow information that is accessible to a control flow engine.Type: GrantFiled: April 30, 1999Date of Patent: February 5, 2002Assignee: COSA Technologies, Inc.Inventor: Gordon E. Morrison
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Patent number: 6345232Abstract: The present invention is a method and apparatus to determine flight parameters of an aircraft. Data received from a global positioning system (GPS) receiver are converted to position data. The position data are filtered based on a least-squares fitting to generate smoothed position data which provide the flight parameters.Type: GrantFiled: April 27, 1999Date of Patent: February 5, 2002Inventors: Urban H. D. Lynch, Robert C. Ettinger
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Patent number: 6343289Abstract: A method and apparatus for efficiently searching a forwarding database or similar data structure are provided. According to one aspect of the present invention, the overall average time required to forward a packet from the ingress port of a network device to one or more egress ports may be reduced by attacking the worst case forwarding database search. Data is received at a first port of the network device and a search key is extracted from the data. Typically the search key includes one or more of a source or destination Internet Protocol (IP) address, a souce or destination Media Access Control (MAC) address, and/or a Virtual Local Area Network (VLAN) tag. Ultimately, the data is forwarded to a second port of the network device based upon a matching entry located by the search. The search includes retrieving keys from entries of the forwarding database and comparing the search key to the keys until a matching entry is located.Type: GrantFiled: July 17, 1998Date of Patent: January 29, 2002Assignee: Nortel Networks LimitedInventors: Van A. Hunter, Milan Momirov
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Patent number: 6340614Abstract: A method of forming a DRAM cell is disclosed. A heavily-doped region is formed in a semiconductor substrate. A first dielectric layer and a second dielectric layer are formed on the semiconductor substrate in sequence. A trench is next formed in the semiconductor substrate and also forming source/drain regions. First spacers with dopant source material are formed on sidewalls of the trench. After forming a gate dielectric layer within the trench, a first plug is formed on the gate dielectric layer. After forming an isolation film on the first plug and forming source/drain extensions, a second plug is formed on the isolation film. After removing the second dielectric layer, second spacers and third spacers are formed on sidewalls of the first spacers. After removing the second spacers and upper portions of the first spacers, a capacitor is formed on the transistor.Type: GrantFiled: October 3, 2000Date of Patent: January 22, 2002Assignee: Vanguard International Semiconductor CorporationInventor: Horng-Huei Tseng
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Patent number: 6340533Abstract: A synthetic-type spin-valve MR sensor having a pinned magnetic layer with a multi-layer film structure. In one embodiment, on a substrate are formed by layering a free magnetic layer, a pinned magnetic layer including first and second ferromagnetic films, which are mutually coupled antiferromagnetically and which enclose a nonmagnetic coupling film. A nonmagnetic conductive layer is enclosed between these two magnetic layers. An antiferromagnetic layer neighbors the pinned magnetic layer. The first ferromagnetic film neighboring the antiferromagnetic layer is formed from a high-resistivity Co-base material. By making the products of the saturation magnetization and the film thickness of the first ferromagnetic layer and the second ferromagnetic layer substantially equal, the apparent magnetic moment of the pinned magnetic layer as a whole is zero, and the magnetostatic action on the free magnetic layer is eliminated or reduced.Type: GrantFiled: November 19, 1999Date of Patent: January 22, 2002Assignee: Read-Rite CorporationInventors: Masaki Ueno, Hideyasu Nagai, Tatsuo Sawasaki, Fuminori Hikami
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Patent number: 6339544Abstract: An apparatus including a contact on a substrate, a dielectric material overlying the contact, a phase change element overlying the dielectric material on a substrate, and a heater element disposed in the dielectric material and coupled to the contact and the phase change element, wherein a portion of the dielectric material comprises a thermal conductivity less than silicon dioxide. A method including introducing over a contact formed on a substrate, a dielectric material, a portion of which comprises a thermal conductivity less than silicon dioxide, introducing a heater element through the dielectric material to the contact, and introducing a phase change material over the dielectric material and the heater element.Type: GrantFiled: September 29, 2000Date of Patent: January 15, 2002Assignee: Intel CorporationInventors: Chien Chiang, Guy C. Wicker
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Patent number: 6339248Abstract: A photodiode with an optimized floating P+ region for a CMOS image sensor. The photodiode is constructed with a P+/Nwell/Psub structure. The Nwell/Psub junction of the photodiode acts as a deep junction photodiode which offers high sensitivity. The P+ floating region passivates the silicon surface to reduce dark currents. Unlike a traditional pinned photodiode structure, the P+ region in the present invention is not connected to the Pwell or Psub regions, thus making the P+ region floating. This avoids the addition of extra capacitance to the cell. The photodiode may be included as part of an active pixel sensor cell, the layout of which is fully compatible with the standard CMOS fabrication process. This type of active pixel sensor cell includes the photodiode, and may be configured with a three transistor configuration for reading out the photodiode signals.Type: GrantFiled: November 15, 1999Date of Patent: January 15, 2002Assignee: Omnivision Technologies, Inc.Inventors: Tiemin Zhao, Xinping He, Datong Chen
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Patent number: 6339616Abstract: A method and apparatus for pixel-by-pixel motion and/or still video data compression and decompression. Each pixel may be encoded as static, new, or direcionally estimated. Directionally estimated pixels are encoded with a value corresponding to a direction in a reduced set of substantially unique directions, wherein each direction may correspond to one or a combination of pixels. Directionally estimated pixels are further encoded using an adaptive variable length code (VLC), while static pixels and new pixels are encoded using run-lenth (RL) coding and delta coding techniques, respectively. Performance parameters, such as compression ratio, quality, etc., may be monitored to dynamically and adaptively update compression thresholds. Pixel processing may be performed in a plurality of directions to improve performance.Type: GrantFiled: May 30, 1997Date of Patent: January 15, 2002Assignees: Alaris, Inc., G. T. Technology, Inc.Inventor: Sergey I. Kovalev
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Patent number: 6339836Abstract: A flexible and extensible automated design partitioning mechanism that facilitates simulation sessions employing two or more simulators is provided. A simulation backplane includes partitioning logic that identifies the design blocks of an overall design pertaining to each of a plurality of simulators. Once the partitions have been identified, nets that cross simulator boundaries (e.g., mixed nets) are determined and inter-simulator connectivity information is generated for the simulators. According to one aspect of the present invention, the partitioning logic is able to accomodate arbitrary (e.g., instance-based) partitioning. A design source expressed in a design representation upon which a first simulator may operate is received. Design blocks to be partitioned to each of a plurality of solvers are identified based upon one or more partitioning directives and the design source. A first instance of a cell is assigned to a first solver and a second instance of the cell is assigned to a second solver.Type: GrantFiled: August 24, 1998Date of Patent: January 15, 2002Assignee: Mentor Graphics CorporationInventors: Karl Eisenhofer, Kevin Nazareth, Peter Odryna
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Patent number: 6337999Abstract: A digital clipper is highly oversampled to decrease aliasing and increase accuracy. The difference between the clipper's input and output is then downsampled and added to the delayed, unclipped signal at 1× sample rate to achieve clipping. Filters operating at 1× can be placed in series with the downsampled differentially-clipped signal to achieve overshoot compensation, bandlimiting of the clipped signal, and other goals.Type: GrantFiled: December 18, 1998Date of Patent: January 8, 2002Assignee: Orban, Inc.Inventor: Robert A. Orban
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Patent number: 6337788Abstract: A circuit protects a power conversion system with a feedback control loop from a fault condition. The circuit has an oscillator having an input for generating a signal with a frequency and a timer connected to the oscillator input and to the feedback control loop. The timer disables the oscillator after a period following the opening of the feedback control loop to protect the power conversion system.Type: GrantFiled: November 16, 1998Date of Patent: January 8, 2002Assignee: Power Integrations, Inc.Inventors: Balu Balakrishnan, Alex Djenguerian, Leif Lund
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Patent number: 6338069Abstract: A method and apparatus for managing functions (e.g., that express business rules) to allow calling functions, maintaining functions, and providing of an execution framework for functions. In one embodiment, there are a number of functions to be maintained. An object technology infrastructure is formed to store data and metadata for the functions. For example, metadata about a function can include data describing what that function does, a “cost” associated with that function, how to execute that function, the input and output parameters required by that function. The exposure of the metadata regarding the functions' input and output parameters allows an engine to track input/output relationships between the functions and, in essence, define the order of execution.Type: GrantFiled: December 11, 1998Date of Patent: January 8, 2002Assignee: Daman, Inc.Inventor: Bhalchandra Ghatate
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Patent number: 6335627Abstract: An apparatus for testing an electrical connection between a first electrical contact on a first side of an electronics package substrate and a first electrical terminal on a second, opposing side of the substrate. A holder is provided which is capable of releasably receiving and holding a substrate. At least a first electrical pin is located on the holder. The first electrical pin is positioned to contact the first electrical contact on the first side of the substrate. A support structure is mounted to the holder. An electrical probe is mounted to the support structure. The electrical probe is movable relatively to the support structure between a first position and a second position. In the first position the electrical probe is distant from the first electrical terminal on the second side of the substrate. In the second position the electrical probe is in contact with the first electrical terminal.Type: GrantFiled: April 13, 1998Date of Patent: January 1, 2002Assignee: Intel CorporationInventor: Stephen Bradford Gospe
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Patent number: 6335128Abstract: A method and apparatus for deep sub-micron layout optimization is described. Components of an integrated circuit (IC) design (e.g., gates) can be identified and manufactured using a phase shifting process to improve circuit density and/or performance as compared to a circuit manufactured without using phase shifting processes. In one embodiment, a first mask (e.g., a phase shift mask) is generated that includes the component to be manufactured using the phase shifting process. A second mask (e.g., a trim mask) is also generated to further process the structure created using the first mask. Both masks are defined based on a region (e.g., a diffusion region) in a different layer of the integrated circuit layout than the structure (e.g., the gate) being created with the phase shifting process.Type: GrantFiled: September 28, 1999Date of Patent: January 1, 2002Inventors: Nicolas Bailey Cobb, Kyohei Sakajiri
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Patent number: 6335661Abstract: A balanced input circuit which is used with an operational amplifier to obtain the difference between two input signals. In a temperature sensor application, one input signal is proportional to absolute temperature (PTAT) and one signal is complimentary to absolute temperature (CTAT) with the CTAT signal being the base-emitter voltage (Vbe) of a bipolar transistor. In this application the operational amplifier output is the PTAT signal minus Vbe times a scale factor determined by the feedback loop of the operational amplifier.Type: GrantFiled: May 11, 2000Date of Patent: January 1, 2002Assignee: Maxim Integrated Products, Inc.Inventor: Bruce Michael Furman
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Patent number: 6336159Abstract: A method and apparatus for transferring data between bus agents in a computer system. The present invention includes transmitting a control signal, from a first agent to a second agent, via a first transfer protocol; and, transmitting data corresponding to the control signal, from the first agent to the second agent, via a second transfer protocol. In one embodiment, the control signals are transmitted from the first agent to the second agent via a synchronous transmission with respect to a bus clock; and, the data is transmitted via an asynchronous transmission with respect to the bus clock, which has a data width greater than the synchronous transmission. In addition, in one embodiment of the present invention, the synchronous transmission is a common clock data transfer protocol, and the asynchronous transmission is a source clock data transfer protocol.Type: GrantFiled: January 13, 1998Date of Patent: January 1, 2002Assignee: Intel CorporationInventors: Peter D. MacWilliams, William S. Wu, Dilip K. Sampath, Bindi A. Prasad
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Patent number: 6333749Abstract: A computer-assisted technique for constructing a three-dimensional model on top of one or more images (e.g., photographs) such that the model's parameters automatically match those of the real world object depicted in the photograph(s). Camera parameters such as focal length, position, and orientation in space may be determined from the images such that the projection of a three-dimensional model through the calculated camera parameters matches the projection of the real world object through the camera onto the image surface. Modeling is accomplished using primitives, such as boxes or pyramids, which may be intuitively manipulated to construct the three-dimensional model on a video display or other display screen of a computer system with a two-dimensional input controller (e.g., a mouse, joystick, etc.) such that the, displayed three-dimensional object manipulation emulates physical three-dimensional object manipulation.Type: GrantFiled: April 17, 1998Date of Patent: December 25, 2001Assignee: Adobe Systems, Inc.Inventors: Tilman Reinhardt, Robert Seidl