Abstract: A test circuit operable to examine both differential outputs and single outputs of a device under test (DUT), the circuit comprises a first circuit having as inputs a first output of the DUT and a first set of independent reference voltages, and an output of the first circuit coupled to a plurality of comparators. The test circuit further comprises a second circuit having as inputs a second output of the DUT and a second set of independent reference voltages, and an output of the second circuit coupled to the plurality of comparators. The test circuit further comprises a select circuit coupled to outputs of the comparators, the output of the first circuit and the output of the second circuit. The select circuit outputting the outputs of the first circuit and the second circuit or outputting the outputs of the comparators.

Abstract: The present invention is a method and apparatus for tracking a frequency of a signal. The received signal is converted to an intermediate frequency (IF) signal using a frequency reference. An automatic gain control (AGC) is provided to the IF signal. The AGC generates a control value. The magnitude and phase parameters of the IF signal are estimated. A frequency error is estimated based on the phase parameter. A control quantity is generated based of the control value, the estimated magnitude parameter and the estimated frequency error. The control quantity adjusts the frequency reference.

Abstract: A video data recordable having integrated channel guides allowing a user to control recording and storage of television signals into personal channels for later playback and viewing. In the described embodiment, the user may specify criteria for recording of shows from an input source such as a broadcast signal and shows are then selected based on the user specified criteria and recorded for later playback. Storage of the shows may be organized into personal channels in order to facilitate later playback, e.g., the user may specify a channel of action movies, a channel of nature programming, a channel for sports, etc. The shows to be recorded may also have a predefined format which may be used to ease playback of recorded programming by allowing the user to easily locate and playback sections of programming of interest.

Abstract: A point-of-presence (POP) call center system capable of answering, servicing, queuing and routing of calls at local points of presence to reduce communications costs and enhance operational efficiency for toll-free inbound call centers. The POP call center system includes a set of point-of-presence call center gateways distributed at points of presence close to the point of call origination that are connected by a virtual private network to premises call center gateways at business locations where the call centers reside.

Abstract: A system is provided for controlling a multicast session in a network having multiple network nodes. The system selects one of the network nodes as a control point associated with the multicast session. Identity of the control point is then advertised to all network nodes in a particular area. The control point determines multicast control information for the multicast session. Multicast control information determined by the control point is transmitted to the network nodes participating in the multicast session. The multicast control information may include network nodes participating in the multicast session, multicast reflection points, or instructions for transmitting multicast data to members of the multicast session. Updating of the multicast control information occurs in response to network changes. The system may provide a secondary control point that maintains a copy of control information associated with the multicast session.

Abstract: Disclosed is a method for servicing a lawn sprinkler head removed from a sprinkler system. Included within a servicing kit is a controller that may be used to regulate the flow of water through the sprinkler head remotely from the sprinkler system, a plug to secure the hole in the sprinkler system from where the sprinkler head was removed, a spacer that may be used to retain the nozzle of the sprinkler head in the deployed position, and a cleaning tool that may be used to dislodge debris from the nozzle water exit perforations. Other features are disclosed.

Abstract: An improved programmable logic device and interconnect architecture is provided. In one embodiment an interconnect network provides programmable routing between calls. In one embodiment the interconnect network includes first routing lines of a first level of routing lines, second routing lines of a second level of routing lines and third routing lines of a third level of routing lines. The first and second routing lines are programmably and bidirectionally coupled to the third routing lines such that signals are selectively driven from either the first or second routing lines to the third routing lines and signals are selectively driven from the third routing lines to the first routing lines and second routing lines.

Abstract: A method and apparatus for avoiding tag compares when writing to a cache. In a cache hierarchy, location information of the cache entries are linked and supplied to the other caches, during caching of the data from memory. When the processor is ready to update the content of the memory location, the location information loaded into a write buffer allows the write buffer to update the cache(s), without the need for tag comparisons to determine if particular entries are present. The avoidance of the tag compare operation during cache update saves a clock cycle, so that overall processor performance is improved.

Abstract: An order promising scheme includes the ability to query a hierarchical scheduling module configured to generate workflows for a series of jobs to be processed in a manufacturing environment to determine the earliest reasonable completion time for one or more additional jobs to be processed in the manufacturing environment. The querying may involve first querying an aggregate planning level of the hierarchical scheduling module to determine whether the one or more additional jobs may be processed. Further, the querying may require querying a detailed scheduling level of the hierarchical scheduling module to determine whether the one or more additional jobs may be processed in the event that the aggregate planning level returns a negative reply to the first query by the order promising module. The querying of the hierarchical scheduling module may be performed in response to user inquiries submitted via a user interface.

Abstract: A method and apparatus for increasing the throughput and forwarding rate of a switch fabric are provided. According to one aspect of the present invention, a packet forwarding device includes a plurality of port interface devices (PIDs), memory access circuitry, and a management device. The PIDs are configured to fragment packets into cells. A portion of a cell serves as forwarding information. The memory access circuitry receives cell data from the PIDs to receive cell data. The memory access circuitry includes a data interface that outputs cell data and an independent control interface that outputs forwarding information. A memory is coupled to the data interface of the memory access circuitry to temporarily store the cell data received from the memory access circuitry. A management device is coupled to the independent control interface of the memory access circuitry to receive the forwarding information. The management device employs the forwarding information to organize cells into one or more groups.

Abstract: An electronic catalog requisition system includes software for efficiently selecting items from a database. The software accepts search terms from a user, and then executes a sequence of search strategies on the database which may include a proximity search, a word count search, and a fuzzy logic search. The sequence is terminated when a search algorithm has uncovered at least one match. Each database entry has a corresponding product category. A list of categories from each of the matching products is dynamically compiled and displayed to the user. The user can page through the list of displayed matches, or alternatively can create a subset of the list by selecting only the items within one of the categories. In addition, the user can further refine the list of items by selecting those items having a particular attribute. The software can also maintain a list of synonyms for attributes as an aid for finding appropriate matches within the database.

Abstract: A GTL I/O transceiver circuit having a pulsed latch receiver. A pulse generator generate a first pulse and a second pulse within the first pulse in response to a rising edge of the bus clock. The first pulse turns on the differential amplifier of the receiver circuit just long enough to provide a valid amplifier output signal. The second pulse controls a tristate latch such that the value of the amplifier output signal is latched before the differential amplifier is turned off. The pulsed latch receiver turns the differential amplifier on for only a fraction of the period of the bus clock such that power dissipation of the pulsed latch receiver circuit is significantly reduced. By using the pulsed latch receiver in VLSI components having hundreds of I/Os, significant reduction in overall component power dissipation can be achieved and static DC power is eliminated. The GTL I/O transceiver is useful for interfacing VLSI CMOS components to a terminated bus.

Abstract: A cryptographic accelerator for handling instruction-intensive bit permutations. The cryptographic accelerator comprises a selector and a plurality of buses coupled to the selector. Herein, at least one of the plurality of buses includes signal lines routed to perform a bit permutation operation incoming data. The bit permutation operation is one of a plurality of operations associated with a symmetric key function.

Abstract: In one embodiment of the invention, a delay circuit generates a plurality of delay strobe signals from a plurality of data strobe signals during an operational mode and a calibration signal from a reference signal by an interval during a calibration mode. The plurality of delay strobe signals clocks a plurality of data into a plurality of registers. A calibrator adjusts the interval according to a timing relationship between the calibration signal and the reference signal.

Abstract: A method and apparatus for providing relationship objects and various features to relationship and other objects. According to one aspect of the invention, a system is described that includes a number of base objects that contain data describing disparate sources of an enterprise. In addition, the system includes a number of relationship objects that express relationships between different ones of the plurality of base objects.

Abstract: A document-collaboration videoconferencing system between a first and a second conference attendee. In one embodiment, the system comprises a document server, a local presenter computing system, and a conferencing computing system. In this embodiment, the local presenter computing system transfers a document to the document server over a network, and the first conferencing system copies such document over the network from the document server.

Abstract: The described DC to AC inverter efficiently controls the amount of electrical power used to drive a cold cathode fluorescent lamp (CCFL). The output is a fairly pure sine wave which is proportional to an input control voltage. The output waveform purity is ensured by driving a symmetrical rectangular waveform into a second-order, low pass filter at the resonant frequency of the filter for all conditions of line voltage and delivered power. Operating stress on the step-up transformer is minimized by placing the load (lamp) directly across the secondary side of the transformer. When configured to regulate delivered power, the secondary side may be fully floated which practically eliminates a thermometer effect on the operation of the lamp. All of the active elements, including the power switches, may be integrated into a monolithic silicon circuit.

Abstract: A high throughput memory access port is provided. The port includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The port allows memory read and write requests to be pipelined in order to hide the effects of memory access latency. In particular, the port allows bus transactions to be performed in either a non-pipelined mode, such as provided by PCI, or in a pipelined mode. In the pipelined mode, one or more additional memory access requests are permitted to be inserted between a first memory access request and its corresponding data transfer. In contrast, in the non-pipelined mode, an additional memory access request cannot be inserted between a first memory access request and its corresponding data transfer.

Abstract: A method and apparatus for clocking an integrated circuit. The apparatus includes an integrated circuit having a clock driver disposed in a first side of a semiconductor substrate, and a clock distribution network coupled to the clock driver and disposed in a second side of the semiconductor substrate to send a clock signal to clock an area of the integrated circuit.

Abstract: A method and apparatus for performing a move mask operation. The present invention provides a method and apparatus for performing operations on packed data values of a first size and format and conversion of the results to data of a second size and format by eliminating redundant data. The present invention is useful, for example, when comparisons are performed on floating point data that is typically larger (e.g., 64 bits) than integer data (e.g., 32 bits) and integer operations are preformed based on the result. Because many processors branch based on integer data, the comparison results stored as floating point data must be transferred to an integer register prior to branching. The present invention takes advantage of redundancy of the floating point comparison results to transfer enough data to convey the comparison result to integer registers with a single instruction.